| 9df5ba05 | 18-Feb-2022 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(ls1088a): add new SoC platform ls1088a
LS1088A is a cost-effective, powerefficient, and highly integrated SoC device featuring eight extremely power-efficient 64-bit ARM Cortex-A53 cores with E
feat(ls1088a): add new SoC platform ls1088a
LS1088A is a cost-effective, powerefficient, and highly integrated SoC device featuring eight extremely power-efficient 64-bit ARM Cortex-A53 cores with ECC-protected L1 and L2 cache memories for high reliability, running up to 1.6 GHz.
This patch is to add ls1088a SoC support in TF-A.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: rocket <rod.dorris@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: Id9ebcdad1beab07ea81a41955edd4f471d6cf090
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| ceae3743 | 08-Mar-2021 |
Biwen Li <biwen.li@nxp.com> |
refactor(layerscape): refine comparison of inerconnection
Refine the code to be compatible with new CCN504 which is used by ls2088a.
Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Jiafei
refactor(layerscape): refine comparison of inerconnection
Refine the code to be compatible with new CCN504 which is used by ls2088a.
Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I2e2b3bbb9392862b04bf8a89dfb9575bf4be974a
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| 9550ce9d | 05-Jan-2021 |
Biwen Li <biwen.li@nxp.com> |
feat(layerscape): add CHASSIS 3 support for tbbr
Support CHASSIS 3.0(such as SoC LS1088A).
Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I6084
feat(layerscape): add CHASSIS 3 support for tbbr
Support CHASSIS 3.0(such as SoC LS1088A).
Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I60843bc4d604f0de1d91c6d3ad5eb4921cdcc91a
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