1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return 26 zero at all but the highest implemented exception level. Reads from the 27 memory mapped view are unaffected by this control. 28 29- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 30 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 31 ``aarch64``. 32 33- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies 34 one or more feature modifiers. This option has the form ``[no]feature+...`` 35 and defaults to ``none``. It translates into compiler option 36 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the 37 list of supported feature modifiers. 38 39- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 40 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 41 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 42 :ref:`Firmware Design`. 43 44- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 45 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 46 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 47 48- ``BL2``: This is an optional build option which specifies the path to BL2 49 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 50 built. 51 52- ``BL2U``: This is an optional build option which specifies the path to 53 BL2U image. In this case, the BL2U in TF-A will not be built. 54 55- ``RESET_TO_BL2``: Boolean option to enable BL2 entrypoint as the CPU reset 56 vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 57 entrypoint) or 1 (CPU reset to BL2 entrypoint). 58 The default value is 0. 59 60- ``BL2_RUNS_AT_EL3``: This is an implicit flag to denote that BL2 runs at EL3. 61 While it is explicitly set to 1 when RESET_TO_BL2 is set to 1 it can also be 62 true in a 4-world system where RESET_TO_BL2 is 0. 63 64- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the 65 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided. 66 67- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 68 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 69 the RW sections in RAM, while leaving the RO sections in place. This option 70 enable this use-case. For now, this option is only supported 71 when RESET_TO_BL2 is set to '1'. 72 73- ``BL31``: This is an optional build option which specifies the path to 74 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 75 be built. 76 77- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 78 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``, 79 this file name will be used to save the key. 80 81- ``BL32``: This is an optional build option which specifies the path to 82 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 83 be built. 84 85- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 86 Trusted OS Extra1 image for the ``fip`` target. 87 88- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 89 Trusted OS Extra2 image for the ``fip`` target. 90 91- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 92 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``, 93 this file name will be used to save the key. 94 95- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 96 ``fip`` target in case TF-A BL2 is used. 97 98- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 99 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``, 100 this file name will be used to save the key. 101 102- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 103 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 104 If enabled, it is needed to use a compiler that supports the option 105 ``-mbranch-protection``. Selects the branch protection features to use: 106- 0: Default value turns off all types of branch protection 107- 1: Enables all types of branch protection features 108- 2: Return address signing to its standard level 109- 3: Extend the signing to include leaf functions 110- 4: Turn on branch target identification mechanism 111 112 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 113 and resulting PAuth/BTI features. 114 115 +-------+--------------+-------+-----+ 116 | Value | GCC option | PAuth | BTI | 117 +=======+==============+=======+=====+ 118 | 0 | none | N | N | 119 +-------+--------------+-------+-----+ 120 | 1 | standard | Y | Y | 121 +-------+--------------+-------+-----+ 122 | 2 | pac-ret | Y | N | 123 +-------+--------------+-------+-----+ 124 | 3 | pac-ret+leaf | Y | N | 125 +-------+--------------+-------+-----+ 126 | 4 | bti | N | Y | 127 +-------+--------------+-------+-----+ 128 129 This option defaults to 0. 130 Note that Pointer Authentication is enabled for Non-secure world 131 irrespective of the value of this option if the CPU supports it. 132 133- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 134 compilation of each build. It must be set to a C string (including quotes 135 where applicable). Defaults to a string that contains the time and date of 136 the compilation. 137 138- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 139 build to be uniquely identified. Defaults to the current git commit id. 140 141- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 142 143- ``CFLAGS``: Extra user options appended on the compiler's command line in 144 addition to the options set by the build system. 145 146- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 147 release several CPUs out of reset. It can take either 0 (several CPUs may be 148 brought up) or 1 (only one CPU will ever be brought up during cold reset). 149 Default is 0. If the platform always brings up a single CPU, there is no 150 need to distinguish between primary and secondary CPUs and the boot path can 151 be optimised. The ``plat_is_my_cpu_primary()`` and 152 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 153 to be implemented in this case. 154 155- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 156 Defaults to ``tbbr``. 157 158- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 159 register state when an unexpected exception occurs during execution of 160 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 161 this is only enabled for a debug build of the firmware. 162 163- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 164 certificate generation tool to create new keys in case no valid keys are 165 present or specified. Allowed options are '0' or '1'. Default is '1'. 166 167- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 168 the AArch32 system registers to be included when saving and restoring the 169 CPU context. The option must be set to 0 for AArch64-only platforms (that 170 is on hardware that does not implement AArch32, or at least not at EL1 and 171 higher ELs). Default value is 1. 172 173- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 174 registers to be included when saving and restoring the CPU context. Default 175 is 0. 176 177- ``CTX_INCLUDE_MTE_REGS``: Numeric value to include Memory Tagging Extension 178 registers in cpu context. This must be enabled, if the platform wants to use 179 this feature in the Secure world and MTE is enabled at ELX. This flag can 180 take values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 181 Default value is 0. 182 183- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV 184 registers to be saved/restored when entering/exiting an EL2 execution 185 context. This flag can take values 0 to 2, to align with the 186 ``FEATURE_DETECTION`` mechanism. Default value is 0. 187 188- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer 189 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers 190 to be included when saving and restoring the CPU context as part of world 191 switch. This flag can take values 0 to 2, to align with ``FEATURE_DETECTION`` 192 mechanism. Default value is 0. 193 194 Note that Pointer Authentication is enabled for Non-secure world irrespective 195 of the value of this flag if the CPU supports it. 196 197- ``DEBUG``: Chooses between a debug and release build. It can take either 0 198 (release) or 1 (debug) as values. 0 is the default. 199 200- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 201 authenticated decryption algorithm to be used to decrypt firmware/s during 202 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 203 this flag is ``none`` to disable firmware decryption which is an optional 204 feature as per TBBR. 205 206- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 207 of the binary image. If set to 1, then only the ELF image is built. 208 0 is the default. 209 210- ``DISABLE_MTPMU``: Boolean option to disable FEAT_MTPMU if implemented 211 (Armv8.6 onwards). Its default value is 0 to keep consistency with platforms 212 that do not implement FEAT_MTPMU. For more information on FEAT_MTPMU, 213 check the latest Arm ARM. 214 215- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 216 Board Boot authentication at runtime. This option is meant to be enabled only 217 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 218 flag has to be enabled. 0 is the default. 219 220- ``E``: Boolean option to make warnings into errors. Default is 1. 221 222 When specifying higher warnings levels (``W=1`` and higher), this option 223 defaults to 0. This is done to encourage contributors to use them, as they 224 are expected to produce warnings that would otherwise fail the build. New 225 contributions are still expected to build with ``W=0`` and ``E=1`` (the 226 default). 227 228- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 229 the normal boot flow. It must specify the entry point address of the EL3 230 payload. Please refer to the "Booting an EL3 payload" section for more 231 details. 232 233- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions. 234 This is an optional architectural feature available on v8.4 onwards. Some 235 v8.2 implementations also implement an AMU and this option can be used to 236 enable this feature on those systems as well. Default is 0. 237 238- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters 239 (also known as group 1 counters). These are implementation-defined counters, 240 and as such require additional platform configuration. Default is 0. 241 242- ``ENABLE_AMU_FCONF``: Enables configuration of the AMU through FCONF, which 243 allows platforms with auxiliary counters to describe them via the 244 ``HW_CONFIG`` device tree blob. Default is 0. 245 246- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 247 are compiled out. For debug builds, this option defaults to 1, and calls to 248 ``assert()`` are left in place. For release builds, this option defaults to 0 249 and calls to ``assert()`` function are compiled out. This option can be set 250 independently of ``DEBUG``. It can also be used to hide any auxiliary code 251 that is only required for the assertion and does not fit in the assertion 252 itself. 253 254- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 255 dumps or not. It is supported in both AArch64 and AArch32. However, in 256 AArch32 the format of the frame records are not defined in the AAPCS and they 257 are defined by the implementation. This implementation of backtrace only 258 supports the format used by GCC when T32 interworking is disabled. For this 259 reason enabling this option in AArch32 will force the compiler to only 260 generate A32 code. This option is enabled by default only in AArch64 debug 261 builds, but this behaviour can be overridden in each platform's Makefile or 262 in the build command line. 263 264- ``ENABLE_FEAT_AMUv1``: Numeric value to enable access to the HAFGRTR_EL2 265 (Hypervisor Activity Monitors Fine-Grained Read Trap Register) during EL2 266 to EL3 context save/restore operations. This flag can take the values 0 to 2, 267 to align with the ``FEATURE_DETECTION`` mechanism. It is an optional feature 268 available on v8.4 and onwards and must be set to either 1 or 2 alongside 269 ``ENABLE_FEAT_FGT``, to access the HAFGRTR_EL2 register. 270 Default value is ``0``. 271 272- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1`` 273 extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6 274 onwards. This flag can take the values 0 to 2, to align with the 275 ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 276 277- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2`` 278 extension. It allows access to the SCXTNUM_EL2 (Software Context Number) 279 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an 280 optional feature available on Arm v8.0 onwards. This flag can take values 281 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 282 Default value is ``0``. 283 284- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent 285 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3. 286 ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4 287 and upwards. This flag can take the values 0 to 2, to align with the 288 ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 289 290- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter 291 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer 292 Physical Offset register) during EL2 to EL3 context save/restore operations. 293 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 294 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 295 mechanism. Default value is ``0``. 296 297- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps) 298 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained 299 Read Trap Register) during EL2 to EL3 context save/restore operations. 300 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 301 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 302 mechanism. Default value is ``0``. 303 304- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to 305 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as 306 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a 307 mandatory architectural feature and is enabled from v8.7 and upwards. This 308 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 309 mechanism. Default value is ``0``. 310 311- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged 312 Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a 313 permission fault for any privileged data access from EL1/EL2 to virtual 314 memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a 315 mandatory architectural feature and is enabled from v8.1 and upwards. This 316 flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 317 mechanism. Default value is ``0``. 318 319- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension. 320 ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This 321 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 322 mechanism. Default value is ``0``. 323 324- ``ENABLE_FEAT_RNG_TRAP``: Numeric value to enable the ``FEAT_RNG_TRAP`` 325 extension. This feature is only supported in AArch64 state. This flag can 326 take values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 327 Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from 328 Armv8.5 onwards. 329 330- ``ENABLE_FEAT_SB``: Numeric value to enable the ``FEAT_SB`` (Speculation 331 Barrier) extension allowing access to ``sb`` instruction. ``FEAT_SB`` is an 332 optional feature and defaults to ``0`` for pre-Armv8.5 CPUs but are mandatory 333 for Armv8.5 or later CPUs. This flag can take values 0 to 2, to align with 334 ``FEATURE_DETECTION`` mechanism. It is enabled from v8.5 and upwards and if 335 needed could be overidden from platforms explicitly. Default value is ``0``. 336 337- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2) 338 extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4. 339 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 340 mechanism. Default is ``0``. 341 342- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed 343 trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature 344 available on Arm v8.6. This flag can take values 0 to 2, to align with the 345 ``FEATURE_DETECTION`` mechanism. Default is ``0``. 346 347 When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets 348 delayed by the amount of value in ``TWED_DELAY``. 349 350- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization 351 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register 352 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory 353 architectural feature and is enabled from v8.1 and upwards. It can take 354 values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 355 Default value is ``0``. 356 357- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 358 support in GCC for TF-A. This option is currently only supported for 359 AArch64. Default is 0. 360 361- ``ENABLE_MPAM_FOR_LOWER_ELS``: Numeric value to enable lower ELs to use MPAM 362 feature. MPAM is an optional Armv8.4 extension that enables various memory 363 system components and resources to define partitions; software running at 364 various ELs can assign themselves to desired partition to control their 365 performance aspects. 366 367 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 368 mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to 369 access their own MPAM registers without trapping into EL3. This option 370 doesn't make use of partitioning in EL3, however. Platform initialisation 371 code should configure and use partitions in EL3 as required. This option 372 defaults to ``0``. 373 374- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power 375 Mitigation Mechanism supported by certain Arm cores, which allows the SoC 376 firmware to detect and limit high activity events to assist in SoC processor 377 power domain dynamic power budgeting and limit the triggering of whole-rail 378 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``. 379 380- ``ENABLE_MPMM_FCONF``: Enables configuration of MPMM through FCONF, which 381 allows platforms with cores supporting MPMM to describe them via the 382 ``HW_CONFIG`` device tree blob. Default is 0. 383 384- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 385 support within generic code in TF-A. This option is currently only supported 386 in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and 387 in BL32 (SP_min) for AARCH32. Default is 0. 388 389- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 390 Measurement Framework(PMF). Default is 0. 391 392- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 393 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 394 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 395 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 396 software. 397 398- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm 399 Management Extension. This flag can take the values 0 to 2, to align with 400 the ``FEATURE_DETECTION`` mechanism. Default value is 0. This is currently 401 an experimental feature. 402 403- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 404 instrumentation which injects timestamp collection points into TF-A to 405 allow runtime performance to be measured. Currently, only PSCI is 406 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 407 as well. Default is 0. 408 409- ``ENABLE_SME_FOR_NS``: Boolean option to enable Scalable Matrix Extension 410 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share 411 registers so are enabled together. Using this option without 412 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure 413 world to trap to EL3. SME is an optional architectural feature for AArch64 414 and TF-A support is experimental. At this time, this build option cannot be 415 used on systems that have SPD=spmd/SPM_MM or ENABLE_RME, and attempting to 416 build with these options will fail. Default is 0. 417 418- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix 419 Extension for secure world use along with SVE and FPU/SIMD, ENABLE_SME_FOR_NS 420 must also be set to use this. If enabling this, the secure world MUST 421 handle context switching for SME, SVE, and FPU/SIMD registers to ensure that 422 no data is leaked to non-secure world. This is experimental. Default is 0. 423 424- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling 425 extensions. This is an optional architectural feature for AArch64. 426 The default is 1 but is automatically disabled when the target architecture 427 is AArch32. 428 429- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension 430 (SVE) for the Non-secure world only. SVE is an optional architectural feature 431 for AArch64. Note that when SVE is enabled for the Non-secure world, access 432 to SIMD and floating-point functionality from the Secure world is disabled by 433 default and controlled with ENABLE_SVE_FOR_SWD. 434 This is to avoid corruption of the Non-secure world data in the Z-registers 435 which are aliased by the SIMD and FP registers. The build option is not 436 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an 437 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to 438 1. The default is 1 but is automatically disabled when ENABLE_SME_FOR_NS=1 439 since SME encompasses SVE. At this time, this build option cannot be used on 440 systems that have SPM_MM enabled. 441 442- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world. 443 SVE is an optional architectural feature for AArch64. Note that this option 444 requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it 445 is automatically disabled when the target architecture is AArch32. 446 447- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 448 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 449 default value is set to "none". "strong" is the recommended stack protection 450 level if this feature is desired. "none" disables the stack protection. For 451 all values other than "none", the ``plat_get_stack_protector_canary()`` 452 platform hook needs to be implemented. The value is passed as the last 453 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 454 455- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 456 flag depends on ``DECRYPTION_SUPPORT`` build flag. 457 458- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 459 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 460 461- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 462 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 463 on ``DECRYPTION_SUPPORT`` build flag. 464 465- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 466 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 467 build flag. 468 469- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 470 deprecated platform APIs, helper functions or drivers within Trusted 471 Firmware as error. It can take the value 1 (flag the use of deprecated 472 APIs as error) or 0. The default is 0. 473 474- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 475 targeted at EL3. When set ``0`` (default), no exceptions are expected or 476 handled at EL3, and a panic will result. The exception to this rule is when 477 ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions 478 occuring during normal world execution, are trapped to EL3. Any exception 479 trapped during secure world execution are trapped to the SPMC. This is 480 supported only for AArch64 builds. 481 482- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when 483 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. 484 Default value is 40 (LOG_LEVEL_INFO). 485 486- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 487 injection from lower ELs, and this build option enables lower ELs to use 488 Error Records accessed via System Registers to inject faults. This is 489 applicable only to AArch64 builds. 490 491 This feature is intended for testing purposes only, and is advisable to keep 492 disabled for production images. 493 494- ``FEATURE_DETECTION``: Boolean option to enable the architectural features 495 detection mechanism. It detects whether the Architectural features enabled 496 through feature specific build flags are supported by the PE or not by 497 validating them either at boot phase or at runtime based on the value 498 possessed by the feature flag (0 to 2) and report error messages at an early 499 stage. 500 501 This prevents and benefits us from EL3 runtime exceptions during context save 502 and restore routines guarded by these build flags. Henceforth validating them 503 before their usage provides more control on the actions taken under them. 504 505 The mechanism permits the build flags to take values 0, 1 or 2 and 506 evaluates them accordingly. 507 508 Lets consider ``ENABLE_FEAT_HCX``, build flag for ``FEAT_HCX`` as an example: 509 510 :: 511 512 ENABLE_FEAT_HCX = 0: Feature disabled statically at compile time. 513 ENABLE_FEAT_HCX = 1: Feature Enabled and the flag is validated at boottime. 514 ENABLE_FEAT_HCX = 2: Feature Enabled and the flag is validated at runtime. 515 516 In the above example, if the feature build flag, ``ENABLE_FEAT_HCX`` set to 517 0, feature is disabled statically during compilation. If it is defined as 1, 518 feature is validated, wherein FEAT_HCX is detected at boot time. In case not 519 implemented by the PE, a hard panic is generated. Finally, if the flag is set 520 to 2, feature is validated at runtime. 521 522 Note that the entire implementation is divided into two phases, wherein as 523 as part of phase-1 we are supporting the values 0,1. Value 2 is currently not 524 supported and is planned to be handled explicilty in phase-2 implementation. 525 526 FEATURE_DETECTION macro is disabled by default, and is currently an 527 experimental procedure. Platforms can explicitly make use of this by 528 mechanism, by enabling it to validate whether they have set their build flags 529 properly at an early phase. 530 531- ``FIP_NAME``: This is an optional build option which specifies the FIP 532 filename for the ``fip`` target. Default is ``fip.bin``. 533 534- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 535 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 536 537- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 538 539 :: 540 541 0: Encryption is done with Secret Symmetric Key (SSK) which is common 542 for a class of devices. 543 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 544 unique per device. 545 546 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 547 548- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 549 tool to create certificates as per the Chain of Trust described in 550 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 551 include the certificates in the FIP and FWU_FIP. Default value is '0'. 552 553 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 554 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 555 the corresponding certificates, and to include those certificates in the 556 FIP and FWU_FIP. 557 558 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 559 images will not include support for Trusted Board Boot. The FIP will still 560 include the corresponding certificates. This FIP can be used to verify the 561 Chain of Trust on the host machine through other mechanisms. 562 563 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 564 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 565 will not include the corresponding certificates, causing a boot failure. 566 567- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 568 inherent support for specific EL3 type interrupts. Setting this build option 569 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 570 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 571 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 572 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 573 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 574 the Secure Payload interrupts needs to be synchronously handed over to Secure 575 EL1 for handling. The default value of this option is ``0``, which means the 576 Group 0 interrupts are assumed to be handled by Secure EL1. 577 578- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError 579 Interrupts, resulting from errors in NS world, will be always trapped in 580 EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions 581 will be trapped in the current exception level (or in EL1 if the current 582 exception level is EL0). 583 584- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 585 software operations are required for CPUs to enter and exit coherency. 586 However, newer systems exist where CPUs' entry to and exit from coherency 587 is managed in hardware. Such systems require software to only initiate these 588 operations, and the rest is managed in hardware, minimizing active software 589 management. In such systems, this boolean option enables TF-A to carry out 590 build and run-time optimizations during boot and power management operations. 591 This option defaults to 0 and if it is enabled, then it implies 592 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 593 594 If this flag is disabled while the platform which TF-A is compiled for 595 includes cores that manage coherency in hardware, then a compilation error is 596 generated. This is based on the fact that a system cannot have, at the same 597 time, cores that manage coherency in hardware and cores that don't. In other 598 words, a platform cannot have, at the same time, cores that require 599 ``HW_ASSISTED_COHERENCY=1`` and cores that require 600 ``HW_ASSISTED_COHERENCY=0``. 601 602 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 603 translation library (xlat tables v2) must be used; version 1 of translation 604 library is not supported. 605 606- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 607 bottom, higher addresses at the top. This build flag can be set to '1' to 608 invert this behavior. Lower addresses will be printed at the top and higher 609 addresses at the bottom. 610 611- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3 612 runtime software in AArch32 mode, which is required to run AArch32 on Juno. 613 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in 614 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable 615 images. 616 617- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 618 used for generating the PKCS keys and subsequent signing of the certificate. 619 It accepts 5 values: ``rsa``, ``rsa_1_5``, ``ecdsa``, ``ecdsa-brainpool-regular`` 620 and ``ecdsa-brainpool-twisted``. The option ``rsa_1_5`` is the legacy PKCS#1 621 RSA 1.5 algorithm which is not TBBR compliant and is retained only for 622 compatibility. The default value of this flag is ``rsa`` which is the TBBR 623 compliant PKCS#1 RSA 2.1 scheme. 624 625- ``KEY_SIZE``: This build flag enables the user to select the key size for 626 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 627 depend on the chosen algorithm and the cryptographic module. 628 629 +---------------------------+------------------------------------+ 630 | KEY_ALG | Possible key sizes | 631 +===========================+====================================+ 632 | rsa | 1024 , 2048 (default), 3072, 4096* | 633 +---------------------------+------------------------------------+ 634 | ecdsa | unavailable | 635 +---------------------------+------------------------------------+ 636 | ecdsa-brainpool-regular | unavailable | 637 +---------------------------+------------------------------------+ 638 | ecdsa-brainpool-twisted | unavailable | 639 +---------------------------+------------------------------------+ 640 641 642 * Only 2048 bits size is available with CryptoCell 712 SBROM release 1. 643 Only 3072 bits size is available with CryptoCell 712 SBROM release 2. 644 645- ``HASH_ALG``: This build flag enables the user to select the secure hash 646 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 647 The default value of this flag is ``sha256``. 648 649- ``LDFLAGS``: Extra user options appended to the linkers' command line in 650 addition to the one set by the build system. 651 652- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 653 output compiled into the build. This should be one of the following: 654 655 :: 656 657 0 (LOG_LEVEL_NONE) 658 10 (LOG_LEVEL_ERROR) 659 20 (LOG_LEVEL_NOTICE) 660 30 (LOG_LEVEL_WARNING) 661 40 (LOG_LEVEL_INFO) 662 50 (LOG_LEVEL_VERBOSE) 663 664 All log output up to and including the selected log level is compiled into 665 the build. The default value is 40 in debug builds and 20 in release builds. 666 667- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 668 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to 669 provide trust that the code taking the measurements and recording them has 670 not been tampered with. 671 672 This option defaults to 0. 673 674- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust 675 for Measurement (DRTM). This feature has trust dependency on BL31 for taking 676 the measurements and recording them as per `PSA DRTM specification`_. For 677 platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can 678 be used and for the platforms which use ``RESET_TO_BL31`` platform owners 679 should have mechanism to authenticate BL31. This is an experimental feature. 680 681 This option defaults to 0. 682 683- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 684 specifies the file that contains the Non-Trusted World private key in PEM 685 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 686 687- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 688 optional. It is only needed if the platform makefile specifies that it 689 is required in order to build the ``fwu_fip`` target. 690 691- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 692 contents upon world switch. It can take either 0 (don't save and restore) or 693 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 694 wants the timer registers to be saved and restored. 695 696- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 697 for the BL image. It can be either 0 (include) or 1 (remove). The default 698 value is 0. 699 700- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 701 the underlying hardware is not a full PL011 UART but a minimally compliant 702 generic UART, which is a subset of the PL011. The driver will not access 703 any register that is not part of the SBSA generic UART specification. 704 Default value is 0 (a full PL011 compliant UART is present). 705 706- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 707 must be subdirectory of any depth under ``plat/``, and must contain a 708 platform makefile named ``platform.mk``. For example, to build TF-A for the 709 Arm Juno board, select PLAT=juno. 710 711- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 712 instead of the normal boot flow. When defined, it must specify the entry 713 point address for the preloaded BL33 image. This option is incompatible with 714 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 715 over ``PRELOADED_BL33_BASE``. 716 717- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 718 vector address can be programmed or is fixed on the platform. It can take 719 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 720 programmable reset address, it is expected that a CPU will start executing 721 code directly at the right address, both on a cold and warm reset. In this 722 case, there is no need to identify the entrypoint on boot and the boot path 723 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 724 does not need to be implemented in this case. 725 726- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 727 possible for the PSCI power-state parameter: original and extended State-ID 728 formats. This flag if set to 1, configures the generic PSCI layer to use the 729 extended format. The default value of this flag is 0, which means by default 730 the original power-state format is used by the PSCI implementation. This flag 731 should be specified by the platform makefile and it governs the return value 732 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 733 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 734 set to 1 as well. 735 736- ``RAS_EXTENSION``: Numeric value to enable Armv8.2 RAS features. RAS features 737 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 738 or later CPUs. This flag can take the values 0 to 2, to align with the 739 ``FEATURE_DETECTION`` mechanism. 740 741 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST_NS`` must also be 742 set to ``1``. 743 744 This option is disabled by default. 745 746- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 747 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 748 entrypoint) or 1 (CPU reset to BL31 entrypoint). 749 The default value is 0. 750 751- ``RESET_TO_BL31_WITH_PARAMS``: If ``RESET_TO_BL31`` has been enabled, setting 752 this additional option guarantees that the input registers are not cleared 753 therefore allowing parameters to be passed to the BL31 entrypoint. 754 The default value is 0. 755 756- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 757 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 758 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 759 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 760 761- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 762 file that contains the ROT private key in PEM format and enforces public key 763 hash generation. If ``SAVE_KEYS=1``, this 764 file name will be used to save the key. 765 766- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 767 certificate generation tool to save the keys used to establish the Chain of 768 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 769 770- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 771 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 772 target. 773 774- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 775 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``, 776 this file name will be used to save the key. 777 778- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 779 optional. It is only needed if the platform makefile specifies that it 780 is required in order to build the ``fwu_fip`` target. 781 782- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 783 Delegated Exception Interface to BL31 image. This defaults to ``0``. 784 785 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 786 set to ``1``. 787 788- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 789 isolated on separate memory pages. This is a trade-off between security and 790 memory usage. See "Isolating code and read-only data on separate memory 791 pages" section in :ref:`Firmware Design`. This flag is disabled by default 792 and affects all BL images. 793 794- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 795 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 796 allocated in RAM discontiguous from the loaded firmware image. When set, the 797 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and 798 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 799 sections are placed in RAM immediately following the loaded firmware image. 800 801- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the 802 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM 803 discontiguous from loaded firmware images. When set, the platform need to 804 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This 805 flag is disabled by default and NOLOAD sections are placed in RAM immediately 806 following the loaded firmware image. 807 808- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration 809 access requests via a standard SMCCC defined in `DEN0115`_. When combined with 810 UEFI+ACPI this can provide a certain amount of OS forward compatibility 811 with newer platforms that aren't ECAM compliant. 812 813- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 814 This build option is only valid if ``ARCH=aarch64``. The value should be 815 the path to the directory containing the SPD source, relative to 816 ``services/spd/``; the directory is expected to contain a makefile called 817 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 818 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 819 cannot be enabled when the ``SPM_MM`` option is enabled. 820 821- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 822 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 823 execution in BL1 just before handing over to BL31. At this point, all 824 firmware images have been loaded in memory, and the MMU and caches are 825 turned off. Refer to the "Debugging options" section for more details. 826 827- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM 828 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 829 component runs at the EL3 exception level. The default value is ``0`` ( 830 disabled). This configuration supports pre-Armv8.4 platforms (aka not 831 implementing the ``FEAT_SEL2`` extension). This is an experimental feature. 832 833- ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM 834 Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to 835 indicate that the SPMC at S-EL1 is OP-TEE and an OP-TEE specific loading 836 mechanism should be used. 837 838- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM 839 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 840 component runs at the S-EL2 exception level provided by the ``FEAT_SEL2`` 841 extension. This is the default when enabling the SPM Dispatcher. When 842 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 843 state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations 844 support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2`` 845 extension). 846 847- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 848 Partition Manager (SPM) implementation. The default value is ``0`` 849 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 850 enabled (``SPD=spmd``). 851 852- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 853 description of secure partitions. The build system will parse this file and 854 package all secure partition blobs into the FIP. This file is not 855 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 856 857- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 858 secure interrupts (caught through the FIQ line). Platforms can enable 859 this directive if they need to handle such interruption. When enabled, 860 the FIQ are handled in monitor mode and non secure world is not allowed 861 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 862 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 863 864- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3. 865 Platforms can configure this if they need to lower the hardware 866 limit, for example due to asymmetric configuration or limitations of 867 software run at lower ELs. The default is the architectural maximum 868 of 2048 which should be suitable for most configurations, the 869 hardware will limit the effective VL to the maximum physically supported 870 VL. 871 872- ``TRNG_SUPPORT``: Setting this to ``1`` enables support for True 873 Random Number Generator Interface to BL31 image. This defaults to ``0``. 874 875- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 876 Boot feature. When set to '1', BL1 and BL2 images include support to load 877 and verify the certificates and images in a FIP, and BL1 includes support 878 for the Firmware Update. The default value is '0'. Generation and inclusion 879 of certificates in the FIP and FWU_FIP depends upon the value of the 880 ``GENERATE_COT`` option. 881 882 .. warning:: 883 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 884 already exist in disk, they will be overwritten without further notice. 885 886- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 887 specifies the file that contains the Trusted World private key in PEM 888 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 889 890- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 891 synchronous, (see "Initializing a BL32 Image" section in 892 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 893 synchronous method) or 1 (BL32 is initialized using asynchronous method). 894 Default is 0. 895 896- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 897 routing model which routes non-secure interrupts asynchronously from TSP 898 to EL3 causing immediate preemption of TSP. The EL3 is responsible 899 for saving and restoring the TSP context in this routing model. The 900 default routing model (when the value is 0) is to route non-secure 901 interrupts to TSP allowing it to save its context and hand over 902 synchronously to EL3 via an SMC. 903 904 .. note:: 905 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 906 must also be set to ``1``. 907 908- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of 909 WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set 910 this delay. It can take values in the range (0-15). Default value is ``0`` 911 and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed. 912 Platforms need to explicitly update this value based on their requirements. 913 914- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 915 linker. When the ``LINKER`` build variable points to the armlink linker, 916 this flag is enabled automatically. To enable support for armlink, platforms 917 will have to provide a scatter file for the BL image. Currently, Tegra 918 platforms use the armlink support to compile BL3-1 images. 919 920- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 921 memory region in the BL memory map or not (see "Use of Coherent memory in 922 TF-A" section in :ref:`Firmware Design`). It can take the value 1 923 (Coherent memory region is included) or 0 (Coherent memory region is 924 excluded). Default is 1. 925 926- ``USE_DEBUGFS``: When set to 1 this option activates an EXPERIMENTAL feature 927 exposing a virtual filesystem interface through BL31 as a SiP SMC function. 928 Default is 0. 929 930- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 931 firmware configuration framework. This will move the io_policies into a 932 configuration device tree, instead of static structure in the code base. 933 934- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 935 at runtime using fconf. If this flag is enabled, COT descriptors are 936 statically captured in tb_fw_config file in the form of device tree nodes 937 and properties. Currently, COT descriptors used by BL2 are moved to the 938 device tree and COT descriptors used by BL1 are retained in the code 939 base statically. 940 941- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 942 runtime using firmware configuration framework. The platform specific SDEI 943 shared and private events configuration is retrieved from device tree rather 944 than static C structures at compile time. This is only supported if 945 SDEI_SUPPORT build flag is enabled. 946 947- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 948 and Group1 secure interrupts using the firmware configuration framework. The 949 platform specific secure interrupt property descriptor is retrieved from 950 device tree in runtime rather than depending on static C structure at compile 951 time. 952 953- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 954 This feature creates a library of functions to be placed in ROM and thus 955 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 956 is 0. 957 958- ``V``: Verbose build. If assigned anything other than 0, the build commands 959 are printed. Default is 0. 960 961- ``VERSION_STRING``: String used in the log output for each TF-A image. 962 Defaults to a string formed by concatenating the version number, build type 963 and build string. 964 965- ``W``: Warning level. Some compiler warning options of interest have been 966 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 967 each level enabling more warning options. Default is 0. 968 969 This option is closely related to the ``E`` option, which enables 970 ``-Werror``. 971 972 - ``W=0`` (default) 973 974 Enables a wide assortment of warnings, most notably ``-Wall`` and 975 ``-Wextra``, as well as various bad practices and things that are likely to 976 result in errors. Includes some compiler specific flags. No warnings are 977 expected at this level for any build. 978 979 - ``W=1`` 980 981 Enables warnings we want the generic build to include but are too time 982 consuming to fix at the moment. It re-enables warnings taken out for 983 ``W=0`` builds (a few of the ``-Wextra`` additions). This level is expected 984 to eventually be merged into ``W=0``. Some warnings are expected on some 985 builds, but new contributions should not introduce new ones. 986 987 - ``W=2`` (recommended) 988 989 Enables warnings we want the generic build to include but cannot be enabled 990 due to external libraries. This level is expected to eventually be merged 991 into ``W=0``. Lots of warnings are expected, primarily from external 992 libraries like zlib and compiler-rt, but new controbutions should not 993 introduce new ones. 994 995 - ``W=3`` 996 997 Enables warnings that are informative but not necessary and generally too 998 verbose and frequently ignored. A very large number of warnings are 999 expected. 1000 1001 The exact set of warning flags depends on the compiler and TF-A warning 1002 level, however they are all succinctly set in the top-level Makefile. Please 1003 refer to the `GCC`_ or `Clang`_ documentation for more information on the 1004 individual flags. 1005 1006- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 1007 the CPU after warm boot. This is applicable for platforms which do not 1008 require interconnect programming to enable cache coherency (eg: single 1009 cluster platforms). If this option is enabled, then warm boot path 1010 enables D-caches immediately after enabling MMU. This option defaults to 0. 1011 1012- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory 1013 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The 1014 default value of this flag is ``no``. Note this option must be enabled only 1015 for ARM architecture greater than Armv8.5-A. 1016 1017- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 1018 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 1019 The default value of this flag is ``0``. 1020 1021 ``AT`` speculative errata workaround disables stage1 page table walk for 1022 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 1023 produces either the correct result or failure without TLB allocation. 1024 1025 This boolean option enables errata for all below CPUs. 1026 1027 +---------+--------------+-------------------------+ 1028 | Errata | CPU | Workaround Define | 1029 +=========+==============+=========================+ 1030 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 1031 +---------+--------------+-------------------------+ 1032 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 1033 +---------+--------------+-------------------------+ 1034 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 1035 +---------+--------------+-------------------------+ 1036 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 1037 +---------+--------------+-------------------------+ 1038 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 1039 +---------+--------------+-------------------------+ 1040 1041 .. note:: 1042 This option is enabled by build only if platform sets any of above defines 1043 mentioned in ’Workaround Define' column in the table. 1044 If this option is enabled for the EL3 software then EL2 software also must 1045 implement this workaround due to the behaviour of the errata mentioned 1046 in new SDEN document which will get published soon. 1047 1048- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR 1049 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 1050 This flag is disabled by default. 1051 1052- ``OPENSSL_DIR``: This option is used to provide the path to a directory on the 1053 host machine where a custom installation of OpenSSL is located, which is used 1054 to build the certificate generation, firmware encryption and FIP tools. If 1055 this option is not set, the default OS installation will be used. 1056 1057- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 1058 functions that wait for an arbitrary time length (udelay and mdelay). The 1059 default value is 0. 1060 1061- ``ENABLE_BRBE_FOR_NS``: Numeric value to enable access to the branch record 1062 buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an 1063 optional architectural feature for AArch64. This flag can take the values 1064 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. The default is 0 1065 and it is automatically disabled when the target architecture is AArch32. 1066 1067- ``ENABLE_TRBE_FOR_NS``: Numeric value to enable access of trace buffer 1068 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented 1069 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural 1070 feature for AArch64. This flag can take the values 0 to 2, to align with the 1071 ``FEATURE_DETECTION`` mechanism. The default is 0 and it is automatically 1072 disabled when the target architecture is AArch32. 1073 1074- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Boolean option to enable trace system 1075 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented 1076 but unused). This feature is available if trace unit such as ETMv4.x, and 1077 ETE(extending ETM feature) is implemented. This flag is disabled by default. 1078 1079- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers 1080 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), 1081 if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align 1082 with the ``FEATURE_DETECTION`` mechanism. This flag is disabled by default. 1083 1084- ``PLAT_RSS_NOT_SUPPORTED``: Boolean option to enable the usage of the PSA 1085 APIs on platforms that doesn't support RSS (providing Arm CCA HES 1086 functionalities). When enabled (``1``), a mocked version of the APIs are used. 1087 The default value is 0. 1088 1089- ``CONDITIONAL_CMO``: Boolean option to enable call to platform-defined routine 1090 ``plat_can_cmo`` which will return zero if cache management operations should 1091 be skipped and non-zero otherwise. By default, this option is disabled which 1092 means platform hook won't be checked and CMOs will always be performed when 1093 related functions are called. 1094 1095GICv3 driver options 1096-------------------- 1097 1098GICv3 driver files are included using directive: 1099 1100``include drivers/arm/gic/v3/gicv3.mk`` 1101 1102The driver can be configured with the following options set in the platform 1103makefile: 1104 1105- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 1106 Enabling this option will add runtime detection support for the 1107 GIC-600, so is safe to select even for a GIC500 implementation. 1108 This option defaults to 0. 1109 1110- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit 1111 for GIC-600 AE. Enabling this option will introduce support to initialize 1112 the FMU. Platforms should call the init function during boot to enable the 1113 FMU and its safety mechanisms. This option defaults to 0. 1114 1115- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 1116 functionality. This option defaults to 0 1117 1118- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 1119 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 1120 functions. This is required for FVP platform which need to simulate GIC save 1121 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 1122 1123- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 1124 This option defaults to 0. 1125 1126- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 1127 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 1128 1129Debugging options 1130----------------- 1131 1132To compile a debug version and make the build more verbose use 1133 1134.. code:: shell 1135 1136 make PLAT=<platform> DEBUG=1 V=1 all 1137 1138AArch64 GCC 11 uses DWARF version 5 debugging symbols by default. Some tools 1139(for example Arm-DS) might not support this and may need an older version of 1140DWARF symbols to be emitted by GCC. This can be achieved by using the 1141``-gdwarf-<version>`` flag, with the version being set to 2, 3, 4 or 5. Setting 1142the version to 4 is recommended for Arm-DS. 1143 1144When debugging logic problems it might also be useful to disable all compiler 1145optimizations by using ``-O0``. 1146 1147.. warning:: 1148 Using ``-O0`` could cause output images to be larger and base addresses 1149 might need to be recalculated (see the **Memory layout on Arm development 1150 platforms** section in the :ref:`Firmware Design`). 1151 1152Extra debug options can be passed to the build system by setting ``CFLAGS`` or 1153``LDFLAGS``: 1154 1155.. code:: shell 1156 1157 CFLAGS='-O0 -gdwarf-2' \ 1158 make PLAT=<platform> DEBUG=1 V=1 all 1159 1160Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 1161ignored as the linker is called directly. 1162 1163It is also possible to introduce an infinite loop to help in debugging the 1164post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 1165``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 1166section. In this case, the developer may take control of the target using a 1167debugger when indicated by the console output. When using Arm-DS, the following 1168commands can be used: 1169 1170:: 1171 1172 # Stop target execution 1173 interrupt 1174 1175 # 1176 # Prepare your debugging environment, e.g. set breakpoints 1177 # 1178 1179 # Jump over the debug loop 1180 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 1181 1182 # Resume execution 1183 continue 1184 1185Firmware update options 1186----------------------- 1187 1188- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used 1189 in defining the firmware update metadata structure. This flag is by default 1190 set to '2'. 1191 1192- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each 1193 firmware bank. Each firmware bank must have the same number of images as per 1194 the `PSA FW update specification`_. 1195 This flag is used in defining the firmware update metadata structure. This 1196 flag is by default set to '1'. 1197 1198- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the 1199 `PSA FW update specification`_. The default value is 0, and this is an 1200 experimental feature. 1201 PSA firmware update implementation has some limitations, such as BL2 is 1202 not part of the protocol-updatable images, if BL2 needs to be updated, then 1203 it should be done through another platform-defined mechanism, and it assumes 1204 that the platform's hardware supports CRC32 instructions. 1205 1206-------------- 1207 1208*Copyright (c) 2019-2023, Arm Limited. All rights reserved.* 1209 1210.. _DEN0115: https://developer.arm.com/docs/den0115/latest 1211.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/ 1212.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a 1213.. _GCC: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html 1214.. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html 1215