1# 2# Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25FVP_DT_PREFIX := fvp-base-gicv3-psci 26 27# The FVP platform depends on this macro to build with correct GIC driver. 28$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 29 30# Pass FVP_CLUSTER_COUNT to the build system. 31$(eval $(call add_define,FVP_CLUSTER_COUNT)) 32 33# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 34$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 35 36# Pass FVP_MAX_PE_PER_CPU to the build system. 37$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 38 39# Pass FVP_GICR_REGION_PROTECTION to the build system. 40$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 41 42# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 43# choose the CCI driver , else the CCN driver 44ifeq ($(FVP_CLUSTER_COUNT), 0) 45$(error "Incorrect cluster count specified for FVP port") 46else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 47FVP_INTERCONNECT_DRIVER := FVP_CCI 48else 49FVP_INTERCONNECT_DRIVER := FVP_CCN 50endif 51 52$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 53 54# Choose the GIC sources depending upon the how the FVP will be invoked 55ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 56 57# The GIC model (GIC-600 or GIC-500) will be detected at runtime 58GICV3_SUPPORT_GIC600 := 1 59GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 60 61# Include GICv3 driver files 62include drivers/arm/gic/v3/gicv3.mk 63 64FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 65 plat/common/plat_gicv3.c \ 66 plat/arm/common/arm_gicv3.c 67 68 ifeq ($(filter 1,${RESET_TO_BL2} \ 69 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 70 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 71 endif 72 73else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 74 75# No GICv4 extension 76GIC_ENABLE_V4_EXTN := 0 77$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 78 79# Include GICv2 driver files 80include drivers/arm/gic/v2/gicv2.mk 81 82FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 83 plat/common/plat_gicv2.c \ 84 plat/arm/common/arm_gicv2.c 85 86FVP_DT_PREFIX := fvp-base-gicv2-psci 87else 88$(error "Incorrect GIC driver chosen on FVP port") 89endif 90 91ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 92FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 93else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 94FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 95 plat/arm/common/arm_ccn.c 96else 97$(error "Incorrect CCN driver chosen on FVP port") 98endif 99 100FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 101 plat/arm/board/fvp/fvp_security.c \ 102 plat/arm/common/arm_tzc400.c 103 104 105PLAT_INCLUDES := -Iplat/arm/board/fvp/include 106 107 108PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 109 110FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 111 112ifeq (${ARCH}, aarch64) 113 114# select a different set of CPU files, depending on whether we compile for 115# hardware assisted coherency cores or not 116ifeq (${HW_ASSISTED_COHERENCY}, 0) 117# Cores used without DSU 118 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 119 lib/cpus/aarch64/cortex_a53.S \ 120 lib/cpus/aarch64/cortex_a57.S \ 121 lib/cpus/aarch64/cortex_a72.S \ 122 lib/cpus/aarch64/cortex_a73.S 123else 124# Cores used with DSU only 125 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 126 # AArch64-only cores 127 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \ 128 lib/cpus/aarch64/cortex_a76ae.S \ 129 lib/cpus/aarch64/cortex_a77.S \ 130 lib/cpus/aarch64/cortex_a78.S \ 131 lib/cpus/aarch64/neoverse_n_common.S \ 132 lib/cpus/aarch64/neoverse_n1.S \ 133 lib/cpus/aarch64/neoverse_n2.S \ 134 lib/cpus/aarch64/neoverse_e1.S \ 135 lib/cpus/aarch64/neoverse_v1.S \ 136 lib/cpus/aarch64/neoverse_v2.S \ 137 lib/cpus/aarch64/cortex_a78_ae.S \ 138 lib/cpus/aarch64/cortex_a510.S \ 139 lib/cpus/aarch64/cortex_a710.S \ 140 lib/cpus/aarch64/cortex_a715.S \ 141 lib/cpus/aarch64/cortex_x3.S \ 142 lib/cpus/aarch64/cortex_a65.S \ 143 lib/cpus/aarch64/cortex_a65ae.S \ 144 lib/cpus/aarch64/cortex_a78c.S \ 145 lib/cpus/aarch64/cortex_hayes.S \ 146 lib/cpus/aarch64/cortex_hunter.S \ 147 lib/cpus/aarch64/cortex_hunter_elp_arm.S \ 148 lib/cpus/aarch64/cortex_x2.S \ 149 lib/cpus/aarch64/neoverse_poseidon.S 150 endif 151 # AArch64/AArch32 cores 152 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 153 lib/cpus/aarch64/cortex_a75.S 154endif 155 156else 157FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S 158endif 159 160BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 161 drivers/arm/sp805/sp805.c \ 162 drivers/delay_timer/delay_timer.c \ 163 drivers/io/io_semihosting.c \ 164 lib/semihosting/semihosting.c \ 165 lib/semihosting/${ARCH}/semihosting_call.S \ 166 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 167 plat/arm/board/fvp/fvp_bl1_setup.c \ 168 plat/arm/board/fvp/fvp_err.c \ 169 plat/arm/board/fvp/fvp_io_storage.c \ 170 ${FVP_CPU_LIBS} \ 171 ${FVP_INTERCONNECT_SOURCES} 172 173ifeq (${USE_SP804_TIMER},1) 174BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 175else 176BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 177endif 178 179 180BL2_SOURCES += drivers/arm/sp805/sp805.c \ 181 drivers/io/io_semihosting.c \ 182 lib/utils/mem_region.c \ 183 lib/semihosting/semihosting.c \ 184 lib/semihosting/${ARCH}/semihosting_call.S \ 185 plat/arm/board/fvp/fvp_bl2_setup.c \ 186 plat/arm/board/fvp/fvp_err.c \ 187 plat/arm/board/fvp/fvp_io_storage.c \ 188 plat/arm/common/arm_nor_psci_mem_protect.c \ 189 ${FVP_SECURITY_SOURCES} 190 191 192ifeq (${COT_DESC_IN_DTB},1) 193BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 194endif 195 196ifeq (${ENABLE_RME},1) 197BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S 198BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 199 plat/arm/board/fvp/fvp_realm_attest_key.c 200endif 201 202ifeq (${ENABLE_FEAT_RNG_TRAP},1) 203BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 204endif 205 206ifeq (${RESET_TO_BL2},1) 207BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 208 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 209 ${FVP_CPU_LIBS} \ 210 ${FVP_INTERCONNECT_SOURCES} 211endif 212 213ifeq (${USE_SP804_TIMER},1) 214BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 215endif 216 217BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 218 ${FVP_SECURITY_SOURCES} 219 220ifeq (${USE_SP804_TIMER},1) 221BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 222endif 223 224BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 225 drivers/arm/smmu/smmu_v3.c \ 226 drivers/delay_timer/delay_timer.c \ 227 drivers/cfi/v2m/v2m_flash.c \ 228 lib/utils/mem_region.c \ 229 plat/arm/board/fvp/fvp_bl31_setup.c \ 230 plat/arm/board/fvp/fvp_console.c \ 231 plat/arm/board/fvp/fvp_pm.c \ 232 plat/arm/board/fvp/fvp_topology.c \ 233 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 234 plat/arm/common/arm_nor_psci_mem_protect.c \ 235 ${FVP_CPU_LIBS} \ 236 ${FVP_GIC_SOURCES} \ 237 ${FVP_INTERCONNECT_SOURCES} \ 238 ${FVP_SECURITY_SOURCES} 239 240# Support for fconf in BL31 241# Added separately from the above list for better readability 242ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 243BL31_SOURCES += lib/fconf/fconf.c \ 244 lib/fconf/fconf_dyn_cfg_getter.c \ 245 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 246 247BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 248 249ifeq (${SEC_INT_DESC_IN_FCONF},1) 250BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 251endif 252 253endif 254 255ifeq (${USE_SP804_TIMER},1) 256BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 257else 258BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 259endif 260 261# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 262ifdef UNIX_MK 263FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 264FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 265 ${PLAT}_fw_config.dts \ 266 ${PLAT}_tb_fw_config.dts \ 267 ${PLAT}_soc_fw_config.dts \ 268 ${PLAT}_nt_fw_config.dts \ 269 ) 270 271FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 272FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 273FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 274FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 275 276ifeq (${SPD},tspd) 277FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 278FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 279 280# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 281$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 282endif 283 284ifeq (${SPD},spmd) 285 286ifeq ($(ARM_SPMC_MANIFEST_DTS),) 287ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 288endif 289 290FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 291FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 292 293# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 294$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 295endif 296 297# Add the FW_CONFIG to FIP and specify the same to certtool 298$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 299# Add the TB_FW_CONFIG to FIP and specify the same to certtool 300$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 301# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 302$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 303# Add the NT_FW_CONFIG to FIP and specify the same to certtool 304$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 305 306FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 307$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 308 309# Add the HW_CONFIG to FIP and specify the same to certtool 310$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 311endif 312 313# Enable Activity Monitor Unit extensions by default 314ENABLE_AMU := 1 315 316# Enable dynamic mitigation support by default 317DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 318 319ifeq (${ENABLE_AMU},1) 320BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 321 lib/cpus/aarch64/cpuamu_helpers.S 322 323ifeq (${HW_ASSISTED_COHERENCY}, 1) 324BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 325 lib/cpus/aarch64/neoverse_n1_pubsub.c 326endif 327endif 328 329ifeq (${RAS_EXTENSION},1) 330BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 331endif 332 333ifneq (${ENABLE_STACK_PROTECTOR},0) 334PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 335endif 336 337ifeq (${ARCH},aarch32) 338 NEED_BL32 := yes 339endif 340 341# Enable the dynamic translation tables library. 342ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 343 ifeq (${ARCH},aarch32) 344 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 345 else # AArch64 346 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 347 endif 348endif 349 350ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 351 ifeq (${ARCH},aarch32) 352 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 353 else # AArch64 354 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 355 ifeq (${SPD},tspd) 356 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 357 endif 358 endif 359endif 360 361ifeq (${USE_DEBUGFS},1) 362 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 363endif 364 365# Add support for platform supplied linker script for BL31 build 366$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 367 368ifneq (${RESET_TO_BL2}, 0) 369 override BL1_SOURCES = 370endif 371 372# Include Measured Boot makefile before any Crypto library makefile. 373# Crypto library makefile may need default definitions of Measured Boot build 374# flags present in Measured Boot makefile. 375ifeq (${MEASURED_BOOT},1) 376 RSS_MEASURED_BOOT_MK := drivers/measured_boot/rss/rss_measured_boot.mk 377 $(info Including ${RSS_MEASURED_BOOT_MK}) 378 include ${RSS_MEASURED_BOOT_MK} 379 380 ifneq (${MBOOT_RSS_HASH_ALG}, sha256) 381 $(eval $(call add_define,TF_MBEDTLS_MBOOT_USE_SHA512)) 382 endif 383 384 BL1_SOURCES += ${MEASURED_BOOT_SOURCES} 385 BL2_SOURCES += ${MEASURED_BOOT_SOURCES} 386endif 387 388include plat/arm/board/common/board_common.mk 389include plat/arm/common/arm_common.mk 390 391ifeq (${MEASURED_BOOT},1) 392BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 393 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 394 lib/psa/measured_boot.c 395 396BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 397 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 398 lib/psa/measured_boot.c 399 400# Note that attestation code does not depend on measured boot interfaces per se, 401# but the two features go together - attestation without boot measurements is 402# pretty much pointless... 403BL31_SOURCES += lib/psa/delegated_attestation.c 404 405PLAT_INCLUDES += -Iinclude/lib/psa 406 407# RSS is not supported on FVP right now. Thus, we use the mocked version 408# of the provided PSA APIs. They return with success and hard-coded data. 409PLAT_RSS_NOT_SUPPORTED := 1 410 411# Even though RSS is not supported on FVP (see above), we support overriding 412# PLAT_RSS_NOT_SUPPORTED from the command line, just for the purpose of building 413# the code to detect any build regressions. The resulting firmware will not be 414# functional. 415ifneq (${PLAT_RSS_NOT_SUPPORTED},1) 416 $(warning "RSS is not supported on FVP. The firmware will not be functional.") 417 include drivers/arm/rss/rss_comms.mk 418 BL1_SOURCES += ${RSS_COMMS_SOURCES} 419 BL2_SOURCES += ${RSS_COMMS_SOURCES} 420 BL31_SOURCES += ${RSS_COMMS_SOURCES} \ 421 lib/psa/delegated_attestation.c 422 423 BL1_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 424 BL2_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 425 BL31_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 426endif 427 428endif 429 430ifeq (${DRTM_SUPPORT}, 1) 431BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 432 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 433 plat/arm/board/fvp/fvp_drtm_err.c \ 434 plat/arm/board/fvp/fvp_drtm_measurement.c \ 435 plat/arm/board/fvp/fvp_drtm_stub.c \ 436 plat/arm/common/arm_dyn_cfg.c \ 437 plat/arm/board/fvp/fvp_err.c 438endif 439 440ifeq (${TRUSTED_BOARD_BOOT}, 1) 441BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 442BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 443 444# FVP being a development platform, enable capability to disable Authentication 445# dynamically if TRUSTED_BOARD_BOOT is set. 446DYN_DISABLE_AUTH := 1 447endif 448 449# enable trace buffer control registers access to NS by default 450ENABLE_TRBE_FOR_NS := 2 451 452# enable branch record buffer control registers access in NS by default 453# only enable for aarch64 454# do not enable when ENABLE_RME=1 455ifeq (${ARCH}, aarch64) 456ifeq (${ENABLE_RME},0) 457 ENABLE_BRBE_FOR_NS := 2 458endif 459endif 460 461# enable trace system registers access to NS by default 462ENABLE_SYS_REG_TRACE_FOR_NS := 1 463 464# enable trace filter control registers access to NS by default 465ENABLE_TRF_FOR_NS := 2 466 467# Linux relies on EL3 enablement if those features are present 468ENABLE_FEAT_FGT := 2 469ENABLE_FEAT_HCX := 2 470 471ifeq (${SPMC_AT_EL3}, 1) 472PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 473endif 474