1 /* 2 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/el3_runtime/context_mgmt.h> 23 #include <lib/el3_runtime/pubsub_events.h> 24 #include <lib/extensions/amu.h> 25 #include <lib/extensions/brbe.h> 26 #include <lib/extensions/mpam.h> 27 #include <lib/extensions/sme.h> 28 #include <lib/extensions/spe.h> 29 #include <lib/extensions/sve.h> 30 #include <lib/extensions/sys_reg_trace.h> 31 #include <lib/extensions/trbe.h> 32 #include <lib/extensions/trf.h> 33 #include <lib/utils.h> 34 35 #if ENABLE_FEAT_TWED 36 /* Make sure delay value fits within the range(0-15) */ 37 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 38 #endif /* ENABLE_FEAT_TWED */ 39 40 static void manage_extensions_secure(cpu_context_t *ctx); 41 42 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 43 { 44 u_register_t sctlr_elx, actlr_elx; 45 46 /* 47 * Initialise SCTLR_EL1 to the reset value corresponding to the target 48 * execution state setting all fields rather than relying on the hw. 49 * Some fields have architecturally UNKNOWN reset values and these are 50 * set to zero. 51 * 52 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 53 * 54 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 55 * required by PSCI specification) 56 */ 57 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 58 if (GET_RW(ep->spsr) == MODE_RW_64) { 59 sctlr_elx |= SCTLR_EL1_RES1; 60 } else { 61 /* 62 * If the target execution state is AArch32 then the following 63 * fields need to be set. 64 * 65 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 66 * instructions are not trapped to EL1. 67 * 68 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 69 * instructions are not trapped to EL1. 70 * 71 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 72 * CP15DMB, CP15DSB, and CP15ISB instructions. 73 */ 74 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 75 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 76 } 77 78 #if ERRATA_A75_764081 79 /* 80 * If workaround of errata 764081 for Cortex-A75 is used then set 81 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 82 */ 83 sctlr_elx |= SCTLR_IESB_BIT; 84 #endif 85 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 86 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 87 88 /* 89 * Base the context ACTLR_EL1 on the current value, as it is 90 * implementation defined. The context restore process will write 91 * the value from the context to the actual register and can cause 92 * problems for processor cores that don't expect certain bits to 93 * be zero. 94 */ 95 actlr_elx = read_actlr_el1(); 96 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 97 } 98 99 /****************************************************************************** 100 * This function performs initializations that are specific to SECURE state 101 * and updates the cpu context specified by 'ctx'. 102 *****************************************************************************/ 103 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 104 { 105 u_register_t scr_el3; 106 el3_state_t *state; 107 108 state = get_el3state_ctx(ctx); 109 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 110 111 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 112 /* 113 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 114 * indicated by the interrupt routing model for BL31. 115 */ 116 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 117 #endif 118 119 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 120 /* Get Memory Tagging Extension support level */ 121 unsigned int mte = get_armv8_5_mte_support(); 122 #endif 123 /* 124 * Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS 125 * is set, or when MTE is only implemented at EL0. 126 */ 127 #if CTX_INCLUDE_MTE_REGS 128 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 129 scr_el3 |= SCR_ATA_BIT; 130 #else 131 if (mte == MTE_IMPLEMENTED_EL0) { 132 scr_el3 |= SCR_ATA_BIT; 133 } 134 #endif /* CTX_INCLUDE_MTE_REGS */ 135 136 /* Enable S-EL2 if the next EL is EL2 and S-EL2 is present */ 137 if ((GET_EL(ep->spsr) == MODE_EL2) && is_armv8_4_sel2_present()) { 138 if (GET_RW(ep->spsr) != MODE_RW_64) { 139 ERROR("S-EL2 can not be used in AArch32\n."); 140 panic(); 141 } 142 143 scr_el3 |= SCR_EEL2_BIT; 144 } 145 146 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 147 148 /* 149 * Initialize EL1 context registers unless SPMC is running 150 * at S-EL2. 151 */ 152 #if !SPMD_SPM_AT_SEL2 153 setup_el1_context(ctx, ep); 154 #endif 155 156 manage_extensions_secure(ctx); 157 } 158 159 #if ENABLE_RME 160 /****************************************************************************** 161 * This function performs initializations that are specific to REALM state 162 * and updates the cpu context specified by 'ctx'. 163 *****************************************************************************/ 164 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 165 { 166 u_register_t scr_el3; 167 el3_state_t *state; 168 169 state = get_el3state_ctx(ctx); 170 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 171 172 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT | SCR_EnSCXT_BIT; 173 174 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 175 } 176 #endif /* ENABLE_RME */ 177 178 /****************************************************************************** 179 * This function performs initializations that are specific to NON-SECURE state 180 * and updates the cpu context specified by 'ctx'. 181 *****************************************************************************/ 182 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 183 { 184 u_register_t scr_el3; 185 el3_state_t *state; 186 187 state = get_el3state_ctx(ctx); 188 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 189 190 /* SCR_NS: Set the NS bit */ 191 scr_el3 |= SCR_NS_BIT; 192 193 #if !CTX_INCLUDE_PAUTH_REGS 194 /* 195 * If the pointer authentication registers aren't saved during world 196 * switches the value of the registers can be leaked from the Secure to 197 * the Non-secure world. To prevent this, rather than enabling pointer 198 * authentication everywhere, we only enable it in the Non-secure world. 199 * 200 * If the Secure world wants to use pointer authentication, 201 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 202 */ 203 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 204 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 205 206 /* Allow access to Allocation Tags when MTE is implemented. */ 207 scr_el3 |= SCR_ATA_BIT; 208 209 #ifdef IMAGE_BL31 210 /* 211 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 212 * indicated by the interrupt routing model for BL31. 213 */ 214 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 215 #endif 216 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 217 218 /* Initialize EL1 context registers */ 219 setup_el1_context(ctx, ep); 220 221 /* Initialize EL2 context registers */ 222 #if CTX_INCLUDE_EL2_REGS 223 224 /* 225 * Initialize SCTLR_EL2 context register using Endianness value 226 * taken from the entrypoint attribute. 227 */ 228 u_register_t sctlr_el2 = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 229 sctlr_el2 |= SCTLR_EL2_RES1; 230 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2, 231 sctlr_el2); 232 233 /* 234 * Program the ICC_SRE_EL2 to make sure the correct bits are set 235 * when restoring NS context. 236 */ 237 u_register_t icc_sre_el2 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 238 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 239 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_ICC_SRE_EL2, 240 icc_sre_el2); 241 #endif /* CTX_INCLUDE_EL2_REGS */ 242 } 243 244 /******************************************************************************* 245 * The following function performs initialization of the cpu_context 'ctx' 246 * for first use that is common to all security states, and sets the 247 * initial entrypoint state as specified by the entry_point_info structure. 248 * 249 * The EE and ST attributes are used to configure the endianness and secure 250 * timer availability for the new execution context. 251 ******************************************************************************/ 252 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 253 { 254 u_register_t scr_el3; 255 el3_state_t *state; 256 gp_regs_t *gp_regs; 257 258 /* Clear any residual register values from the context */ 259 zeromem(ctx, sizeof(*ctx)); 260 261 /* 262 * SCR_EL3 was initialised during reset sequence in macro 263 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 264 * affect the next EL. 265 * 266 * The following fields are initially set to zero and then updated to 267 * the required value depending on the state of the SPSR_EL3 and the 268 * Security state and entrypoint attributes of the next EL. 269 */ 270 scr_el3 = read_scr(); 271 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 272 SCR_ST_BIT | SCR_HCE_BIT | SCR_NSE_BIT); 273 274 /* 275 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 276 * Exception level as specified by SPSR. 277 */ 278 if (GET_RW(ep->spsr) == MODE_RW_64) { 279 scr_el3 |= SCR_RW_BIT; 280 } 281 282 /* 283 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 284 * Secure timer registers to EL3, from AArch64 state only, if specified 285 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 286 * bit always behaves as 1 (i.e. secure physical timer register access 287 * is not trapped) 288 */ 289 if (EP_GET_ST(ep->h.attr) != 0U) { 290 scr_el3 |= SCR_ST_BIT; 291 } 292 293 /* 294 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 295 * SCR_EL3.HXEn. 296 */ 297 #if ENABLE_FEAT_HCX 298 scr_el3 |= SCR_HXEn_BIT; 299 #endif 300 301 /* 302 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 303 * registers are trapped to EL3. 304 */ 305 #if ENABLE_FEAT_RNG_TRAP 306 scr_el3 |= SCR_TRNDR_BIT; 307 #endif 308 309 #if RAS_TRAP_LOWER_EL_ERR_ACCESS 310 /* 311 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 312 * and RAS ERX registers from EL1 and EL2 are trapped to EL3. 313 */ 314 scr_el3 |= SCR_TERR_BIT; 315 #endif 316 317 #if !HANDLE_EA_EL3_FIRST 318 /* 319 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 320 * to EL3 when executing at a lower EL. When executing at EL3, External 321 * Aborts are taken to EL3. 322 */ 323 scr_el3 &= ~SCR_EA_BIT; 324 #endif 325 326 #if FAULT_INJECTION_SUPPORT 327 /* Enable fault injection from lower ELs */ 328 scr_el3 |= SCR_FIEN_BIT; 329 #endif 330 331 /* 332 * CPTR_EL3 was initialized out of reset, copy that value to the 333 * context register. 334 */ 335 write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3()); 336 337 /* 338 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 339 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 340 * next mode is Hyp. 341 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 342 * same conditions as HVC instructions and when the processor supports 343 * ARMv8.6-FGT. 344 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 345 * CNTPOFF_EL2 register under the same conditions as HVC instructions 346 * and when the processor supports ECV. 347 */ 348 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 349 || ((GET_RW(ep->spsr) != MODE_RW_64) 350 && (GET_M32(ep->spsr) == MODE32_hyp))) { 351 scr_el3 |= SCR_HCE_BIT; 352 353 if (is_armv8_6_fgt_present()) { 354 scr_el3 |= SCR_FGTEN_BIT; 355 } 356 357 if (get_armv8_6_ecv_support() 358 == ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) { 359 scr_el3 |= SCR_ECVEN_BIT; 360 } 361 } 362 363 #if ENABLE_FEAT_TWED 364 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 365 /* Set delay in SCR_EL3 */ 366 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 367 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 368 << SCR_TWEDEL_SHIFT); 369 370 /* Enable WFE delay */ 371 scr_el3 |= SCR_TWEDEn_BIT; 372 #endif /* ENABLE_FEAT_TWED */ 373 374 /* 375 * Populate EL3 state so that we've the right context 376 * before doing ERET 377 */ 378 state = get_el3state_ctx(ctx); 379 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 380 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 381 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 382 383 /* 384 * Store the X0-X7 value from the entrypoint into the context 385 * Use memcpy as we are in control of the layout of the structures 386 */ 387 gp_regs = get_gpregs_ctx(ctx); 388 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 389 } 390 391 /******************************************************************************* 392 * Context management library initialization routine. This library is used by 393 * runtime services to share pointers to 'cpu_context' structures for secure 394 * non-secure and realm states. Management of the structures and their associated 395 * memory is not done by the context management library e.g. the PSCI service 396 * manages the cpu context used for entry from and exit to the non-secure state. 397 * The Secure payload dispatcher service manages the context(s) corresponding to 398 * the secure state. It also uses this library to get access to the non-secure 399 * state cpu context pointers. 400 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 401 * which will be used for programming an entry into a lower EL. The same context 402 * will be used to save state upon exception entry from that EL. 403 ******************************************************************************/ 404 void __init cm_init(void) 405 { 406 /* 407 * The context management library has only global data to intialize, but 408 * that will be done when the BSS is zeroed out. 409 */ 410 } 411 412 /******************************************************************************* 413 * This is the high-level function used to initialize the cpu_context 'ctx' for 414 * first use. It performs initializations that are common to all security states 415 * and initializations specific to the security state specified in 'ep' 416 ******************************************************************************/ 417 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 418 { 419 unsigned int security_state; 420 421 assert(ctx != NULL); 422 423 /* 424 * Perform initializations that are common 425 * to all security states 426 */ 427 setup_context_common(ctx, ep); 428 429 security_state = GET_SECURITY_STATE(ep->h.attr); 430 431 /* Perform security state specific initializations */ 432 switch (security_state) { 433 case SECURE: 434 setup_secure_context(ctx, ep); 435 break; 436 #if ENABLE_RME 437 case REALM: 438 setup_realm_context(ctx, ep); 439 break; 440 #endif 441 case NON_SECURE: 442 setup_ns_context(ctx, ep); 443 break; 444 default: 445 ERROR("Invalid security state\n"); 446 panic(); 447 break; 448 } 449 } 450 451 /******************************************************************************* 452 * Enable architecture extensions on first entry to Non-secure world. 453 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 454 * it is zero. 455 ******************************************************************************/ 456 static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx) 457 { 458 #if IMAGE_BL31 459 #if ENABLE_SPE_FOR_LOWER_ELS 460 spe_enable(el2_unused); 461 #endif 462 463 #if ENABLE_AMU 464 amu_enable(el2_unused, ctx); 465 #endif 466 467 #if ENABLE_SME_FOR_NS 468 /* Enable SME, SVE, and FPU/SIMD for non-secure world. */ 469 sme_enable(ctx); 470 #elif ENABLE_SVE_FOR_NS 471 /* Enable SVE and FPU/SIMD for non-secure world. */ 472 sve_enable(ctx); 473 #endif 474 475 #if ENABLE_MPAM_FOR_LOWER_ELS 476 mpam_enable(el2_unused); 477 #endif 478 479 #if ENABLE_TRBE_FOR_NS 480 trbe_enable(); 481 #endif /* ENABLE_TRBE_FOR_NS */ 482 483 #if ENABLE_BRBE_FOR_NS 484 brbe_enable(); 485 #endif /* ENABLE_BRBE_FOR_NS */ 486 487 #if ENABLE_SYS_REG_TRACE_FOR_NS 488 sys_reg_trace_enable(ctx); 489 #endif /* ENABLE_SYS_REG_TRACE_FOR_NS */ 490 491 #if ENABLE_TRF_FOR_NS 492 trf_enable(); 493 #endif /* ENABLE_TRF_FOR_NS */ 494 #endif 495 } 496 497 /******************************************************************************* 498 * Enable architecture extensions on first entry to Secure world. 499 ******************************************************************************/ 500 static void manage_extensions_secure(cpu_context_t *ctx) 501 { 502 #if IMAGE_BL31 503 #if ENABLE_SME_FOR_NS 504 #if ENABLE_SME_FOR_SWD 505 /* 506 * Enable SME, SVE, FPU/SIMD in secure context, secure manager must 507 * ensure SME, SVE, and FPU/SIMD context properly managed. 508 */ 509 sme_enable(ctx); 510 #else /* ENABLE_SME_FOR_SWD */ 511 /* 512 * Disable SME, SVE, FPU/SIMD in secure context so non-secure world can 513 * safely use the associated registers. 514 */ 515 sme_disable(ctx); 516 #endif /* ENABLE_SME_FOR_SWD */ 517 #elif ENABLE_SVE_FOR_NS 518 #if ENABLE_SVE_FOR_SWD 519 /* 520 * Enable SVE and FPU in secure context, secure manager must ensure that 521 * the SVE and FPU register contexts are properly managed. 522 */ 523 sve_enable(ctx); 524 #else /* ENABLE_SVE_FOR_SWD */ 525 /* 526 * Disable SVE and FPU in secure context so non-secure world can safely 527 * use them. 528 */ 529 sve_disable(ctx); 530 #endif /* ENABLE_SVE_FOR_SWD */ 531 #endif /* ENABLE_SVE_FOR_NS */ 532 #endif /* IMAGE_BL31 */ 533 } 534 535 /******************************************************************************* 536 * The following function initializes the cpu_context for a CPU specified by 537 * its `cpu_idx` for first use, and sets the initial entrypoint state as 538 * specified by the entry_point_info structure. 539 ******************************************************************************/ 540 void cm_init_context_by_index(unsigned int cpu_idx, 541 const entry_point_info_t *ep) 542 { 543 cpu_context_t *ctx; 544 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 545 cm_setup_context(ctx, ep); 546 } 547 548 /******************************************************************************* 549 * The following function initializes the cpu_context for the current CPU 550 * for first use, and sets the initial entrypoint state as specified by the 551 * entry_point_info structure. 552 ******************************************************************************/ 553 void cm_init_my_context(const entry_point_info_t *ep) 554 { 555 cpu_context_t *ctx; 556 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 557 cm_setup_context(ctx, ep); 558 } 559 560 /******************************************************************************* 561 * Prepare the CPU system registers for first entry into realm, secure, or 562 * normal world. 563 * 564 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 565 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 566 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 567 * For all entries, the EL1 registers are initialized from the cpu_context 568 ******************************************************************************/ 569 void cm_prepare_el3_exit(uint32_t security_state) 570 { 571 u_register_t sctlr_elx, scr_el3, mdcr_el2; 572 cpu_context_t *ctx = cm_get_context(security_state); 573 bool el2_unused = false; 574 uint64_t hcr_el2 = 0U; 575 576 assert(ctx != NULL); 577 578 if (security_state == NON_SECURE) { 579 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 580 CTX_SCR_EL3); 581 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 582 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 583 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 584 CTX_SCTLR_EL1); 585 sctlr_elx &= SCTLR_EE_BIT; 586 sctlr_elx |= SCTLR_EL2_RES1; 587 #if ERRATA_A75_764081 588 /* 589 * If workaround of errata 764081 for Cortex-A75 is used 590 * then set SCTLR_EL2.IESB to enable Implicit Error 591 * Synchronization Barrier. 592 */ 593 sctlr_elx |= SCTLR_IESB_BIT; 594 #endif 595 write_sctlr_el2(sctlr_elx); 596 } else if (el_implemented(2) != EL_IMPL_NONE) { 597 el2_unused = true; 598 599 /* 600 * EL2 present but unused, need to disable safely. 601 * SCTLR_EL2 can be ignored in this case. 602 * 603 * Set EL2 register width appropriately: Set HCR_EL2 604 * field to match SCR_EL3.RW. 605 */ 606 if ((scr_el3 & SCR_RW_BIT) != 0U) 607 hcr_el2 |= HCR_RW_BIT; 608 609 /* 610 * For Armv8.3 pointer authentication feature, disable 611 * traps to EL2 when accessing key registers or using 612 * pointer authentication instructions from lower ELs. 613 */ 614 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 615 616 write_hcr_el2(hcr_el2); 617 618 /* 619 * Initialise CPTR_EL2 setting all fields rather than 620 * relying on the hw. All fields have architecturally 621 * UNKNOWN reset values. 622 * 623 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 624 * accesses to the CPACR_EL1 or CPACR from both 625 * Execution states do not trap to EL2. 626 * 627 * CPTR_EL2.TTA: Set to zero so that Non-secure System 628 * register accesses to the trace registers from both 629 * Execution states do not trap to EL2. 630 * If PE trace unit System registers are not implemented 631 * then this bit is reserved, and must be set to zero. 632 * 633 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 634 * to SIMD and floating-point functionality from both 635 * Execution states do not trap to EL2. 636 */ 637 write_cptr_el2(CPTR_EL2_RESET_VAL & 638 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 639 | CPTR_EL2_TFP_BIT)); 640 641 /* 642 * Initialise CNTHCTL_EL2. All fields are 643 * architecturally UNKNOWN on reset and are set to zero 644 * except for field(s) listed below. 645 * 646 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to 647 * Hyp mode of Non-secure EL0 and EL1 accesses to the 648 * physical timer registers. 649 * 650 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 651 * Hyp mode of Non-secure EL0 and EL1 accesses to the 652 * physical counter registers. 653 */ 654 write_cnthctl_el2(CNTHCTL_RESET_VAL | 655 EL1PCEN_BIT | EL1PCTEN_BIT); 656 657 /* 658 * Initialise CNTVOFF_EL2 to zero as it resets to an 659 * architecturally UNKNOWN value. 660 */ 661 write_cntvoff_el2(0); 662 663 /* 664 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 665 * MPIDR_EL1 respectively. 666 */ 667 write_vpidr_el2(read_midr_el1()); 668 write_vmpidr_el2(read_mpidr_el1()); 669 670 /* 671 * Initialise VTTBR_EL2. All fields are architecturally 672 * UNKNOWN on reset. 673 * 674 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 675 * 2 address translation is disabled, cache maintenance 676 * operations depend on the VMID. 677 * 678 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 679 * translation is disabled. 680 */ 681 write_vttbr_el2(VTTBR_RESET_VAL & 682 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 683 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 684 685 /* 686 * Initialise MDCR_EL2, setting all fields rather than 687 * relying on hw. Some fields are architecturally 688 * UNKNOWN on reset. 689 * 690 * MDCR_EL2.HLP: Set to one so that event counter 691 * overflow, that is recorded in PMOVSCLR_EL0[0-30], 692 * occurs on the increment that changes 693 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is 694 * implemented. This bit is RES0 in versions of the 695 * architecture earlier than ARMv8.5, setting it to 1 696 * doesn't have any effect on them. 697 * 698 * MDCR_EL2.TTRF: Set to zero so that access to Trace 699 * Filter Control register TRFCR_EL1 at EL1 is not 700 * trapped to EL2. This bit is RES0 in versions of 701 * the architecture earlier than ARMv8.4. 702 * 703 * MDCR_EL2.HPMD: Set to one so that event counting is 704 * prohibited at EL2. This bit is RES0 in versions of 705 * the architecture earlier than ARMv8.1, setting it 706 * to 1 doesn't have any effect on them. 707 * 708 * MDCR_EL2.TPMS: Set to zero so that accesses to 709 * Statistical Profiling control registers from EL1 710 * do not trap to EL2. This bit is RES0 when SPE is 711 * not implemented. 712 * 713 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 714 * EL1 System register accesses to the Debug ROM 715 * registers are not trapped to EL2. 716 * 717 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 718 * System register accesses to the powerdown debug 719 * registers are not trapped to EL2. 720 * 721 * MDCR_EL2.TDA: Set to zero so that System register 722 * accesses to the debug registers do not trap to EL2. 723 * 724 * MDCR_EL2.TDE: Set to zero so that debug exceptions 725 * are not routed to EL2. 726 * 727 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 728 * Monitors. 729 * 730 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 731 * EL1 accesses to all Performance Monitors registers 732 * are not trapped to EL2. 733 * 734 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 735 * and EL1 accesses to the PMCR_EL0 or PMCR are not 736 * trapped to EL2. 737 * 738 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 739 * architecturally-defined reset value. 740 * 741 * MDCR_EL2.E2TB: Set to zero so that the trace Buffer 742 * owning exception level is NS-EL1 and, tracing is 743 * prohibited at NS-EL2. These bits are RES0 when 744 * FEAT_TRBE is not implemented. 745 */ 746 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | 747 MDCR_EL2_HPMD) | 748 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 749 >> PMCR_EL0_N_SHIFT)) & 750 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | 751 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | 752 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | 753 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | 754 MDCR_EL2_TPMCR_BIT | 755 MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1)); 756 757 write_mdcr_el2(mdcr_el2); 758 759 /* 760 * Initialise HSTR_EL2. All fields are architecturally 761 * UNKNOWN on reset. 762 * 763 * HSTR_EL2.T<n>: Set all these fields to zero so that 764 * Non-secure EL0 or EL1 accesses to System registers 765 * do not trap to EL2. 766 */ 767 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 768 /* 769 * Initialise CNTHP_CTL_EL2. All fields are 770 * architecturally UNKNOWN on reset. 771 * 772 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 773 * physical timer and prevent timer interrupts. 774 */ 775 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 776 ~(CNTHP_CTL_ENABLE_BIT)); 777 } 778 manage_extensions_nonsecure(el2_unused, ctx); 779 } 780 781 cm_el1_sysregs_context_restore(security_state); 782 cm_set_next_eret_context(security_state); 783 } 784 785 #if CTX_INCLUDE_EL2_REGS 786 /******************************************************************************* 787 * Save EL2 sysreg context 788 ******************************************************************************/ 789 void cm_el2_sysregs_context_save(uint32_t security_state) 790 { 791 u_register_t scr_el3 = read_scr(); 792 793 /* 794 * Always save the non-secure and realm EL2 context, only save the 795 * S-EL2 context if S-EL2 is enabled. 796 */ 797 if ((security_state != SECURE) || 798 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 799 cpu_context_t *ctx; 800 el2_sysregs_t *el2_sysregs_ctx; 801 802 ctx = cm_get_context(security_state); 803 assert(ctx != NULL); 804 805 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 806 807 el2_sysregs_context_save_common(el2_sysregs_ctx); 808 #if ENABLE_SPE_FOR_LOWER_ELS 809 el2_sysregs_context_save_spe(el2_sysregs_ctx); 810 #endif 811 #if CTX_INCLUDE_MTE_REGS 812 el2_sysregs_context_save_mte(el2_sysregs_ctx); 813 #endif 814 #if ENABLE_MPAM_FOR_LOWER_ELS 815 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 816 #endif 817 #if ENABLE_FEAT_FGT 818 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 819 #endif 820 #if ENABLE_FEAT_ECV 821 el2_sysregs_context_save_ecv(el2_sysregs_ctx); 822 #endif 823 #if ENABLE_FEAT_VHE 824 el2_sysregs_context_save_vhe(el2_sysregs_ctx); 825 #endif 826 #if RAS_EXTENSION 827 el2_sysregs_context_save_ras(el2_sysregs_ctx); 828 #endif 829 #if CTX_INCLUDE_NEVE_REGS 830 el2_sysregs_context_save_nv2(el2_sysregs_ctx); 831 #endif 832 #if ENABLE_TRF_FOR_NS 833 el2_sysregs_context_save_trf(el2_sysregs_ctx); 834 #endif 835 #if ENABLE_FEAT_CSV2_2 836 el2_sysregs_context_save_csv2(el2_sysregs_ctx); 837 #endif 838 #if ENABLE_FEAT_HCX 839 el2_sysregs_context_save_hcx(el2_sysregs_ctx); 840 #endif 841 } 842 } 843 844 /******************************************************************************* 845 * Restore EL2 sysreg context 846 ******************************************************************************/ 847 void cm_el2_sysregs_context_restore(uint32_t security_state) 848 { 849 u_register_t scr_el3 = read_scr(); 850 851 /* 852 * Always restore the non-secure and realm EL2 context, only restore the 853 * S-EL2 context if S-EL2 is enabled. 854 */ 855 if ((security_state != SECURE) || 856 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 857 cpu_context_t *ctx; 858 el2_sysregs_t *el2_sysregs_ctx; 859 860 ctx = cm_get_context(security_state); 861 assert(ctx != NULL); 862 863 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 864 865 el2_sysregs_context_restore_common(el2_sysregs_ctx); 866 #if ENABLE_SPE_FOR_LOWER_ELS 867 el2_sysregs_context_restore_spe(el2_sysregs_ctx); 868 #endif 869 #if CTX_INCLUDE_MTE_REGS 870 el2_sysregs_context_restore_mte(el2_sysregs_ctx); 871 #endif 872 #if ENABLE_MPAM_FOR_LOWER_ELS 873 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 874 #endif 875 #if ENABLE_FEAT_FGT 876 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 877 #endif 878 #if ENABLE_FEAT_ECV 879 el2_sysregs_context_restore_ecv(el2_sysregs_ctx); 880 #endif 881 #if ENABLE_FEAT_VHE 882 el2_sysregs_context_restore_vhe(el2_sysregs_ctx); 883 #endif 884 #if RAS_EXTENSION 885 el2_sysregs_context_restore_ras(el2_sysregs_ctx); 886 #endif 887 #if CTX_INCLUDE_NEVE_REGS 888 el2_sysregs_context_restore_nv2(el2_sysregs_ctx); 889 #endif 890 #if ENABLE_TRF_FOR_NS 891 el2_sysregs_context_restore_trf(el2_sysregs_ctx); 892 #endif 893 #if ENABLE_FEAT_CSV2_2 894 el2_sysregs_context_restore_csv2(el2_sysregs_ctx); 895 #endif 896 #if ENABLE_FEAT_HCX 897 el2_sysregs_context_restore_hcx(el2_sysregs_ctx); 898 #endif 899 } 900 } 901 #endif /* CTX_INCLUDE_EL2_REGS */ 902 903 /******************************************************************************* 904 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 905 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 906 * updating EL1 and EL2 registers. Otherwise, it calls the generic 907 * cm_prepare_el3_exit function. 908 ******************************************************************************/ 909 void cm_prepare_el3_exit_ns(void) 910 { 911 #if CTX_INCLUDE_EL2_REGS 912 cpu_context_t *ctx = cm_get_context(NON_SECURE); 913 assert(ctx != NULL); 914 915 /* Assert that EL2 is used. */ 916 #if ENABLE_ASSERTIONS 917 el3_state_t *state = get_el3state_ctx(ctx); 918 u_register_t scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 919 #endif 920 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 921 (el_implemented(2U) != EL_IMPL_NONE)); 922 923 /* 924 * Currently some extensions are configured using 925 * direct register updates. Therefore, do this here 926 * instead of when setting up context. 927 */ 928 manage_extensions_nonsecure(0, ctx); 929 930 /* 931 * Set the NS bit to be able to access the ICC_SRE_EL2 932 * register when restoring context. 933 */ 934 write_scr_el3(read_scr_el3() | SCR_NS_BIT); 935 936 /* 937 * Ensure the NS bit change is committed before the EL2/EL1 938 * state restoration. 939 */ 940 isb(); 941 942 /* Restore EL2 and EL1 sysreg contexts */ 943 cm_el2_sysregs_context_restore(NON_SECURE); 944 cm_el1_sysregs_context_restore(NON_SECURE); 945 cm_set_next_eret_context(NON_SECURE); 946 #else 947 cm_prepare_el3_exit(NON_SECURE); 948 #endif /* CTX_INCLUDE_EL2_REGS */ 949 } 950 951 /******************************************************************************* 952 * The next four functions are used by runtime services to save and restore 953 * EL1 context on the 'cpu_context' structure for the specified security 954 * state. 955 ******************************************************************************/ 956 void cm_el1_sysregs_context_save(uint32_t security_state) 957 { 958 cpu_context_t *ctx; 959 960 ctx = cm_get_context(security_state); 961 assert(ctx != NULL); 962 963 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 964 965 #if IMAGE_BL31 966 if (security_state == SECURE) 967 PUBLISH_EVENT(cm_exited_secure_world); 968 else 969 PUBLISH_EVENT(cm_exited_normal_world); 970 #endif 971 } 972 973 void cm_el1_sysregs_context_restore(uint32_t security_state) 974 { 975 cpu_context_t *ctx; 976 977 ctx = cm_get_context(security_state); 978 assert(ctx != NULL); 979 980 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 981 982 #if IMAGE_BL31 983 if (security_state == SECURE) 984 PUBLISH_EVENT(cm_entering_secure_world); 985 else 986 PUBLISH_EVENT(cm_entering_normal_world); 987 #endif 988 } 989 990 /******************************************************************************* 991 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 992 * given security state with the given entrypoint 993 ******************************************************************************/ 994 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 995 { 996 cpu_context_t *ctx; 997 el3_state_t *state; 998 999 ctx = cm_get_context(security_state); 1000 assert(ctx != NULL); 1001 1002 /* Populate EL3 state so that ERET jumps to the correct entry */ 1003 state = get_el3state_ctx(ctx); 1004 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1005 } 1006 1007 /******************************************************************************* 1008 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1009 * pertaining to the given security state 1010 ******************************************************************************/ 1011 void cm_set_elr_spsr_el3(uint32_t security_state, 1012 uintptr_t entrypoint, uint32_t spsr) 1013 { 1014 cpu_context_t *ctx; 1015 el3_state_t *state; 1016 1017 ctx = cm_get_context(security_state); 1018 assert(ctx != NULL); 1019 1020 /* Populate EL3 state so that ERET jumps to the correct entry */ 1021 state = get_el3state_ctx(ctx); 1022 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1023 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1024 } 1025 1026 /******************************************************************************* 1027 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1028 * pertaining to the given security state using the value and bit position 1029 * specified in the parameters. It preserves all other bits. 1030 ******************************************************************************/ 1031 void cm_write_scr_el3_bit(uint32_t security_state, 1032 uint32_t bit_pos, 1033 uint32_t value) 1034 { 1035 cpu_context_t *ctx; 1036 el3_state_t *state; 1037 u_register_t scr_el3; 1038 1039 ctx = cm_get_context(security_state); 1040 assert(ctx != NULL); 1041 1042 /* Ensure that the bit position is a valid one */ 1043 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1044 1045 /* Ensure that the 'value' is only a bit wide */ 1046 assert(value <= 1U); 1047 1048 /* 1049 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1050 * and set it to its new value. 1051 */ 1052 state = get_el3state_ctx(ctx); 1053 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1054 scr_el3 &= ~(1UL << bit_pos); 1055 scr_el3 |= (u_register_t)value << bit_pos; 1056 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1057 } 1058 1059 /******************************************************************************* 1060 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1061 * given security state. 1062 ******************************************************************************/ 1063 u_register_t cm_get_scr_el3(uint32_t security_state) 1064 { 1065 cpu_context_t *ctx; 1066 el3_state_t *state; 1067 1068 ctx = cm_get_context(security_state); 1069 assert(ctx != NULL); 1070 1071 /* Populate EL3 state so that ERET jumps to the correct entry */ 1072 state = get_el3state_ctx(ctx); 1073 return read_ctx_reg(state, CTX_SCR_EL3); 1074 } 1075 1076 /******************************************************************************* 1077 * This function is used to program the context that's used for exception 1078 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1079 * the required security state 1080 ******************************************************************************/ 1081 void cm_set_next_eret_context(uint32_t security_state) 1082 { 1083 cpu_context_t *ctx; 1084 1085 ctx = cm_get_context(security_state); 1086 assert(ctx != NULL); 1087 1088 cm_set_next_context(ctx); 1089 } 1090