1/* 2 * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <arch.h> 10#include <asm_macros.S> 11#include <bl31/ea_handle.h> 12#include <bl31/interrupt_mgmt.h> 13#include <bl31/sync_handle.h> 14#include <common/runtime_svc.h> 15#include <context.h> 16#include <el3_common_macros.S> 17#include <lib/el3_runtime/cpu_data.h> 18#include <lib/smccc.h> 19 20 .globl runtime_exceptions 21 22 .globl sync_exception_sp_el0 23 .globl irq_sp_el0 24 .globl fiq_sp_el0 25 .globl serror_sp_el0 26 27 .globl sync_exception_sp_elx 28 .globl irq_sp_elx 29 .globl fiq_sp_elx 30 .globl serror_sp_elx 31 32 .globl sync_exception_aarch64 33 .globl irq_aarch64 34 .globl fiq_aarch64 35 .globl serror_aarch64 36 37 .globl sync_exception_aarch32 38 .globl irq_aarch32 39 .globl fiq_aarch32 40 .globl serror_aarch32 41 42 /* 43 * Macro that prepares entry to EL3 upon taking an exception. 44 * 45 * With RAS_EXTENSION, this macro synchronizes pending errors with an ESB 46 * instruction. When an error is thus synchronized, the handling is 47 * delegated to platform EA handler. 48 * 49 * Without RAS_EXTENSION, this macro synchronizes pending errors using 50 * a DSB, unmasks Asynchronous External Aborts and saves X30 before 51 * setting the flag CTX_IS_IN_EL3. 52 */ 53 .macro check_and_unmask_ea 54#if RAS_EXTENSION 55 /* Synchronize pending External Aborts */ 56 esb 57 58 /* Unmask the SError interrupt */ 59 msr daifclr, #DAIF_ABT_BIT 60 61 /* 62 * Explicitly save x30 so as to free up a register and to enable 63 * branching 64 */ 65 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 66 67 /* Check for SErrors synchronized by the ESB instruction */ 68 mrs x30, DISR_EL1 69 tbz x30, #DISR_A_BIT, 1f 70 71 /* 72 * Save general purpose and ARMv8.3-PAuth registers (if enabled). 73 * If Secure Cycle Counter is not disabled in MDCR_EL3 when 74 * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. 75 * Also set the PSTATE to a known state. 76 */ 77 bl prepare_el3_entry 78 79 bl handle_lower_el_ea_esb 80 81 /* Restore general purpose, PMCR_EL0 and ARMv8.3-PAuth registers */ 82 bl restore_gp_pmcr_pauth_regs 831: 84#else 85 /* 86 * Note 1: The explicit DSB at the entry of various exception vectors 87 * for handling exceptions from lower ELs can inadvertently trigger an 88 * SError exception in EL3 due to pending asynchronous aborts in lower 89 * ELs. This will end up being handled by serror_sp_elx which will 90 * ultimately panic and die. 91 * The way to workaround is to update a flag to indicate if the exception 92 * truly came from EL3. This flag is allocated in the cpu_context 93 * structure and located at offset "CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3" 94 * This is not a bullet proof solution to the problem at hand because 95 * we assume the instructions following "isb" that help to update the 96 * flag execute without causing further exceptions. 97 */ 98 99 /* 100 * For SoCs which do not implement RAS, use DSB as a barrier to 101 * synchronize pending external aborts. 102 */ 103 dsb sy 104 105 /* Unmask the SError interrupt */ 106 msr daifclr, #DAIF_ABT_BIT 107 108 /* Use ISB for the above unmask operation to take effect immediately */ 109 isb 110 111 /* 112 * Refer Note 1. 113 * No need to restore X30 as macros following this modify x30 anyway. 114 */ 115 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 116 mov x30, #1 117 str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3] 118 dmb sy 119#endif 120 .endm 121 122 /* --------------------------------------------------------------------- 123 * This macro handles Synchronous exceptions. 124 * Only SMC exceptions are supported. 125 * --------------------------------------------------------------------- 126 */ 127 .macro handle_sync_exception 128#if ENABLE_RUNTIME_INSTRUMENTATION 129 /* 130 * Read the timestamp value and store it in per-cpu data. The value 131 * will be extracted from per-cpu data by the C level SMC handler and 132 * saved to the PMF timestamp region. 133 */ 134 mrs x30, cntpct_el0 135 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 136 mrs x29, tpidr_el3 137 str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET] 138 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 139#endif 140 141 mrs x30, esr_el3 142 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 143 144 /* Handle SMC exceptions separately from other synchronous exceptions */ 145 cmp x30, #EC_AARCH32_SMC 146 b.eq smc_handler32 147 148 cmp x30, #EC_AARCH64_SMC 149 b.eq sync_handler64 150 151 cmp x30, #EC_AARCH64_SYS 152 b.eq sync_handler64 153 154 /* Synchronous exceptions other than the above are assumed to be EA */ 155 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 156 b enter_lower_el_sync_ea 157 .endm 158 159 160 /* --------------------------------------------------------------------- 161 * This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS 162 * interrupts. 163 * --------------------------------------------------------------------- 164 */ 165 .macro handle_interrupt_exception label 166 167 /* 168 * Save general purpose and ARMv8.3-PAuth registers (if enabled). 169 * If Secure Cycle Counter is not disabled in MDCR_EL3 when 170 * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. 171 * Also set the PSTATE to a known state. 172 */ 173 bl prepare_el3_entry 174 175#if ENABLE_PAUTH 176 /* Load and program APIAKey firmware key */ 177 bl pauth_load_bl31_apiakey 178#endif 179 180 /* Save the EL3 system registers needed to return from this exception */ 181 mrs x0, spsr_el3 182 mrs x1, elr_el3 183 stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 184 185 /* Switch to the runtime stack i.e. SP_EL0 */ 186 ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 187 mov x20, sp 188 msr spsel, #MODE_SP_EL0 189 mov sp, x2 190 191 /* 192 * Find out whether this is a valid interrupt type. 193 * If the interrupt controller reports a spurious interrupt then return 194 * to where we came from. 195 */ 196 bl plat_ic_get_pending_interrupt_type 197 cmp x0, #INTR_TYPE_INVAL 198 b.eq interrupt_exit_\label 199 200 /* 201 * Get the registered handler for this interrupt type. 202 * A NULL return value could be 'cause of the following conditions: 203 * 204 * a. An interrupt of a type was routed correctly but a handler for its 205 * type was not registered. 206 * 207 * b. An interrupt of a type was not routed correctly so a handler for 208 * its type was not registered. 209 * 210 * c. An interrupt of a type was routed correctly to EL3, but was 211 * deasserted before its pending state could be read. Another 212 * interrupt of a different type pended at the same time and its 213 * type was reported as pending instead. However, a handler for this 214 * type was not registered. 215 * 216 * a. and b. can only happen due to a programming error. The 217 * occurrence of c. could be beyond the control of Trusted Firmware. 218 * It makes sense to return from this exception instead of reporting an 219 * error. 220 */ 221 bl get_interrupt_type_handler 222 cbz x0, interrupt_exit_\label 223 mov x21, x0 224 225 mov x0, #INTR_ID_UNAVAILABLE 226 227 /* Set the current security state in the 'flags' parameter */ 228 mrs x2, scr_el3 229 ubfx x1, x2, #0, #1 230 231 /* Restore the reference to the 'handle' i.e. SP_EL3 */ 232 mov x2, x20 233 234 /* x3 will point to a cookie (not used now) */ 235 mov x3, xzr 236 237 /* Call the interrupt type handler */ 238 blr x21 239 240interrupt_exit_\label: 241 /* Return from exception, possibly in a different security state */ 242 b el3_exit 243 244 .endm 245 246 247vector_base runtime_exceptions 248 249 /* --------------------------------------------------------------------- 250 * Current EL with SP_EL0 : 0x0 - 0x200 251 * --------------------------------------------------------------------- 252 */ 253vector_entry sync_exception_sp_el0 254#ifdef MONITOR_TRAPS 255 stp x29, x30, [sp, #-16]! 256 257 mrs x30, esr_el3 258 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 259 260 /* Check for BRK */ 261 cmp x30, #EC_BRK 262 b.eq brk_handler 263 264 ldp x29, x30, [sp], #16 265#endif /* MONITOR_TRAPS */ 266 267 /* We don't expect any synchronous exceptions from EL3 */ 268 b report_unhandled_exception 269end_vector_entry sync_exception_sp_el0 270 271vector_entry irq_sp_el0 272 /* 273 * EL3 code is non-reentrant. Any asynchronous exception is a serious 274 * error. Loop infinitely. 275 */ 276 b report_unhandled_interrupt 277end_vector_entry irq_sp_el0 278 279 280vector_entry fiq_sp_el0 281 b report_unhandled_interrupt 282end_vector_entry fiq_sp_el0 283 284 285vector_entry serror_sp_el0 286 no_ret plat_handle_el3_ea 287end_vector_entry serror_sp_el0 288 289 /* --------------------------------------------------------------------- 290 * Current EL with SP_ELx: 0x200 - 0x400 291 * --------------------------------------------------------------------- 292 */ 293vector_entry sync_exception_sp_elx 294 /* 295 * This exception will trigger if anything went wrong during a previous 296 * exception entry or exit or while handling an earlier unexpected 297 * synchronous exception. There is a high probability that SP_EL3 is 298 * corrupted. 299 */ 300 b report_unhandled_exception 301end_vector_entry sync_exception_sp_elx 302 303vector_entry irq_sp_elx 304 b report_unhandled_interrupt 305end_vector_entry irq_sp_elx 306 307vector_entry fiq_sp_elx 308 b report_unhandled_interrupt 309end_vector_entry fiq_sp_elx 310 311vector_entry serror_sp_elx 312#if !RAS_EXTENSION 313 /* 314 * This will trigger if the exception was taken due to SError in EL3 or 315 * because of pending asynchronous external aborts from lower EL that got 316 * triggered due to explicit synchronization in EL3. Refer Note 1. 317 */ 318 /* Assumes SP_EL3 on entry */ 319 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 320 ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3] 321 cbnz x30, 1f 322 323 /* Handle asynchronous external abort from lower EL */ 324 b handle_lower_el_async_ea 3251: 326#endif 327 no_ret plat_handle_el3_ea 328end_vector_entry serror_sp_elx 329 330 /* --------------------------------------------------------------------- 331 * Lower EL using AArch64 : 0x400 - 0x600 332 * --------------------------------------------------------------------- 333 */ 334vector_entry sync_exception_aarch64 335 /* 336 * This exception vector will be the entry point for SMCs and traps 337 * that are unhandled at lower ELs most commonly. SP_EL3 should point 338 * to a valid cpu context where the general purpose and system register 339 * state can be saved. 340 */ 341 apply_at_speculative_wa 342 check_and_unmask_ea 343 handle_sync_exception 344end_vector_entry sync_exception_aarch64 345 346vector_entry irq_aarch64 347 apply_at_speculative_wa 348 check_and_unmask_ea 349 handle_interrupt_exception irq_aarch64 350end_vector_entry irq_aarch64 351 352vector_entry fiq_aarch64 353 apply_at_speculative_wa 354 check_and_unmask_ea 355 handle_interrupt_exception fiq_aarch64 356end_vector_entry fiq_aarch64 357 358vector_entry serror_aarch64 359 apply_at_speculative_wa 360#if RAS_EXTENSION 361 msr daifclr, #DAIF_ABT_BIT 362 b enter_lower_el_async_ea 363#else 364 check_and_unmask_ea 365 b handle_lower_el_async_ea 366#endif 367end_vector_entry serror_aarch64 368 369 /* --------------------------------------------------------------------- 370 * Lower EL using AArch32 : 0x600 - 0x800 371 * --------------------------------------------------------------------- 372 */ 373vector_entry sync_exception_aarch32 374 /* 375 * This exception vector will be the entry point for SMCs and traps 376 * that are unhandled at lower ELs most commonly. SP_EL3 should point 377 * to a valid cpu context where the general purpose and system register 378 * state can be saved. 379 */ 380 apply_at_speculative_wa 381 check_and_unmask_ea 382 handle_sync_exception 383end_vector_entry sync_exception_aarch32 384 385vector_entry irq_aarch32 386 apply_at_speculative_wa 387 check_and_unmask_ea 388 handle_interrupt_exception irq_aarch32 389end_vector_entry irq_aarch32 390 391vector_entry fiq_aarch32 392 apply_at_speculative_wa 393 check_and_unmask_ea 394 handle_interrupt_exception fiq_aarch32 395end_vector_entry fiq_aarch32 396 397vector_entry serror_aarch32 398 apply_at_speculative_wa 399#if RAS_EXTENSION 400 msr daifclr, #DAIF_ABT_BIT 401 b enter_lower_el_async_ea 402#else 403 check_and_unmask_ea 404 b handle_lower_el_async_ea 405#endif 406end_vector_entry serror_aarch32 407 408#ifdef MONITOR_TRAPS 409 .section .rodata.brk_string, "aS" 410brk_location: 411 .asciz "Error at instruction 0x" 412brk_message: 413 .asciz "Unexpected BRK instruction with value 0x" 414#endif /* MONITOR_TRAPS */ 415 416 /* --------------------------------------------------------------------- 417 * The following code handles secure monitor calls. 418 * Depending upon the execution state from where the SMC has been 419 * invoked, it frees some general purpose registers to perform the 420 * remaining tasks. They involve finding the runtime service handler 421 * that is the target of the SMC & switching to runtime stacks (SP_EL0) 422 * before calling the handler. 423 * 424 * Note that x30 has been explicitly saved and can be used here 425 * --------------------------------------------------------------------- 426 */ 427func sync_exception_handler 428smc_handler32: 429 /* Check whether aarch32 issued an SMC64 */ 430 tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited 431 432sync_handler64: 433 /* NOTE: The code below must preserve x0-x4 */ 434 435 /* 436 * Save general purpose and ARMv8.3-PAuth registers (if enabled). 437 * If Secure Cycle Counter is not disabled in MDCR_EL3 when 438 * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. 439 * Also set the PSTATE to a known state. 440 */ 441 bl prepare_el3_entry 442 443#if ENABLE_PAUTH 444 /* Load and program APIAKey firmware key */ 445 bl pauth_load_bl31_apiakey 446#endif 447 448 /* 449 * Populate the parameters for the SMC handler. 450 * We already have x0-x4 in place. x5 will point to a cookie (not used 451 * now). x6 will point to the context structure (SP_EL3) and x7 will 452 * contain flags we need to pass to the handler. 453 */ 454 mov x5, xzr 455 mov x6, sp 456 457 /* 458 * Restore the saved C runtime stack value which will become the new 459 * SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context' 460 * structure prior to the last ERET from EL3. 461 */ 462 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 463 464 /* Switch to SP_EL0 */ 465 msr spsel, #MODE_SP_EL0 466 467 /* 468 * Save the SPSR_EL3 and ELR_EL3 in case there is a world 469 * switch during SMC handling. 470 * TODO: Revisit if all system registers can be saved later. 471 */ 472 mrs x16, spsr_el3 473 mrs x17, elr_el3 474 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 475 476 /* Load SCR_EL3 */ 477 mrs x18, scr_el3 478 479 /* check for system register traps */ 480 mrs x16, esr_el3 481 ubfx x17, x16, #ESR_EC_SHIFT, #ESR_EC_LENGTH 482 cmp x17, #EC_AARCH64_SYS 483 b.eq sysreg_handler64 484 485 /* Clear flag register */ 486 mov x7, xzr 487 488#if ENABLE_RME 489 /* Copy SCR_EL3.NSE bit to the flag to indicate caller's security */ 490 ubfx x7, x18, #SCR_NSE_SHIFT, 1 491 492 /* 493 * Shift copied SCR_EL3.NSE bit by 5 to create space for 494 * SCR_EL3.NS bit. Bit 5 of the flag corresponds to 495 * the SCR_EL3.NSE bit. 496 */ 497 lsl x7, x7, #5 498#endif /* ENABLE_RME */ 499 500 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ 501 bfi x7, x18, #0, #1 502 503 /* 504 * Per SMCCCv1.3 a caller can set the SVE hint bit in the SMC FID 505 * passed through x0. Copy the SVE hint bit to flags and mask the 506 * bit in smc_fid passed to the standard service dispatcher. 507 * A service/dispatcher can retrieve the SVE hint bit state from 508 * flags using the appropriate helper. 509 */ 510 bfi x7, x0, #FUNCID_SVE_HINT_SHIFT, #FUNCID_SVE_HINT_MASK 511 bic x0, x0, #(FUNCID_SVE_HINT_MASK << FUNCID_SVE_HINT_SHIFT) 512 513 mov sp, x12 514 515 /* Get the unique owning entity number */ 516 ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH 517 ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH 518 orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH 519 520 /* Load descriptor index from array of indices */ 521 adrp x14, rt_svc_descs_indices 522 add x14, x14, :lo12:rt_svc_descs_indices 523 ldrb w15, [x14, x16] 524 525 /* Any index greater than 127 is invalid. Check bit 7. */ 526 tbnz w15, 7, smc_unknown 527 528 /* 529 * Get the descriptor using the index 530 * x11 = (base + off), w15 = index 531 * 532 * handler = (base + off) + (index << log2(size)) 533 */ 534 adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE) 535 lsl w10, w15, #RT_SVC_SIZE_LOG2 536 ldr x15, [x11, w10, uxtw] 537 538 /* 539 * Call the Secure Monitor Call handler and then drop directly into 540 * el3_exit() which will program any remaining architectural state 541 * prior to issuing the ERET to the desired lower EL. 542 */ 543#if DEBUG 544 cbz x15, rt_svc_fw_critical_error 545#endif 546 blr x15 547 548 b el3_exit 549 550sysreg_handler64: 551 mov x0, x16 /* ESR_EL3, containing syndrome information */ 552 mov x1, x6 /* lower EL's context */ 553 mov x19, x6 /* save context pointer for after the call */ 554 mov sp, x12 /* EL3 runtime stack, as loaded above */ 555 556 /* int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx); */ 557 bl handle_sysreg_trap 558 /* 559 * returns: 560 * -1: unhandled trap, panic 561 * 0: handled trap, return to the trapping instruction (repeating it) 562 * 1: handled trap, return to the next instruction 563 */ 564 565 tst w0, w0 566 b.mi do_panic /* negative return value: panic */ 567 b.eq 1f /* zero: do not change ELR_EL3 */ 568 569 /* advance the PC to continue after the instruction */ 570 ldr x1, [x19, #CTX_EL3STATE_OFFSET + CTX_ELR_EL3] 571 add x1, x1, #4 572 str x1, [x19, #CTX_EL3STATE_OFFSET + CTX_ELR_EL3] 5731: 574 b el3_exit 575 576smc_unknown: 577 /* 578 * Unknown SMC call. Populate return value with SMC_UNK and call 579 * el3_exit() which will restore the remaining architectural state 580 * i.e., SYS, GP and PAuth registers(if any) prior to issuing the ERET 581 * to the desired lower EL. 582 */ 583 mov x0, #SMC_UNK 584 str x0, [x6, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 585 b el3_exit 586 587smc_prohibited: 588 restore_ptw_el1_sys_regs 589 ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] 590 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 591 mov x0, #SMC_UNK 592 exception_return 593 594#if DEBUG 595rt_svc_fw_critical_error: 596 /* Switch to SP_ELx */ 597 msr spsel, #MODE_SP_ELX 598 no_ret report_unhandled_exception 599#endif 600endfunc sync_exception_handler 601 602 /* --------------------------------------------------------------------- 603 * The following code handles exceptions caused by BRK instructions. 604 * Following a BRK instruction, the only real valid cause of action is 605 * to print some information and panic, as the code that caused it is 606 * likely in an inconsistent internal state. 607 * 608 * This is initially intended to be used in conjunction with 609 * __builtin_trap. 610 * --------------------------------------------------------------------- 611 */ 612#ifdef MONITOR_TRAPS 613func brk_handler 614 /* Extract the ISS */ 615 mrs x10, esr_el3 616 ubfx x10, x10, #ESR_ISS_SHIFT, #ESR_ISS_LENGTH 617 618 /* Ensure the console is initialized */ 619 bl plat_crash_console_init 620 621 adr x4, brk_location 622 bl asm_print_str 623 mrs x4, elr_el3 624 bl asm_print_hex 625 bl asm_print_newline 626 627 adr x4, brk_message 628 bl asm_print_str 629 mov x4, x10 630 mov x5, #28 631 bl asm_print_hex_bits 632 bl asm_print_newline 633 634 no_ret plat_panic_handler 635endfunc brk_handler 636#endif /* MONITOR_TRAPS */ 637