1/* 2 * Copyright (c) 2021-2026, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v2.h> 11#include "wa_cve_2022_23960_bhb_vector.S" 12 13#include <cpu_macros.S> 14#include <wa_cve_2025_0647_cpprctx.h> 15 16#include <plat_macros.S> 17 18/* Hardware handled coherency */ 19#if HW_ASSISTED_COHERENCY == 0 20#error "Neoverse V2 must be compiled with HW_ASSISTED_COHERENCY enabled" 21#endif 22 23/* 64-bit only core */ 24#if CTX_INCLUDE_AARCH32_REGS == 1 25#error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 26#endif 27 28.global check_erratum_neoverse_v2_3701771 29 30cpu_reset_prologue neoverse_v2 31 32workaround_reset_start neoverse_v2, ERRATUM(2618597), ERRATA_V2_2618597 33 /* Disable retention control for WFI and WFE. */ 34 mrs x0, NEOVERSE_V2_CPUPWRCTLR_EL1 35 bfi x0, xzr, #NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_SHIFT, \ 36 #NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_WIDTH 37 bfi x0, xzr, #NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_SHIFT, \ 38 #NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_WIDTH 39 msr NEOVERSE_V2_CPUPWRCTLR_EL1, x0 40workaround_reset_end neoverse_v2, ERRATUM(2618597) 41 42/* Erratum entry and check function for SMCCC_ARCH_WORKAROUND_3 */ 43add_erratum_entry neoverse_v2, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960 44 45check_erratum_ls neoverse_v2, ERRATUM(ARCH_WORKAROUND_3), CPU_REV(0, 0) 46 47check_erratum_ls neoverse_v2, ERRATUM(2618597), CPU_REV(0, 1) 48 49workaround_reset_start neoverse_v2, ERRATUM(2662553), ERRATA_V2_2662553 50 sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_STATIC_FULL, \ 51 NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_LSB, NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_WIDTH 52workaround_reset_end neoverse_v2, ERRATUM(2662553) 53 54check_erratum_ls neoverse_v2, ERRATUM(2662553), CPU_REV(0, 1) 55 56workaround_reset_start neoverse_v2, ERRATUM(2719105), ERRATA_V2_2719105 57 sysreg_bit_set NEOVERSE_V2_CPUACTLR2_EL1, NEOVERSE_V2_CPUACTLR2_EL1_BIT_0 58workaround_reset_end neoverse_v2, ERRATUM(2719105) 59 60check_erratum_ls neoverse_v2, ERRATUM(2719105), CPU_REV(0, 1) 61 62workaround_reset_start neoverse_v2, ERRATUM(2743011), ERRATA_V2_2743011 63 sysreg_bit_set NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_55 64 sysreg_bit_clear NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_56 65workaround_reset_end neoverse_v2, ERRATUM(2743011) 66 67check_erratum_ls neoverse_v2, ERRATUM(2743011), CPU_REV(0, 1) 68 69workaround_reset_start neoverse_v2, ERRATUM(2779510), ERRATA_V2_2779510 70 sysreg_bit_set NEOVERSE_V2_CPUACTLR3_EL1, NEOVERSE_V2_CPUACTLR3_EL1_BIT_47 71workaround_reset_end neoverse_v2, ERRATUM(2779510) 72 73check_erratum_ls neoverse_v2, ERRATUM(2779510), CPU_REV(0, 1) 74 75workaround_runtime_start neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 76 /* dsb before isb of power down sequence */ 77 dsb sy 78workaround_runtime_end neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 79 80check_erratum_ls neoverse_v2, ERRATUM(2801372), CPU_REV(0, 1) 81 82workaround_reset_start neoverse_v2, ERRATUM(3442699), ERRATA_V2_3442699 83 sysreg_bit_set NEOVERSE_V2_CPUACTLR_EL1, NEOVERSE_V2_CPUACTLR_EL1_BIT_36 84workaround_reset_end neoverse_v2, ERRATUM(3442699) 85 86check_erratum_ls neoverse_v2, ERRATUM(3442699), CPU_REV(0, 2) 87 88add_erratum_entry neoverse_v2, ERRATUM(3701771), ERRATA_V2_3701771 89 90check_erratum_ls neoverse_v2, ERRATUM(3701771), CPU_REV(0, 2) 91 92workaround_reset_start neoverse_v2, ERRATUM(3841324), ERRATA_V2_3841324 93 sysreg_bit_set NEOVERSE_V2_CPUACTLR_EL1, BIT(1) 94workaround_reset_end neoverse_v2, ERRATUM(3841324) 95 96check_erratum_ls neoverse_v2, ERRATUM(3841324), CPU_REV(0, 1) 97 98workaround_reset_start neoverse_v2, ERRATUM(3888126), ERRATA_V2_3888126 99 sysreg_bit_set NEOVERSE_V2_CPUACTLR2_EL1, BIT(22) 100workaround_reset_end neoverse_v2, ERRATUM(3888126) 101 102check_erratum_ls neoverse_v2, ERRATUM(3888126), CPU_REV(0, 2) 103 104workaround_reset_start neoverse_v2, ERRATUM(4302968), ERRATA_V2_4302968 105 sysreg_bit_set NEOVERSE_V2_CPUACTLR5_EL1, BIT(50) 106workaround_reset_end neoverse_v2, ERRATUM(4302968) 107 108check_erratum_ls neoverse_v2, ERRATUM(4302968), CPU_REV(0, 2) 109 110workaround_reset_start neoverse_v2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 111#if IMAGE_BL31 112 /* 113 * The Neoverse-V2 generic vectors are overridden to apply errata 114 * mitigation on exception entry from lower ELs. 115 */ 116 override_vector_table wa_cve_vbar_neoverse_v2 117#endif /* IMAGE_BL31 */ 118workaround_reset_end neoverse_v2, CVE(2022,23960) 119 120check_erratum_ls neoverse_v2, CVE(2022, 23960), CPU_REV(0, 0) 121 122/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 123workaround_reset_start neoverse_v2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 124 sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, BIT(46) 125workaround_reset_end neoverse_v2, CVE(2024, 5660) 126 127check_erratum_ls neoverse_v2, CVE(2024, 5660), CPU_REV(0, 2) 128 129#if WORKAROUND_CVE_2022_23960 130 wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2 131#endif /* WORKAROUND_CVE_2022_23960 */ 132 133 /* ---------------------------------------------------------------- 134 * CVE-2024-7881 is mitigated for Neoverse-V2 using erratum 3696445 135 * workaround by disabling the affected prefetcher setting 136 * CPUACTLR6_EL1[41]. 137 * ---------------------------------------------------------------- 138 */ 139workaround_reset_start neoverse_v2, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 140 sysreg_bit_set NEOVERSE_V2_CPUACTLR6_EL1, BIT(41) 141workaround_reset_end neoverse_v2, CVE(2024, 7881) 142 143check_erratum_ls neoverse_v2, CVE(2024, 7881), CPU_REV(0, 2) 144 145 /* 146 * Instruction patch sequence to trap 'cpp rctx' instructions to EL3. 147 * Enables mitigation for CVE-2025-0647. 148 */ 149workaround_reset_start neoverse_v2, CVE(2025, 647), WORKAROUND_CVE_2025_0647 150 mov x0, #WA_PATCH_SLOT(3) 151 bl wa_cve_2025_0647_instruction_patch 152workaround_reset_end neoverse_v2, CVE(2025, 647) 153 154check_erratum_chosen neoverse_v2, CVE(2025, 647), WORKAROUND_CVE_2025_0647 155 156#if WORKAROUND_CVE_2025_0647 157func neoverse_v2_impl_defined_el3_handler 158 mov x0, #WA_LS_RCG_EN 159 160 /* See if this call came from trap handler. */ 161 cmp x1, #EC_IMP_DEF_EL3 162 bne wa_cve_2025_0647_do_cpp_wa 163 orr x0, x0, #WA_IS_TRAP_HANDLER 164 b wa_cve_2025_0647_do_cpp_wa 165endfunc neoverse_v2_impl_defined_el3_handler 166#endif 167 168 /* ---------------------------------------------------- 169 * HW will do the cache maintenance while powering down 170 * ---------------------------------------------------- 171 */ 172func neoverse_v2_core_pwr_dwn 173 /* --------------------------------------------------- 174 * Enable CPU power down bit in power control register 175 * --------------------------------------------------- 176 */ 177 sysreg_bit_set NEOVERSE_V2_CPUPWRCTLR_EL1, NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 178 apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 179 180 isb 181 ret 182endfunc neoverse_v2_core_pwr_dwn 183 184cpu_reset_func_start neoverse_v2 185 /* Disable speculative loads */ 186 msr SSBS, xzr 187 188#if NEOVERSE_Vx_EXTERNAL_LLC 189 /* Some systems may have External LLC, core needs to be made aware */ 190 sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, NEOVERSE_V2_CPUECTLR_EL1_EXTLLC_BIT 191#endif 192cpu_reset_func_end neoverse_v2 193 194 /* --------------------------------------------- 195 * This function provides Neoverse V2- 196 * specific register information for crash 197 * reporting. It needs to return with x6 198 * pointing to a list of register names in ascii 199 * and x8 - x15 having values of registers to be 200 * reported. 201 * --------------------------------------------- 202 */ 203.section .rodata.neoverse_v2_regs, "aS" 204neoverse_v2_regs: /* The ascii list of register names to be reported */ 205 .asciz "cpuectlr_el1", "" 206 207func neoverse_v2_cpu_reg_dump 208 adr x6, neoverse_v2_regs 209 mrs x8, NEOVERSE_V2_CPUECTLR_EL1 210 ret 211endfunc neoverse_v2_cpu_reg_dump 212 213#if WORKAROUND_CVE_2025_0647 214declare_cpu_ops_eh neoverse_v2, NEOVERSE_V2_MIDR, \ 215 neoverse_v2_reset_func, \ 216 neoverse_v2_impl_defined_el3_handler, \ 217 neoverse_v2_core_pwr_dwn 218#else 219declare_cpu_ops neoverse_v2, NEOVERSE_V2_MIDR, \ 220 neoverse_v2_reset_func, \ 221 neoverse_v2_core_pwr_dwn 222#endif 223 224