1/* 2 * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a77.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-A77 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-A77 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_A77_BHB_LOOP_COUNT, cortex_a77 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29 /* -------------------------------------------------- 30 * Errata Workaround for Cortex A77 Errata #1508412. 31 * This applies only to revision <= r1p0 of Cortex A77. 32 * Inputs: 33 * x0: variant[4:7] and revision[0:3] of current cpu. 34 * Shall clobber: x0-x17 35 * -------------------------------------------------- 36 */ 37func errata_a77_1508412_wa 38 /* 39 * Compare x0 against revision r1p0 40 */ 41 mov x17, x30 42 bl check_errata_1508412 43 cbz x0, 3f 44 /* 45 * Compare x0 against revision r0p0 46 */ 47 bl check_errata_1508412_0 48 cbz x0, 1f 49 ldr x0, =0x0 50 msr CORTEX_A77_CPUPSELR_EL3, x0 51 ldr x0, =0x00E8400000 52 msr CORTEX_A77_CPUPOR_EL3, x0 53 ldr x0, =0x00FFE00000 54 msr CORTEX_A77_CPUPMR_EL3, x0 55 ldr x0, =0x4004003FF 56 msr CORTEX_A77_CPUPCR_EL3, x0 57 ldr x0, =0x1 58 msr CORTEX_A77_CPUPSELR_EL3, x0 59 ldr x0, =0x00E8C00040 60 msr CORTEX_A77_CPUPOR_EL3, x0 61 ldr x0, =0x00FFE00040 62 msr CORTEX_A77_CPUPMR_EL3, x0 63 b 2f 641: 65 ldr x0, =0x0 66 msr CORTEX_A77_CPUPSELR_EL3, x0 67 ldr x0, =0x00E8400000 68 msr CORTEX_A77_CPUPOR_EL3, x0 69 ldr x0, =0x00FF600000 70 msr CORTEX_A77_CPUPMR_EL3, x0 71 ldr x0, =0x00E8E00080 72 msr CORTEX_A77_CPUPOR2_EL3, x0 73 ldr x0, =0x00FFE000C0 74 msr CORTEX_A77_CPUPMR2_EL3, x0 752: 76 ldr x0, =0x04004003FF 77 msr CORTEX_A77_CPUPCR_EL3, x0 78 isb 793: 80 ret x17 81endfunc errata_a77_1508412_wa 82 83func check_errata_1508412 84 mov x1, #0x10 85 b cpu_rev_var_ls 86endfunc check_errata_1508412 87 88func check_errata_1508412_0 89 mov x1, #0x0 90 b cpu_rev_var_ls 91endfunc check_errata_1508412_0 92 93 /* -------------------------------------------------- 94 * Errata Workaround for Cortex A77 Errata #1925769. 95 * This applies to revision <= r1p1 of Cortex A77. 96 * Inputs: 97 * x0: variant[4:7] and revision[0:3] of current cpu. 98 * Shall clobber: x0-x17 99 * -------------------------------------------------- 100 */ 101func errata_a77_1925769_wa 102 /* Compare x0 against revision <= r1p1 */ 103 mov x17, x30 104 bl check_errata_1925769 105 cbz x0, 1f 106 107 /* Set bit 8 in ECTLR_EL1 */ 108 mrs x1, CORTEX_A77_CPUECTLR_EL1 109 orr x1, x1, #CORTEX_A77_CPUECTLR_EL1_BIT_8 110 msr CORTEX_A77_CPUECTLR_EL1, x1 111 isb 1121: 113 ret x17 114endfunc errata_a77_1925769_wa 115 116func check_errata_1925769 117 /* Applies to everything <= r1p1 */ 118 mov x1, #0x11 119 b cpu_rev_var_ls 120endfunc check_errata_1925769 121 122 /* -------------------------------------------------- 123 * Errata Workaround for Cortex A77 Errata #1946167. 124 * This applies to revision <= r1p1 of Cortex A77. 125 * Inputs: 126 * x0: variant[4:7] and revision[0:3] of current cpu. 127 * Shall clobber: x0-x17 128 * -------------------------------------------------- 129 */ 130func errata_a77_1946167_wa 131 /* Compare x0 against revision <= r1p1 */ 132 mov x17, x30 133 bl check_errata_1946167 134 cbz x0, 1f 135 136 ldr x0,=0x4 137 msr CORTEX_A77_CPUPSELR_EL3,x0 138 ldr x0,=0x10E3900002 139 msr CORTEX_A77_CPUPOR_EL3,x0 140 ldr x0,=0x10FFF00083 141 msr CORTEX_A77_CPUPMR_EL3,x0 142 ldr x0,=0x2001003FF 143 msr CORTEX_A77_CPUPCR_EL3,x0 144 145 ldr x0,=0x5 146 msr CORTEX_A77_CPUPSELR_EL3,x0 147 ldr x0,=0x10E3800082 148 msr CORTEX_A77_CPUPOR_EL3,x0 149 ldr x0,=0x10FFF00083 150 msr CORTEX_A77_CPUPMR_EL3,x0 151 ldr x0,=0x2001003FF 152 msr CORTEX_A77_CPUPCR_EL3,x0 153 154 ldr x0,=0x6 155 msr CORTEX_A77_CPUPSELR_EL3,x0 156 ldr x0,=0x10E3800200 157 msr CORTEX_A77_CPUPOR_EL3,x0 158 ldr x0,=0x10FFF003E0 159 msr CORTEX_A77_CPUPMR_EL3,x0 160 ldr x0,=0x2001003FF 161 msr CORTEX_A77_CPUPCR_EL3,x0 162 163 isb 1641: 165 ret x17 166endfunc errata_a77_1946167_wa 167 168func check_errata_1946167 169 /* Applies to everything <= r1p1 */ 170 mov x1, #0x11 171 b cpu_rev_var_ls 172endfunc check_errata_1946167 173 174 /* -------------------------------------------------- 175 * Errata Workaround for Cortex A77 Errata #1791578. 176 * This applies to revisions r0p0, r1p0, and r1p1 and is still open. 177 * x0: variant[4:7] and revision[0:3] of current cpu. 178 * Shall clobber: x0-x17 179 * -------------------------------------------------- 180 */ 181func errata_a77_1791578_wa 182 /* Check workaround compatibility. */ 183 mov x17, x30 184 bl check_errata_1791578 185 cbz x0, 1f 186 187 /* Set bit 2 in ACTLR2_EL1 */ 188 mrs x1, CORTEX_A77_ACTLR2_EL1 189 orr x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_2 190 msr CORTEX_A77_ACTLR2_EL1, x1 191 isb 1921: 193 ret x17 194endfunc errata_a77_1791578_wa 195 196func check_errata_1791578 197 /* Applies to r0p0, r1p0, and r1p1 right now */ 198 mov x1, #0x11 199 b cpu_rev_var_ls 200endfunc check_errata_1791578 201 202 /* -------------------------------------------------- 203 * Errata Workaround for Cortex A77 Errata #2356587. 204 * This applies to revisions r0p0, r1p0, and r1p1 and is still open. 205 * x0: variant[4:7] and revision[0:3] of current cpu. 206 * Shall clobber: x0-x17 207 * -------------------------------------------------- 208 */ 209func errata_a77_2356587_wa 210 /* Check workaround compatibility. */ 211 mov x17, x30 212 bl check_errata_2356587 213 cbz x0, 1f 214 215 /* Set bit 0 in ACTLR2_EL1 */ 216 mrs x1, CORTEX_A77_ACTLR2_EL1 217 orr x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_0 218 msr CORTEX_A77_ACTLR2_EL1, x1 219 isb 2201: 221 ret x17 222endfunc errata_a77_2356587_wa 223 224func check_errata_2356587 225 /* Applies to r0p0, r1p0, and r1p1 right now */ 226 mov x1, #0x11 227 b cpu_rev_var_ls 228endfunc check_errata_2356587 229 230 /* ----------------------------------------------------------------- 231 * Errata Workaround for Cortex A77 Errata #2743100 232 * This applies to revisions r0p0, r1p0, and r1p1 and is still open. 233 * x0: variant[4:7] and revision[0:3] of current cpu. 234 * Shall clobber: x0-x17 235 * ----------------------------------------------------------------- 236 */ 237func errata_a77_2743100_wa 238 mov x17, x30 239 bl check_errata_2743100 240 cbz x0, 1f 241 242 /* dsb before isb of power down sequence */ 243 dsb sy 2441: 245 ret x17 246endfunc errata_a77_2743100_wa 247 248func check_errata_2743100 249 /* Applies to r0p0, r1p0, and r1p1 right now */ 250 mov x1, #0x11 251 b cpu_rev_var_ls 252endfunc check_errata_2743100 253 254func check_errata_cve_2022_23960 255#if WORKAROUND_CVE_2022_23960 256 mov x0, #ERRATA_APPLIES 257#else 258 mov x0, #ERRATA_MISSING 259#endif 260 ret 261endfunc check_errata_cve_2022_23960 262 263 /* -------------------------------------------------- 264 * Errata Workaround for Cortex A77 Errata #1800714. 265 * This applies to revision <= r1p1 of Cortex A77. 266 * Inputs: 267 * x0: variant[4:7] and revision[0:3] of current cpu. 268 * Shall clobber: x0-x17 269 * -------------------------------------------------- 270 */ 271func errata_a77_1800714_wa 272 /* Compare x0 against revision <= r1p1 */ 273 mov x17, x30 274 bl check_errata_1800714 275 cbz x0, 1f 276 277 /* Disable allocation of splintered pages in the L2 TLB */ 278 mrs x1, CORTEX_A77_CPUECTLR_EL1 279 orr x1, x1, CORTEX_A77_CPUECTLR_EL1_BIT_53 280 msr CORTEX_A77_CPUECTLR_EL1, x1 281 isb 2821: 283 ret x17 284endfunc errata_a77_1800714_wa 285 286func check_errata_1800714 287 /* Applies to everything <= r1p1 */ 288 mov x1, #0x11 289 b cpu_rev_var_ls 290endfunc check_errata_1800714 291 292 /* ------------------------------------------------- 293 * The CPU Ops reset function for Cortex-A77. 294 * Shall clobber: x0-x19 295 * ------------------------------------------------- 296 */ 297func cortex_a77_reset_func 298 mov x19, x30 299 bl cpu_get_rev_var 300 mov x18, x0 301 302#if ERRATA_A77_1508412 303 mov x0, x18 304 bl errata_a77_1508412_wa 305#endif 306 307#if ERRATA_A77_1925769 308 mov x0, x18 309 bl errata_a77_1925769_wa 310#endif 311 312#if ERRATA_A77_1946167 313 mov x0, x18 314 bl errata_a77_1946167_wa 315#endif 316 317#if ERRATA_A77_1791578 318 mov x0, x18 319 bl errata_a77_1791578_wa 320#endif 321 322#if ERRATA_A77_2356587 323 mov x0, x18 324 bl errata_a77_2356587_wa 325#endif 326 327#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 328 /* 329 * The Cortex-A77 generic vectors are overridden to apply errata 330 * mitigation on exception entry from lower ELs. 331 */ 332 adr x0, wa_cve_vbar_cortex_a77 333 msr vbar_el3, x0 334#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ 335 336#if ERRATA_A77_1800714 337 mov x0, x18 338 bl errata_a77_1800714_wa 339#endif 340 341 isb 342 ret x19 343endfunc cortex_a77_reset_func 344 345 /* --------------------------------------------- 346 * HW will do the cache maintenance while powering down 347 * --------------------------------------------- 348 */ 349func cortex_a77_core_pwr_dwn 350 /* --------------------------------------------- 351 * Enable CPU power down bit in power control register 352 * --------------------------------------------- 353 */ 354 mrs x0, CORTEX_A77_CPUPWRCTLR_EL1 355 orr x0, x0, #CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 356 msr CORTEX_A77_CPUPWRCTLR_EL1, x0 357#if ERRATA_A77_2743100 358 mov x15, x30 359 bl cpu_get_rev_var 360 bl errata_a77_2743100_wa 361 mov x30, x15 362#endif /* ERRATA_A77_2743100 */ 363 isb 364 ret 365endfunc cortex_a77_core_pwr_dwn 366 367#if REPORT_ERRATA 368/* 369 * Errata printing function for Cortex-A77. Must follow AAPCS. 370 */ 371func cortex_a77_errata_report 372 stp x8, x30, [sp, #-16]! 373 374 bl cpu_get_rev_var 375 mov x8, x0 376 377 /* 378 * Report all errata. The revision-variant information is passed to 379 * checking functions of each errata. 380 */ 381 report_errata ERRATA_A77_1508412, cortex_a77, 1508412 382 report_errata ERRATA_A77_1791578, cortex_a77, 1791578 383 report_errata ERRATA_A77_1800714, cortex_a77, 1800714 384 report_errata ERRATA_A77_1925769, cortex_a77, 1925769 385 report_errata ERRATA_A77_1946167, cortex_a77, 1946167 386 report_errata ERRATA_A77_2356587, cortex_a77, 2356587 387 report_errata ERRATA_A77_2743100, cortex_a77, 2743100 388 report_errata WORKAROUND_CVE_2022_23960, cortex_a77, cve_2022_23960 389 390 ldp x8, x30, [sp], #16 391 ret 392endfunc cortex_a77_errata_report 393#endif 394 395 396 /* --------------------------------------------- 397 * This function provides Cortex-A77 specific 398 * register information for crash reporting. 399 * It needs to return with x6 pointing to 400 * a list of register names in ascii and 401 * x8 - x15 having values of registers to be 402 * reported. 403 * --------------------------------------------- 404 */ 405.section .rodata.cortex_a77_regs, "aS" 406cortex_a77_regs: /* The ascii list of register names to be reported */ 407 .asciz "cpuectlr_el1", "" 408 409func cortex_a77_cpu_reg_dump 410 adr x6, cortex_a77_regs 411 mrs x8, CORTEX_A77_CPUECTLR_EL1 412 ret 413endfunc cortex_a77_cpu_reg_dump 414 415declare_cpu_ops cortex_a77, CORTEX_A77_MIDR, \ 416 cortex_a77_reset_func, \ 417 cortex_a77_core_pwr_dwn 418