fix(intel): update the AES GCM/GCM_GHASH modes return data size

On the Agilex5 platform, in FCS AES method if block mode is
GCM/GCM_GHASH mode then the data size written to the destination
buffer is

fix(intel): update the AES GCM/GCM_GHASH modes return data size

On the Agilex5 platform, in FCS AES method if block mode is
GCM/GCM_GHASH mode then the data size written to the destination
buffer is at index[7] instead of [3] as in other cases.

Change-Id: Ide664f594ea63aaee7f74d21e8e2986de48e94a2
Signed-off-by: Girisha Dengi <girisha.dengi@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): add missing cache flush operation for hmac

Add missing cache flush operation for HMAC verify
operation.Also update the code to query the correct
buffer for the final result of HMAC veri

fix(intel): add missing cache flush operation for hmac

Add missing cache flush operation for HMAC verify
operation.Also update the code to query the correct
buffer for the final result of HMAC verify operation.

Change-Id: I85208765313b9048cfef13727d280dca8af6d548
Signed-off-by: Mahesh Rao <mahesh.rao@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): flush the mailbox response buffer in SiPSVC V3

In SiPSVC V3, the user suppiled buffer will be directly used
for collecting the response from SDM mailbox - this way we
can avoid keeping t

fix(intel): flush the mailbox response buffer in SiPSVC V3

In SiPSVC V3, the user suppiled buffer will be directly used
for collecting the response from SDM mailbox - this way we
can avoid keeping the response local copy in the TF-A and
improve performance. Once the response is collected in the
user buffer, we need to FLUSH to maintain coherency.

Change-Id: I265ce177fe42d7ab647c875d52286de4b998672d
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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feat(intel): move common functions to common lib files

This patch is used to move common functions that used across
files into commmon lib files to prevent multiple functions
declaration and share a

feat(intel): move common functions to common lib files

This patch is used to move common functions that used across
files into commmon lib files to prevent multiple functions
declaration and share among files.

Change-Id: I19d9727eac895e7bf597a66076a7b68755cbe0ef
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): support SMC 64bit return args in SiPSVC V3

Update SiPSVC V3 framework to support 64bit SMC return
arguments and other miscellaneous debug prints.

Change-Id: I659a0aea8e24eb5876e69327e44

fix(intel): support SMC 64bit return args in SiPSVC V3

Update SiPSVC V3 framework to support 64bit SMC return
arguments and other miscellaneous debug prints.

Change-Id: I659a0aea8e24eb5876e69327e44a667d2a54c241
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): verify data size in AES GCM and GCM-GHASH modes

On the Agilex5 platform, in the FCS AES GCM and GCM-GHASH
modes enc/dec data size should be 0 or multiple of 16bytes.

Change-Id: I23e51bf

fix(intel): verify data size in AES GCM and GCM-GHASH modes

On the Agilex5 platform, in the FCS AES GCM and GCM-GHASH
modes enc/dec data size should be 0 or multiple of 16bytes.

Change-Id: I23e51bf942771e74d16f8a87fbfdbf36ef3c3893
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): update FCS AES method for GCM block modes

On the Agilex5 platform, AES enc/dec with GCM and GCM-GHASH
modes, the source and destination size should be in multiples
of 16 bytes. For other

fix(intel): update FCS AES method for GCM block modes

On the Agilex5 platform, AES enc/dec with GCM and GCM-GHASH
modes, the source and destination size should be in multiples
of 16 bytes. For other platforms and other modes, it should
be in multiples of 32 bytes.

Change-Id: I0fa9adafb5d7fc4c794a4acb9339cf8259df0c78
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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feat(intel): support FCS commands with SiPSVC V3 framework

Support all the FCS(FPGA Crypto Service) commands with
SiPSVC verson3 framework.

Change-Id: I1dfb95aaddf7111325ce0082eb26f7a201001141
Sign

feat(intel): support FCS commands with SiPSVC V3 framework

Support all the FCS(FPGA Crypto Service) commands with
SiPSVC verson3 framework.

Change-Id: I1dfb95aaddf7111325ce0082eb26f7a201001141
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@altera.com>

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fix(intel): update memcpy to memcpy_s

memcpy does not check the dst_size which may
create vulnerable issue as it can overflow the buffer.
Using memcpy_s which check the dst_size will help to
reduce

fix(intel): update memcpy to memcpy_s

memcpy does not check the dst_size which may
create vulnerable issue as it can overflow the buffer.
Using memcpy_s which check the dst_size will help to
reduce the risk. Also, this memcpy is always 4 bytes
each time.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I413e6ae2ee9330501703c4cd63b7943c6f55b4c7

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Merge "fix(intel): update fcs crypto init code to check for mode" into integration