1/* 2 * Copyright (c) 2021-2022, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x2.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex X2 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex X2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_X2_BHB_LOOP_COUNT, cortex_x2 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29 /* -------------------------------------------------- 30 * Errata Workaround for Cortex X2 Errata #2002765. 31 * This applies to revisions r0p0, r1p0, and r2p0 and 32 * is open. 33 * x0: variant[4:7] and revision[0:3] of current cpu. 34 * Shall clobber: x0, x1, x17 35 * -------------------------------------------------- 36 */ 37func errata_cortex_x2_2002765_wa 38 /* Check workaround compatibility. */ 39 mov x17, x30 40 bl check_errata_2002765 41 cbz x0, 1f 42 43 ldr x0, =0x6 44 msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */ 45 ldr x0, =0xF3A08002 46 msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */ 47 ldr x0, =0xFFF0F7FE 48 msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */ 49 ldr x0, =0x40000001003ff 50 msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */ 51 isb 52 531: 54 ret x17 55endfunc errata_cortex_x2_2002765_wa 56 57func check_errata_2002765 58 /* Applies to r0p0 - r2p0 */ 59 mov x1, #0x20 60 b cpu_rev_var_ls 61endfunc check_errata_2002765 62 63 /* -------------------------------------------------- 64 * Errata Workaround for Cortex X2 Errata #2058056. 65 * This applies to revisions r0p0, r1p0, and r2p0 and 66 * is open. 67 * x0: variant[4:7] and revision[0:3] of current cpu. 68 * Shall clobber: x0, x1, x17 69 * -------------------------------------------------- 70 */ 71func errata_cortex_x2_2058056_wa 72 /* Check workaround compatibility. */ 73 mov x17, x30 74 bl check_errata_2058056 75 cbz x0, 1f 76 77 mrs x1, CORTEX_X2_CPUECTLR2_EL1 78 mov x0, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV 79 bfi x1, x0, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH 80 msr CORTEX_X2_CPUECTLR2_EL1, x1 81 821: 83 ret x17 84endfunc errata_cortex_x2_2058056_wa 85 86func check_errata_2058056 87 /* Applies to r0p0 - r2p0 */ 88 mov x1, #0x20 89 b cpu_rev_var_ls 90endfunc check_errata_2058056 91 92 /* -------------------------------------------------- 93 * Errata Workaround for Cortex X2 Errata #2083908. 94 * This applies to revision r2p0 and is open. 95 * x0: variant[4:7] and revision[0:3] of current cpu. 96 * Shall clobber: x0-x2, x17 97 * -------------------------------------------------- 98 */ 99func errata_cortex_x2_2083908_wa 100 /* Check workaround compatibility. */ 101 mov x17, x30 102 bl check_errata_2083908 103 cbz x0, 1f 104 105 /* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */ 106 mrs x1, CORTEX_X2_CPUACTLR5_EL1 107 orr x1, x1, #BIT(13) 108 msr CORTEX_X2_CPUACTLR5_EL1, x1 109 1101: 111 ret x17 112endfunc errata_cortex_x2_2083908_wa 113 114func check_errata_2083908 115 /* Applies to r2p0 */ 116 mov x1, #0x20 117 mov x2, #0x20 118 b cpu_rev_var_range 119endfunc check_errata_2083908 120 121 /* -------------------------------------------------- 122 * Errata Workaround for Cortex-X2 Errata 2017096. 123 * This applies only to revisions r0p0, r1p0 and r2p0 124 * and is fixed in r2p1. 125 * Inputs: 126 * x0: variant[4:7] and revision[0:3] of current cpu. 127 * Shall clobber: x0, x1, x17 128 * -------------------------------------------------- 129 */ 130func errata_x2_2017096_wa 131 /* Compare x0 against revision r0p0 to r2p0 */ 132 mov x17, x30 133 bl check_errata_2017096 134 cbz x0, 1f 135 mrs x1, CORTEX_X2_CPUECTLR_EL1 136 orr x1, x1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT 137 msr CORTEX_X2_CPUECTLR_EL1, x1 138 1391: 140 ret x17 141endfunc errata_x2_2017096_wa 142 143func check_errata_2017096 144 /* Applies to r0p0, r1p0, r2p0 */ 145 mov x1, #0x20 146 b cpu_rev_var_ls 147endfunc check_errata_2017096 148 149 /* -------------------------------------------------- 150 * Errata Workaround for Cortex-X2 Errata 2081180. 151 * This applies to revision r0p0, r1p0 and r2p0 152 * and is fixed in r2p1. 153 * Inputs: 154 * x0: variant[4:7] and revision[0:3] of current cpu. 155 * Shall clobber: x0, x1, x17 156 * -------------------------------------------------- 157 */ 158func errata_x2_2081180_wa 159 /* Check revision. */ 160 mov x17, x30 161 bl check_errata_2081180 162 cbz x0, 1f 163 164 /* Apply instruction patching sequence */ 165 ldr x0, =0x3 166 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 167 ldr x0, =0xF3A08002 168 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 169 ldr x0, =0xFFF0F7FE 170 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 171 ldr x0, =0x10002001003FF 172 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 173 ldr x0, =0x4 174 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 175 ldr x0, =0xBF200000 176 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 177 ldr x0, =0xFFEF0000 178 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 179 ldr x0, =0x10002001003F3 180 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 181 isb 1821: 183 ret x17 184endfunc errata_x2_2081180_wa 185 186func check_errata_2081180 187 /* Applies to r0p0, r1p0 and r2p0 */ 188 mov x1, #0x20 189 b cpu_rev_var_ls 190endfunc check_errata_2081180 191 192 /* -------------------------------------------------- 193 * Errata Workaround for Cortex X2 Errata 2216384. 194 * This applies to revisions r0p0, r1p0, and r2p0 195 * and is fixed in r2p1. 196 * x0: variant[4:7] and revision[0:3] of current cpu. 197 * Shall clobber: x0, x1, x17 198 * -------------------------------------------------- 199 */ 200func errata_x2_2216384_wa 201 /* Check workaround compatibility. */ 202 mov x17, x30 203 bl check_errata_2216384 204 cbz x0, 1f 205 206 mrs x1, CORTEX_X2_CPUACTLR5_EL1 207 orr x1, x1, CORTEX_X2_CPUACTLR5_EL1_BIT_17 208 msr CORTEX_X2_CPUACTLR5_EL1, x1 209 210 /* Apply instruction patching sequence */ 211 ldr x0, =0x5 212 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 213 ldr x0, =0x10F600E000 214 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 215 ldr x0, =0x10FF80E000 216 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 217 ldr x0, =0x80000000003FF 218 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 219 isb 220 2211: 222 ret x17 223endfunc errata_x2_2216384_wa 224 225func check_errata_2216384 226 /* Applies to r0p0 - r2p0 */ 227 mov x1, #0x20 228 b cpu_rev_var_ls 229endfunc check_errata_2216384 230 231func check_errata_cve_2022_23960 232#if WORKAROUND_CVE_2022_23960 233 mov x0, #ERRATA_APPLIES 234#else 235 mov x0, #ERRATA_MISSING 236#endif 237 ret 238endfunc check_errata_cve_2022_23960 239 240 /* --------------------------------------------------------- 241 * Errata Workaround for Cortex-X2 Errata 2147715. 242 * This applies only to revisions r2p0 and is fixed in r2p1. 243 * Inputs: 244 * x0: variant[4:7] and revision[0:3] of current cpu. 245 * Shall clobber: x0, x1, x17 246 * --------------------------------------------------------- 247 */ 248func errata_x2_2147715_wa 249 /* Compare x0 against revision r2p0 */ 250 mov x17, x30 251 bl check_errata_2147715 252 cbz x0, 1f 253 254 /* Apply the workaround by setting bit 22 in CPUACTLR_EL1. */ 255 mrs x1, CORTEX_X2_CPUACTLR_EL1 256 orr x1, x1, CORTEX_X2_CPUACTLR_EL1_BIT_22 257 msr CORTEX_X2_CPUACTLR_EL1, x1 258 2591: 260 ret x17 261endfunc errata_x2_2147715_wa 262 263func check_errata_2147715 264 /* Applies to r2p0 */ 265 mov x1, #0x20 266 mov x2, #0x20 267 b cpu_rev_var_range 268endfunc check_errata_2147715 269 270 /* ---------------------------------------------------- 271 * HW will do the cache maintenance while powering down 272 * ---------------------------------------------------- 273 */ 274func cortex_x2_core_pwr_dwn 275 /* --------------------------------------------------- 276 * Enable CPU power down bit in power control register 277 * --------------------------------------------------- 278 */ 279 mrs x0, CORTEX_X2_CPUPWRCTLR_EL1 280 orr x0, x0, #CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 281 msr CORTEX_X2_CPUPWRCTLR_EL1, x0 282 isb 283 ret 284endfunc cortex_x2_core_pwr_dwn 285 286 /* 287 * Errata printing function for Cortex X2. Must follow AAPCS. 288 */ 289#if REPORT_ERRATA 290func cortex_x2_errata_report 291 stp x8, x30, [sp, #-16]! 292 293 bl cpu_get_rev_var 294 mov x8, x0 295 296 /* 297 * Report all errata. The revision-variant information is passed to 298 * checking functions of each errata. 299 */ 300 report_errata ERRATA_X2_2002765, cortex_x2, 2002765 301 report_errata ERRATA_X2_2017096, cortex_x2, 2017096 302 report_errata ERRATA_X2_2058056, cortex_x2, 2058056 303 report_errata ERRATA_X2_2081180, cortex_x2, 2081180 304 report_errata ERRATA_X2_2083908, cortex_x2, 2083908 305 report_errata ERRATA_X2_2147715, cortex_x2, 2147715 306 report_errata ERRATA_X2_2216384, cortex_x2, 2216384 307 report_errata WORKAROUND_CVE_2022_23960, cortex_x2, cve_2022_23960 308 report_errata ERRATA_DSU_2313941, cortex_x2, dsu_2313941 309 310 ldp x8, x30, [sp], #16 311 ret 312endfunc cortex_x2_errata_report 313#endif 314 315func cortex_x2_reset_func 316 mov x19, x30 317 318 /* Disable speculative loads */ 319 msr SSBS, xzr 320 321 /* Get the CPU revision and stash it in x18. */ 322 bl cpu_get_rev_var 323 mov x18, x0 324 325#if ERRATA_DSU_2313941 326 bl errata_dsu_2313941_wa 327#endif 328 329#if ERRATA_X2_2002765 330 mov x0, x18 331 bl errata_cortex_x2_2002765_wa 332#endif 333 334#if ERRATA_X2_2058056 335 mov x0, x18 336 bl errata_cortex_x2_2058056_wa 337#endif 338 339#if ERRATA_X2_2083908 340 mov x0, x18 341 bl errata_cortex_x2_2083908_wa 342#endif 343 344#if ERRATA_X2_2017096 345 mov x0, x18 346 bl errata_x2_2017096_wa 347#endif 348 349#if ERRATA_X2_2081180 350 mov x0, x18 351 bl errata_x2_2081180_wa 352#endif 353 354#if ERRATA_X2_2216384 355 mov x0, x18 356 bl errata_x2_2216384_wa 357#endif 358 359#if ERRATA_X2_2147715 360 mov x0, x18 361 bl errata_x2_2147715_wa 362#endif 363 364#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 365 /* 366 * The Cortex-X2 generic vectors are overridden to apply errata 367 * mitigation on exception entry from lower ELs. 368 */ 369 adr x0, wa_cve_vbar_cortex_x2 370 msr vbar_el3, x0 371#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ 372 373 isb 374 ret x19 375endfunc cortex_x2_reset_func 376 377 /* --------------------------------------------- 378 * This function provides Cortex X2 specific 379 * register information for crash reporting. 380 * It needs to return with x6 pointing to 381 * a list of register names in ascii and 382 * x8 - x15 having values of registers to be 383 * reported. 384 * --------------------------------------------- 385 */ 386.section .rodata.cortex_x2_regs, "aS" 387cortex_x2_regs: /* The ascii list of register names to be reported */ 388 .asciz "cpuectlr_el1", "" 389 390func cortex_x2_cpu_reg_dump 391 adr x6, cortex_x2_regs 392 mrs x8, CORTEX_X2_CPUECTLR_EL1 393 ret 394endfunc cortex_x2_cpu_reg_dump 395 396declare_cpu_ops cortex_x2, CORTEX_X2_MIDR, \ 397 cortex_x2_reset_func, \ 398 cortex_x2_core_pwr_dwn 399