1 /* 2 * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CONTEXT_EL2_H 8 #define CONTEXT_EL2_H 9 10 #ifndef __ASSEMBLER__ 11 /******************************************************************************* 12 * EL2 Registers: 13 * AArch64 EL2 system register context structure for preserving the 14 * architectural state during world switches. 15 ******************************************************************************/ 16 typedef struct el2_common_regs { 17 uint64_t actlr_el2; 18 uint64_t afsr0_el2; 19 uint64_t afsr1_el2; 20 uint64_t amair_el2; 21 uint64_t cnthctl_el2; 22 uint64_t cntvoff_el2; 23 uint64_t cptr_el2; 24 uint64_t dbgvcr32_el2; 25 uint64_t elr_el2; 26 uint64_t esr_el2; 27 uint64_t far_el2; 28 uint64_t hacr_el2; 29 uint64_t hcr_el2; 30 uint64_t hpfar_el2; 31 uint64_t hstr_el2; 32 uint64_t icc_sre_el2; 33 uint64_t ich_hcr_el2; 34 uint64_t ich_vmcr_el2; 35 uint64_t mair_el2; 36 uint64_t mdcr_el2; 37 uint64_t pmscr_el2; 38 uint64_t sctlr_el2; 39 uint64_t spsr_el2; 40 uint64_t sp_el2; 41 uint64_t tcr_el2; 42 uint64_t tpidr_el2; 43 uint64_t ttbr0_el2; 44 uint64_t vbar_el2; 45 uint64_t vmpidr_el2; 46 uint64_t vpidr_el2; 47 uint64_t vtcr_el2; 48 uint64_t vttbr_el2; 49 } el2_common_regs_t; 50 51 typedef struct el2_mte2_regs { 52 uint64_t tfsr_el2; 53 } el2_mte2_regs_t; 54 55 typedef struct el2_fgt_regs { 56 uint64_t hdfgrtr_el2; 57 uint64_t hafgrtr_el2; 58 uint64_t hdfgwtr_el2; 59 uint64_t hfgitr_el2; 60 uint64_t hfgrtr_el2; 61 uint64_t hfgwtr_el2; 62 } el2_fgt_regs_t; 63 64 typedef struct el2_fgt2_regs { 65 uint64_t hdfgrtr2_el2; 66 uint64_t hdfgwtr2_el2; 67 uint64_t hfgitr2_el2; 68 uint64_t hfgrtr2_el2; 69 uint64_t hfgwtr2_el2; 70 } el2_fgt2_regs_t; 71 72 typedef struct el2_ecv_regs { 73 uint64_t cntpoff_el2; 74 } el2_ecv_regs_t; 75 76 typedef struct el2_vhe_regs { 77 uint64_t contextidr_el2; 78 uint64_t ttbr1_el2; 79 } el2_vhe_regs_t; 80 81 typedef struct el2_ras_regs { 82 uint64_t vdisr_el2; 83 uint64_t vsesr_el2; 84 } el2_ras_regs_t; 85 86 typedef struct el2_neve_regs { 87 uint64_t vncr_el2; 88 } el2_neve_regs_t; 89 90 typedef struct el2_trf_regs { 91 uint64_t trfcr_el2; 92 } el2_trf_regs_t; 93 94 typedef struct el2_csv2_regs { 95 uint64_t scxtnum_el2; 96 } el2_csv2_regs_t; 97 98 typedef struct el2_hcx_regs { 99 uint64_t hcrx_el2; 100 } el2_hcx_regs_t; 101 102 typedef struct el2_tcr2_regs { 103 uint64_t tcr2_el2; 104 } el2_tcr2_regs_t; 105 106 typedef struct el2_sxpoe_regs { 107 uint64_t por_el2; 108 } el2_sxpoe_regs_t; 109 110 typedef struct el2_sxpie_regs { 111 uint64_t pire0_el2; 112 uint64_t pir_el2; 113 } el2_sxpie_regs_t; 114 115 typedef struct el2_s2pie_regs { 116 uint64_t s2pir_el2; 117 } el2_s2pie_regs_t; 118 119 typedef struct el2_gcs_regs { 120 uint64_t gcscr_el2; 121 uint64_t gcspr_el2; 122 } el2_gcs_regs_t; 123 124 typedef struct el2_mpam_regs { 125 uint64_t mpam2_el2; 126 uint64_t mpamhcr_el2; 127 uint64_t mpamvpm0_el2; 128 uint64_t mpamvpm1_el2; 129 uint64_t mpamvpm2_el2; 130 uint64_t mpamvpm3_el2; 131 uint64_t mpamvpm4_el2; 132 uint64_t mpamvpm5_el2; 133 uint64_t mpamvpm6_el2; 134 uint64_t mpamvpm7_el2; 135 uint64_t mpamvpmv_el2; 136 } el2_mpam_regs_t; 137 138 typedef struct el2_sysregs { 139 140 el2_common_regs_t common; 141 142 #if ENABLE_FEAT_MTE2 143 el2_mte2_regs_t mte2; 144 #endif 145 146 #if ENABLE_FEAT_FGT 147 el2_fgt_regs_t fgt; 148 #endif 149 150 #if ENABLE_FEAT_FGT2 151 el2_fgt2_regs_t fgt2; 152 #endif 153 154 #if ENABLE_FEAT_ECV 155 el2_ecv_regs_t ecv; 156 #endif 157 158 #if ENABLE_FEAT_VHE 159 el2_vhe_regs_t vhe; 160 #endif 161 162 #if ENABLE_FEAT_RAS 163 el2_ras_regs_t ras; 164 #endif 165 166 #if CTX_INCLUDE_NEVE_REGS 167 el2_neve_regs_t neve; 168 #endif 169 170 #if ENABLE_TRF_FOR_NS 171 el2_trf_regs_t trf; 172 #endif 173 174 #if ENABLE_FEAT_CSV2_2 175 el2_csv2_regs_t csv2; 176 #endif 177 178 #if ENABLE_FEAT_HCX 179 el2_hcx_regs_t hcx; 180 #endif 181 182 #if ENABLE_FEAT_TCR2 183 el2_tcr2_regs_t tcr2; 184 #endif 185 186 #if (ENABLE_FEAT_S1POE || ENABLE_FEAT_S2POE) 187 el2_sxpoe_regs_t sxpoe; 188 #endif 189 190 #if (ENABLE_FEAT_S1PIE || ENABLE_FEAT_S2PIE) 191 el2_sxpie_regs_t sxpie; 192 #endif 193 194 #if ENABLE_FEAT_S2PIE 195 el2_s2pie_regs_t s2pie; 196 #endif 197 198 #if ENABLE_FEAT_GCS 199 el2_gcs_regs_t gcs; 200 #endif 201 202 #if CTX_INCLUDE_MPAM_REGS 203 el2_mpam_regs_t mpam; 204 #endif 205 206 } el2_sysregs_t; 207 208 /* 209 * Macros to access members related to individual features of the el2_sysregs_t 210 * structures. 211 */ 212 #define read_el2_ctx_common(ctx, reg) (((ctx)->common).reg) 213 214 #define write_el2_ctx_common(ctx, reg, val) ((((ctx)->common).reg) \ 215 = (uint64_t) (val)) 216 217 #if ENABLE_FEAT_MTE2 218 #define read_el2_ctx_mte2(ctx, reg) (((ctx)->mte2).reg) 219 #define write_el2_ctx_mte2(ctx, reg, val) ((((ctx)->mte2).reg) \ 220 = (uint64_t) (val)) 221 #else 222 #define read_el2_ctx_mte2(ctx, reg) ULL(0) 223 #define write_el2_ctx_mte2(ctx, reg, val) 224 #endif /* ENABLE_FEAT_MTE2 */ 225 226 #if ENABLE_FEAT_FGT 227 #define read_el2_ctx_fgt(ctx, reg) (((ctx)->fgt).reg) 228 #define write_el2_ctx_fgt(ctx, reg, val) ((((ctx)->fgt).reg) \ 229 = (uint64_t) (val)) 230 #else 231 #define read_el2_ctx_fgt(ctx, reg) ULL(0) 232 #define write_el2_ctx_fgt(ctx, reg, val) 233 #endif /* ENABLE_FEAT_FGT */ 234 235 #if ENABLE_FEAT_FGT2 236 #define read_el2_ctx_fgt2(ctx, reg) (((ctx)->fgt2).reg) 237 #define write_el2_ctx_fgt2(ctx, reg, val) ((((ctx)->fgt2).reg) \ 238 = (uint64_t) (val)) 239 #else 240 #define read_el2_ctx_fgt2(ctx, reg) ULL(0) 241 #define write_el2_ctx_fgt2(ctx, reg, val) 242 #endif /* ENABLE_FEAT_FGT */ 243 244 #if ENABLE_FEAT_ECV 245 #define read_el2_ctx_ecv(ctx, reg) (((ctx)->ecv).reg) 246 #define write_el2_ctx_ecv(ctx, reg, val) ((((ctx)->ecv).reg) \ 247 = (uint64_t) (val)) 248 #else 249 #define read_el2_ctx_ecv(ctx, reg) ULL(0) 250 #define write_el2_ctx_ecv(ctx, reg, val) 251 #endif /* ENABLE_FEAT_ECV */ 252 253 #if ENABLE_FEAT_VHE 254 #define read_el2_ctx_vhe(ctx, reg) (((ctx)->vhe).reg) 255 #define write_el2_ctx_vhe(ctx, reg, val) ((((ctx)->vhe).reg) \ 256 = (uint64_t) (val)) 257 #else 258 #define read_el2_ctx_vhe(ctx, reg) ULL(0) 259 #define write_el2_ctx_vhe(ctx, reg, val) 260 #endif /* ENABLE_FEAT_VHE */ 261 262 #if ENABLE_FEAT_RAS 263 #define read_el2_ctx_ras(ctx, reg) (((ctx)->ras).reg) 264 #define write_el2_ctx_ras(ctx, reg, val) ((((ctx)->ras).reg) \ 265 = (uint64_t) (val)) 266 #else 267 #define read_el2_ctx_ras(ctx, reg) ULL(0) 268 #define write_el2_ctx_ras(ctx, reg, val) 269 #endif /* ENABLE_FEAT_RAS */ 270 271 #if CTX_INCLUDE_NEVE_REGS 272 #define read_el2_ctx_neve(ctx, reg) (((ctx)->neve).reg) 273 #define write_el2_ctx_neve(ctx, reg, val) ((((ctx)->neve).reg) \ 274 = (uint64_t) (val)) 275 #else 276 #define read_el2_ctx_neve(ctx, reg) ULL(0) 277 #define write_el2_ctx_neve(ctx, reg, val) 278 #endif /* CTX_INCLUDE_NEVE_REGS */ 279 280 #if ENABLE_TRF_FOR_NS 281 #define read_el2_ctx_trf(ctx, reg) (((ctx)->trf).reg) 282 #define write_el2_ctx_trf(ctx, reg, val) ((((ctx)->trf).reg) \ 283 = (uint64_t) (val)) 284 #else 285 #define read_el2_ctx_trf(ctx, reg) ULL(0) 286 #define write_el2_ctx_trf(ctx, reg, val) 287 #endif /* ENABLE_TRF_FOR_NS */ 288 289 #if ENABLE_FEAT_CSV2_2 290 #define read_el2_ctx_csv2_2(ctx, reg) (((ctx)->csv2).reg) 291 #define write_el2_ctx_csv2_2(ctx, reg, val) ((((ctx)->csv2).reg) \ 292 = (uint64_t) (val)) 293 #else 294 #define read_el2_ctx_csv2_2(ctx, reg) ULL(0) 295 #define write_el2_ctx_csv2_2(ctx, reg, val) 296 #endif /* ENABLE_FEAT_CSV2_2 */ 297 298 #if ENABLE_FEAT_HCX 299 #define read_el2_ctx_hcx(ctx, reg) (((ctx)->hcx).reg) 300 #define write_el2_ctx_hcx(ctx, reg, val) ((((ctx)->hcx).reg) \ 301 = (uint64_t) (val)) 302 #else 303 #define read_el2_ctx_hcx(ctx, reg) ULL(0) 304 #define write_el2_ctx_hcx(ctx, reg, val) 305 #endif /* ENABLE_FEAT_HCX */ 306 307 #if ENABLE_FEAT_TCR2 308 #define read_el2_ctx_tcr2(ctx, reg) (((ctx)->tcr2).reg) 309 #define write_el2_ctx_tcr2(ctx, reg, val) ((((ctx)->tcr2).reg) \ 310 = (uint64_t) (val)) 311 #else 312 #define read_el2_ctx_tcr2(ctx, reg) ULL(0) 313 #define write_el2_ctx_tcr2(ctx, reg, val) 314 #endif /* ENABLE_FEAT_TCR2 */ 315 316 #if (ENABLE_FEAT_S1POE || ENABLE_FEAT_S2POE) 317 #define read_el2_ctx_sxpoe(ctx, reg) (((ctx)->sxpoe).reg) 318 #define write_el2_ctx_sxpoe(ctx, reg, val) ((((ctx)->sxpoe).reg) \ 319 = (uint64_t) (val)) 320 #else 321 #define read_el2_ctx_sxpoe(ctx, reg) ULL(0) 322 #define write_el2_ctx_sxpoe(ctx, reg, val) 323 #endif /*(ENABLE_FEAT_S1POE || ENABLE_FEAT_S2POE) */ 324 325 #if (ENABLE_FEAT_S1PIE || ENABLE_FEAT_S2PIE) 326 #define read_el2_ctx_sxpie(ctx, reg) (((ctx)->sxpie).reg) 327 #define write_el2_ctx_sxpie(ctx, reg, val) ((((ctx)->sxpie).reg) \ 328 = (uint64_t) (val)) 329 #else 330 #define read_el2_ctx_sxpie(ctx, reg) ULL(0) 331 #define write_el2_ctx_sxpie(ctx, reg, val) 332 #endif /*(ENABLE_FEAT_S1PIE || ENABLE_FEAT_S2PIE) */ 333 334 #if ENABLE_FEAT_S2PIE 335 #define read_el2_ctx_s2pie(ctx, reg) (((ctx)->s2pie).reg) 336 #define write_el2_ctx_s2pie(ctx, reg, val) ((((ctx)->s2pie).reg) \ 337 = (uint64_t) (val)) 338 #else 339 #define read_el2_ctx_s2pie(ctx, reg) ULL(0) 340 #define write_el2_ctx_s2pie(ctx, reg, val) 341 #endif /* ENABLE_FEAT_S2PIE */ 342 343 #if ENABLE_FEAT_GCS 344 #define read_el2_ctx_gcs(ctx, reg) (((ctx)->gcs).reg) 345 #define write_el2_ctx_gcs(ctx, reg, val) ((((ctx)->gcs).reg) \ 346 = (uint64_t) (val)) 347 #else 348 #define read_el2_ctx_gcs(ctx, reg) ULL(0) 349 #define write_el2_ctx_gcs(ctx, reg, val) 350 #endif /* ENABLE_FEAT_GCS */ 351 352 #if CTX_INCLUDE_MPAM_REGS 353 #define read_el2_ctx_mpam(ctx, reg) (((ctx)->mpam).reg) 354 #define write_el2_ctx_mpam(ctx, reg, val) ((((ctx)->mpam).reg) \ 355 = (uint64_t) (val)) 356 #else 357 #define read_el2_ctx_mpam(ctx, reg) ULL(0) 358 #define write_el2_ctx_mpam(ctx, reg, val) 359 #endif /* CTX_INCLUDE_MPAM_REGS */ 360 361 /******************************************************************************/ 362 363 #endif /* __ASSEMBLER__ */ 364 365 #endif /* CONTEXT_EL2_H */ 366