1 /* 2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/debug.h> 9 #include <common/runtime_svc.h> 10 #include <lib/mmio.h> 11 #include <tools_share/uuid.h> 12 13 #include "socfpga_fcs.h" 14 #include "socfpga_mailbox.h" 15 #include "socfpga_reset_manager.h" 16 #include "socfpga_sip_svc.h" 17 18 19 /* Total buffer the driver can hold */ 20 #define FPGA_CONFIG_BUFFER_SIZE 4 21 22 static config_type request_type = NO_REQUEST; 23 static int current_block, current_buffer; 24 static int read_block, max_blocks; 25 static uint32_t send_id, rcv_id; 26 static uint32_t bytes_per_block, blocks_submitted; 27 static bool bridge_disable; 28 29 /* RSU static variables */ 30 static uint32_t rsu_dcmf_ver[4] = {0}; 31 static uint16_t rsu_dcmf_stat[4] = {0}; 32 static uint32_t rsu_max_retry; 33 34 /* SiP Service UUID */ 35 DEFINE_SVC_UUID2(intl_svc_uid, 36 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 37 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 38 39 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 40 uint64_t x1, 41 uint64_t x2, 42 uint64_t x3, 43 uint64_t x4, 44 void *cookie, 45 void *handle, 46 uint64_t flags) 47 { 48 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 49 SMC_RET1(handle, SMC_UNK); 50 } 51 52 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 53 54 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 55 { 56 uint32_t args[3]; 57 58 while (max_blocks > 0 && buffer->size > buffer->size_written) { 59 args[0] = (1<<8); 60 args[1] = buffer->addr + buffer->size_written; 61 if (buffer->size - buffer->size_written <= bytes_per_block) { 62 args[2] = buffer->size - buffer->size_written; 63 current_buffer++; 64 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 65 } else { 66 args[2] = bytes_per_block; 67 } 68 69 buffer->size_written += args[2]; 70 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 71 3U, CMD_INDIRECT); 72 73 buffer->subblocks_sent++; 74 max_blocks--; 75 } 76 77 return !max_blocks; 78 } 79 80 static int intel_fpga_sdm_write_all(void) 81 { 82 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 83 if (intel_fpga_sdm_write_buffer( 84 &fpga_config_buffers[current_buffer])) { 85 break; 86 } 87 } 88 return 0; 89 } 90 91 static uint32_t intel_mailbox_fpga_config_isdone(void) 92 { 93 uint32_t ret; 94 95 switch (request_type) { 96 case RECONFIGURATION: 97 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 98 true); 99 break; 100 case BITSTREAM_AUTH: 101 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 102 false); 103 break; 104 default: 105 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, 106 false); 107 break; 108 } 109 110 if (ret != 0U) { 111 if (ret == MBOX_CFGSTAT_STATE_CONFIG) { 112 return INTEL_SIP_SMC_STATUS_BUSY; 113 } else { 114 request_type = NO_REQUEST; 115 return INTEL_SIP_SMC_STATUS_ERROR; 116 } 117 } 118 119 if (bridge_disable != 0U) { 120 socfpga_bridges_enable(~0); /* Enable bridge */ 121 bridge_disable = false; 122 } 123 request_type = NO_REQUEST; 124 125 return INTEL_SIP_SMC_STATUS_OK; 126 } 127 128 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 129 { 130 int i; 131 132 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 133 if (fpga_config_buffers[i].block_number == current_block) { 134 fpga_config_buffers[i].subblocks_sent--; 135 if (fpga_config_buffers[i].subblocks_sent == 0 136 && fpga_config_buffers[i].size <= 137 fpga_config_buffers[i].size_written) { 138 fpga_config_buffers[i].write_requested = 0; 139 current_block++; 140 *buffer_addr_completed = 141 fpga_config_buffers[i].addr; 142 return 0; 143 } 144 } 145 } 146 147 return -1; 148 } 149 150 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 151 uint32_t *count, uint32_t *job_id) 152 { 153 uint32_t resp[5]; 154 unsigned int resp_len = ARRAY_SIZE(resp); 155 int status = INTEL_SIP_SMC_STATUS_OK; 156 int all_completed = 1; 157 *count = 0; 158 159 while (*count < 3) { 160 161 status = mailbox_read_response(job_id, 162 resp, &resp_len); 163 164 if (status < 0) { 165 break; 166 } 167 168 max_blocks++; 169 170 if (mark_last_buffer_xfer_completed( 171 &completed_addr[*count]) == 0) { 172 *count = *count + 1; 173 } else { 174 break; 175 } 176 } 177 178 if (*count <= 0) { 179 if (status != MBOX_NO_RESPONSE && 180 status != MBOX_TIMEOUT && resp_len != 0) { 181 mailbox_clear_response(); 182 request_type = NO_REQUEST; 183 return INTEL_SIP_SMC_STATUS_ERROR; 184 } 185 186 *count = 0; 187 } 188 189 intel_fpga_sdm_write_all(); 190 191 if (*count > 0) { 192 status = INTEL_SIP_SMC_STATUS_OK; 193 } else if (*count == 0) { 194 status = INTEL_SIP_SMC_STATUS_BUSY; 195 } 196 197 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 198 if (fpga_config_buffers[i].write_requested != 0) { 199 all_completed = 0; 200 break; 201 } 202 } 203 204 if (all_completed == 1) { 205 return INTEL_SIP_SMC_STATUS_OK; 206 } 207 208 return status; 209 } 210 211 static int intel_fpga_config_start(uint32_t flag) 212 { 213 uint32_t argument = 0x1; 214 uint32_t response[3]; 215 int status = 0; 216 unsigned int size = 0; 217 unsigned int resp_len = ARRAY_SIZE(response); 218 219 request_type = RECONFIGURATION; 220 221 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) { 222 bridge_disable = true; 223 } 224 225 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) { 226 size = 1; 227 bridge_disable = false; 228 request_type = BITSTREAM_AUTH; 229 } 230 231 mailbox_clear_response(); 232 233 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 234 CMD_CASUAL, NULL, NULL); 235 236 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 237 CMD_CASUAL, response, &resp_len); 238 239 if (status < 0) { 240 bridge_disable = false; 241 request_type = NO_REQUEST; 242 return INTEL_SIP_SMC_STATUS_ERROR; 243 } 244 245 max_blocks = response[0]; 246 bytes_per_block = response[1]; 247 248 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 249 fpga_config_buffers[i].size = 0; 250 fpga_config_buffers[i].size_written = 0; 251 fpga_config_buffers[i].addr = 0; 252 fpga_config_buffers[i].write_requested = 0; 253 fpga_config_buffers[i].block_number = 0; 254 fpga_config_buffers[i].subblocks_sent = 0; 255 } 256 257 blocks_submitted = 0; 258 current_block = 0; 259 read_block = 0; 260 current_buffer = 0; 261 262 /* Disable bridge on full reconfiguration */ 263 if (bridge_disable) { 264 socfpga_bridges_disable(~0); 265 } 266 267 return INTEL_SIP_SMC_STATUS_OK; 268 } 269 270 static bool is_fpga_config_buffer_full(void) 271 { 272 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 273 if (!fpga_config_buffers[i].write_requested) { 274 return false; 275 } 276 } 277 return true; 278 } 279 280 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 281 { 282 if (!addr && !size) { 283 return true; 284 } 285 if (size > (UINT64_MAX - addr)) { 286 return false; 287 } 288 if (addr < BL31_LIMIT) { 289 return false; 290 } 291 if (addr + size > DRAM_BASE + DRAM_SIZE) { 292 return false; 293 } 294 295 return true; 296 } 297 298 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 299 { 300 int i; 301 302 intel_fpga_sdm_write_all(); 303 304 if (!is_address_in_ddr_range(mem, size) || 305 is_fpga_config_buffer_full()) { 306 return INTEL_SIP_SMC_STATUS_REJECTED; 307 } 308 309 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 310 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 311 312 if (!fpga_config_buffers[j].write_requested) { 313 fpga_config_buffers[j].addr = mem; 314 fpga_config_buffers[j].size = size; 315 fpga_config_buffers[j].size_written = 0; 316 fpga_config_buffers[j].write_requested = 1; 317 fpga_config_buffers[j].block_number = 318 blocks_submitted++; 319 fpga_config_buffers[j].subblocks_sent = 0; 320 break; 321 } 322 } 323 324 if (is_fpga_config_buffer_full()) { 325 return INTEL_SIP_SMC_STATUS_BUSY; 326 } 327 328 return INTEL_SIP_SMC_STATUS_OK; 329 } 330 331 static int is_out_of_sec_range(uint64_t reg_addr) 332 { 333 #if DEBUG 334 return 0; 335 #endif 336 337 switch (reg_addr) { 338 case(0xF8011100): /* ECCCTRL1 */ 339 case(0xF8011104): /* ECCCTRL2 */ 340 case(0xF8011110): /* ERRINTEN */ 341 case(0xF8011114): /* ERRINTENS */ 342 case(0xF8011118): /* ERRINTENR */ 343 case(0xF801111C): /* INTMODE */ 344 case(0xF8011120): /* INTSTAT */ 345 case(0xF8011124): /* DIAGINTTEST */ 346 case(0xF801112C): /* DERRADDRA */ 347 case(0xFA000000): /* SMMU SCR0 */ 348 case(0xFA000004): /* SMMU SCR1 */ 349 case(0xFA000400): /* SMMU NSCR0 */ 350 case(0xFA004000): /* SMMU SSD0_REG */ 351 case(0xFA000820): /* SMMU SMR8 */ 352 case(0xFA000c20): /* SMMU SCR8 */ 353 case(0xFA028000): /* SMMU CB8_SCTRL */ 354 case(0xFA001020): /* SMMU CBAR8 */ 355 case(0xFA028030): /* SMMU TCR_LPAE */ 356 case(0xFA028020): /* SMMU CB8_TTBR0_LOW */ 357 case(0xFA028024): /* SMMU CB8_PRRR_HIGH */ 358 case(0xFA028038): /* SMMU CB8_PRRR_MIR0 */ 359 case(0xFA02803C): /* SMMU CB8_PRRR_MIR1 */ 360 case(0xFA028010): /* SMMU_CB8)TCR2 */ 361 case(0xFFD080A4): /* SDM SMMU STREAM ID REG */ 362 case(0xFA001820): /* SMMU_CBA2R8 */ 363 case(0xFA000074): /* SMMU_STLBGSTATUS */ 364 case(0xFA0287F4): /* SMMU_CB8_TLBSTATUS */ 365 case(0xFA000060): /* SMMU_STLBIALL */ 366 case(0xFA000070): /* SMMU_STLBGSYNC */ 367 case(0xFA028618): /* CB8_TLBALL */ 368 case(0xFA0287F0): /* CB8_TLBSYNC */ 369 case(0xFFD12028): /* SDMMCGRP_CTRL */ 370 case(0xFFD12044): /* EMAC0 */ 371 case(0xFFD12048): /* EMAC1 */ 372 case(0xFFD1204C): /* EMAC2 */ 373 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 374 case(0xFFD12094): /* ECC_INT_MASK_SET */ 375 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 376 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 377 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 378 case(0xFFD120C0): /* NOC_TIMEOUT */ 379 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 380 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 381 case(0xFFD120D0): /* NOC_IDLEACK */ 382 case(0xFFD120D4): /* NOC_IDLESTATUS */ 383 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 384 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 385 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 386 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 387 return 0; 388 389 default: 390 break; 391 } 392 393 return -1; 394 } 395 396 /* Secure register access */ 397 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 398 { 399 if (is_out_of_sec_range(reg_addr)) { 400 return INTEL_SIP_SMC_STATUS_ERROR; 401 } 402 403 *retval = mmio_read_32(reg_addr); 404 405 return INTEL_SIP_SMC_STATUS_OK; 406 } 407 408 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 409 uint32_t *retval) 410 { 411 if (is_out_of_sec_range(reg_addr)) { 412 return INTEL_SIP_SMC_STATUS_ERROR; 413 } 414 415 mmio_write_32(reg_addr, val); 416 417 return intel_secure_reg_read(reg_addr, retval); 418 } 419 420 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 421 uint32_t val, uint32_t *retval) 422 { 423 if (!intel_secure_reg_read(reg_addr, retval)) { 424 *retval &= ~mask; 425 *retval |= val & mask; 426 return intel_secure_reg_write(reg_addr, *retval, retval); 427 } 428 429 return INTEL_SIP_SMC_STATUS_ERROR; 430 } 431 432 /* Intel Remote System Update (RSU) services */ 433 uint64_t intel_rsu_update_address; 434 435 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 436 { 437 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 438 return INTEL_SIP_SMC_RSU_ERROR; 439 } 440 441 return INTEL_SIP_SMC_STATUS_OK; 442 } 443 444 static uint32_t intel_rsu_update(uint64_t update_address) 445 { 446 intel_rsu_update_address = update_address; 447 return INTEL_SIP_SMC_STATUS_OK; 448 } 449 450 static uint32_t intel_rsu_notify(uint32_t execution_stage) 451 { 452 if (mailbox_hps_stage_notify(execution_stage) < 0) { 453 return INTEL_SIP_SMC_RSU_ERROR; 454 } 455 456 return INTEL_SIP_SMC_STATUS_OK; 457 } 458 459 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 460 uint32_t *ret_stat) 461 { 462 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 463 return INTEL_SIP_SMC_RSU_ERROR; 464 } 465 466 *ret_stat = respbuf[8]; 467 return INTEL_SIP_SMC_STATUS_OK; 468 } 469 470 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 471 uint64_t dcmf_ver_3_2) 472 { 473 rsu_dcmf_ver[0] = dcmf_ver_1_0; 474 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 475 rsu_dcmf_ver[2] = dcmf_ver_3_2; 476 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 477 478 return INTEL_SIP_SMC_STATUS_OK; 479 } 480 481 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) 482 { 483 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); 484 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); 485 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); 486 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); 487 488 return INTEL_SIP_SMC_STATUS_OK; 489 } 490 491 /* Intel HWMON services */ 492 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval) 493 { 494 if (mailbox_hwmon_readtemp(chan, retval) < 0) { 495 return INTEL_SIP_SMC_STATUS_ERROR; 496 } 497 498 return INTEL_SIP_SMC_STATUS_OK; 499 } 500 501 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval) 502 { 503 if (mailbox_hwmon_readvolt(chan, retval) < 0) { 504 return INTEL_SIP_SMC_STATUS_ERROR; 505 } 506 507 return INTEL_SIP_SMC_STATUS_OK; 508 } 509 510 /* Mailbox services */ 511 static uint32_t intel_smc_fw_version(uint32_t *fw_version) 512 { 513 int status; 514 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE; 515 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U}; 516 517 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U, 518 CMD_CASUAL, resp_data, &resp_len); 519 520 if (status < 0) { 521 return INTEL_SIP_SMC_STATUS_ERROR; 522 } 523 524 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) { 525 return INTEL_SIP_SMC_STATUS_ERROR; 526 } 527 528 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK; 529 530 return INTEL_SIP_SMC_STATUS_OK; 531 } 532 533 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 534 unsigned int len, uint32_t urgent, uint64_t response, 535 unsigned int resp_len, int *mbox_status, 536 unsigned int *len_in_resp) 537 { 538 *len_in_resp = 0; 539 *mbox_status = GENERIC_RESPONSE_ERROR; 540 541 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) { 542 return INTEL_SIP_SMC_STATUS_REJECTED; 543 } 544 545 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 546 (uint32_t *) response, &resp_len); 547 548 if (status < 0) { 549 *mbox_status = -status; 550 return INTEL_SIP_SMC_STATUS_ERROR; 551 } 552 553 *mbox_status = 0; 554 *len_in_resp = resp_len; 555 556 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE); 557 558 return INTEL_SIP_SMC_STATUS_OK; 559 } 560 561 static int intel_smc_get_usercode(uint32_t *user_code) 562 { 563 int status; 564 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE; 565 566 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL, 567 0U, CMD_CASUAL, user_code, &resp_len); 568 569 if (status < 0) { 570 return INTEL_SIP_SMC_STATUS_ERROR; 571 } 572 573 return INTEL_SIP_SMC_STATUS_OK; 574 } 575 576 uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size, 577 uint32_t mode, uint32_t *job_id, 578 uint32_t *ret_size, uint32_t *mbox_error) 579 { 580 int status = 0; 581 uint32_t resp_len = size / MBOX_WORD_BYTE; 582 583 if (resp_len > MBOX_DATA_MAX_LEN) { 584 return INTEL_SIP_SMC_STATUS_REJECTED; 585 } 586 587 if (!is_address_in_ddr_range(addr, size)) { 588 return INTEL_SIP_SMC_STATUS_REJECTED; 589 } 590 591 if (mode == SERVICE_COMPLETED_MODE_ASYNC) { 592 status = mailbox_read_response_async(job_id, 593 NULL, (uint32_t *) addr, &resp_len, 0); 594 } else { 595 status = mailbox_read_response(job_id, 596 (uint32_t *) addr, &resp_len); 597 598 if (status == MBOX_NO_RESPONSE) { 599 status = MBOX_BUSY; 600 } 601 } 602 603 if (status == MBOX_NO_RESPONSE) { 604 return INTEL_SIP_SMC_STATUS_NO_RESPONSE; 605 } 606 607 if (status == MBOX_BUSY) { 608 return INTEL_SIP_SMC_STATUS_BUSY; 609 } 610 611 *ret_size = resp_len * MBOX_WORD_BYTE; 612 flush_dcache_range(addr, *ret_size); 613 614 if (status != MBOX_RET_OK) { 615 *mbox_error = -status; 616 return INTEL_SIP_SMC_STATUS_ERROR; 617 } 618 619 return INTEL_SIP_SMC_STATUS_OK; 620 } 621 622 /* Miscellaneous HPS services */ 623 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask) 624 { 625 int status = 0; 626 627 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) { 628 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 629 status = socfpga_bridges_enable((uint32_t)mask); 630 } else { 631 status = socfpga_bridges_enable(~0); 632 } 633 } else { 634 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 635 status = socfpga_bridges_disable((uint32_t)mask); 636 } else { 637 status = socfpga_bridges_disable(~0); 638 } 639 } 640 641 if (status < 0) { 642 return INTEL_SIP_SMC_STATUS_ERROR; 643 } 644 645 return INTEL_SIP_SMC_STATUS_OK; 646 } 647 648 /* 649 * This function is responsible for handling all SiP calls from the NS world 650 */ 651 652 uintptr_t sip_smc_handler_v1(uint32_t smc_fid, 653 u_register_t x1, 654 u_register_t x2, 655 u_register_t x3, 656 u_register_t x4, 657 void *cookie, 658 void *handle, 659 u_register_t flags) 660 { 661 uint32_t retval = 0, completed_addr[3]; 662 uint32_t retval2 = 0; 663 uint32_t mbox_error = 0; 664 uint64_t retval64, rsu_respbuf[9]; 665 int status = INTEL_SIP_SMC_STATUS_OK; 666 int mbox_status; 667 unsigned int len_in_resp; 668 u_register_t x5, x6, x7; 669 670 switch (smc_fid) { 671 case SIP_SVC_UID: 672 /* Return UID to the caller */ 673 SMC_UUID_RET(handle, intl_svc_uid); 674 675 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 676 status = intel_mailbox_fpga_config_isdone(); 677 SMC_RET4(handle, status, 0, 0, 0); 678 679 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 680 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 681 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 682 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 683 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 684 685 case INTEL_SIP_SMC_FPGA_CONFIG_START: 686 status = intel_fpga_config_start(x1); 687 SMC_RET4(handle, status, 0, 0, 0); 688 689 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 690 status = intel_fpga_config_write(x1, x2); 691 SMC_RET4(handle, status, 0, 0, 0); 692 693 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 694 status = intel_fpga_config_completed_write(completed_addr, 695 &retval, &rcv_id); 696 switch (retval) { 697 case 1: 698 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 699 completed_addr[0], 0, 0); 700 701 case 2: 702 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 703 completed_addr[0], 704 completed_addr[1], 0); 705 706 case 3: 707 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 708 completed_addr[0], 709 completed_addr[1], 710 completed_addr[2]); 711 712 case 0: 713 SMC_RET4(handle, status, 0, 0, 0); 714 715 default: 716 mailbox_clear_response(); 717 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 718 } 719 720 case INTEL_SIP_SMC_REG_READ: 721 status = intel_secure_reg_read(x1, &retval); 722 SMC_RET3(handle, status, retval, x1); 723 724 case INTEL_SIP_SMC_REG_WRITE: 725 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 726 SMC_RET3(handle, status, retval, x1); 727 728 case INTEL_SIP_SMC_REG_UPDATE: 729 status = intel_secure_reg_update(x1, (uint32_t)x2, 730 (uint32_t)x3, &retval); 731 SMC_RET3(handle, status, retval, x1); 732 733 case INTEL_SIP_SMC_RSU_STATUS: 734 status = intel_rsu_status(rsu_respbuf, 735 ARRAY_SIZE(rsu_respbuf)); 736 if (status) { 737 SMC_RET1(handle, status); 738 } else { 739 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 740 rsu_respbuf[2], rsu_respbuf[3]); 741 } 742 743 case INTEL_SIP_SMC_RSU_UPDATE: 744 status = intel_rsu_update(x1); 745 SMC_RET1(handle, status); 746 747 case INTEL_SIP_SMC_RSU_NOTIFY: 748 status = intel_rsu_notify(x1); 749 SMC_RET1(handle, status); 750 751 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 752 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 753 ARRAY_SIZE(rsu_respbuf), &retval); 754 if (status) { 755 SMC_RET1(handle, status); 756 } else { 757 SMC_RET2(handle, status, retval); 758 } 759 760 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 761 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 762 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 763 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 764 765 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 766 status = intel_rsu_copy_dcmf_version(x1, x2); 767 SMC_RET1(handle, status); 768 769 case INTEL_SIP_SMC_RSU_DCMF_STATUS: 770 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, 771 ((uint64_t)rsu_dcmf_stat[3] << 48) | 772 ((uint64_t)rsu_dcmf_stat[2] << 32) | 773 ((uint64_t)rsu_dcmf_stat[1] << 16) | 774 rsu_dcmf_stat[0]); 775 776 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: 777 status = intel_rsu_copy_dcmf_status(x1); 778 SMC_RET1(handle, status); 779 780 case INTEL_SIP_SMC_RSU_MAX_RETRY: 781 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 782 783 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 784 rsu_max_retry = x1; 785 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 786 787 case INTEL_SIP_SMC_ECC_DBE: 788 status = intel_ecc_dbe_notification(x1); 789 SMC_RET1(handle, status); 790 791 case INTEL_SIP_SMC_SERVICE_COMPLETED: 792 status = intel_smc_service_completed(x1, x2, x3, &rcv_id, 793 &len_in_resp, &mbox_error); 794 SMC_RET4(handle, status, mbox_error, x1, len_in_resp); 795 796 case INTEL_SIP_SMC_FIRMWARE_VERSION: 797 status = intel_smc_fw_version(&retval); 798 SMC_RET2(handle, status, retval); 799 800 case INTEL_SIP_SMC_MBOX_SEND_CMD: 801 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 802 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 803 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6, 804 &mbox_status, &len_in_resp); 805 SMC_RET3(handle, status, mbox_status, len_in_resp); 806 807 case INTEL_SIP_SMC_GET_USERCODE: 808 status = intel_smc_get_usercode(&retval); 809 SMC_RET2(handle, status, retval); 810 811 case INTEL_SIP_SMC_FCS_CRYPTION: 812 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 813 814 if (x1 == FCS_MODE_DECRYPT) { 815 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id); 816 } else if (x1 == FCS_MODE_ENCRYPT) { 817 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id); 818 } else { 819 status = INTEL_SIP_SMC_STATUS_REJECTED; 820 } 821 822 SMC_RET3(handle, status, x4, x5); 823 824 case INTEL_SIP_SMC_FCS_CRYPTION_EXT: 825 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 826 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 827 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 828 829 if (x3 == FCS_MODE_DECRYPT) { 830 status = intel_fcs_decryption_ext(x1, x2, x4, x5, x6, 831 (uint32_t *) &x7, &mbox_error); 832 } else if (x3 == FCS_MODE_ENCRYPT) { 833 status = intel_fcs_encryption_ext(x1, x2, x4, x5, x6, 834 (uint32_t *) &x7, &mbox_error); 835 } else { 836 status = INTEL_SIP_SMC_STATUS_REJECTED; 837 } 838 839 SMC_RET4(handle, status, mbox_error, x6, x7); 840 841 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER: 842 status = intel_fcs_random_number_gen(x1, &retval64, 843 &mbox_error); 844 SMC_RET4(handle, status, mbox_error, x1, retval64); 845 846 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT: 847 status = intel_fcs_random_number_gen_ext(x1, x2, x3, 848 &send_id); 849 SMC_RET1(handle, status); 850 851 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE: 852 status = intel_fcs_send_cert(x1, x2, &send_id); 853 SMC_RET1(handle, status); 854 855 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA: 856 status = intel_fcs_get_provision_data(&send_id); 857 SMC_RET1(handle, status); 858 859 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH: 860 status = intel_fcs_cntr_set_preauth(x1, x2, x3, 861 &mbox_error); 862 SMC_RET2(handle, status, mbox_error); 863 864 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 865 status = intel_hps_set_bridges(x1, x2); 866 SMC_RET1(handle, status); 867 868 case INTEL_SIP_SMC_HWMON_READTEMP: 869 status = intel_hwmon_readtemp(x1, &retval); 870 SMC_RET2(handle, status, retval); 871 872 case INTEL_SIP_SMC_HWMON_READVOLT: 873 status = intel_hwmon_readvolt(x1, &retval); 874 SMC_RET2(handle, status, retval); 875 876 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN: 877 status = intel_fcs_sigma_teardown(x1, &mbox_error); 878 SMC_RET2(handle, status, mbox_error); 879 880 case INTEL_SIP_SMC_FCS_CHIP_ID: 881 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error); 882 SMC_RET4(handle, status, mbox_error, retval, retval2); 883 884 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY: 885 status = intel_fcs_attestation_subkey(x1, x2, x3, 886 (uint32_t *) &x4, &mbox_error); 887 SMC_RET4(handle, status, mbox_error, x3, x4); 888 889 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS: 890 status = intel_fcs_get_measurement(x1, x2, x3, 891 (uint32_t *) &x4, &mbox_error); 892 SMC_RET4(handle, status, mbox_error, x3, x4); 893 894 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT: 895 status = intel_fcs_get_attestation_cert(x1, x2, 896 (uint32_t *) &x3, &mbox_error); 897 SMC_RET4(handle, status, mbox_error, x2, x3); 898 899 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD: 900 status = intel_fcs_create_cert_on_reload(x1, &mbox_error); 901 SMC_RET2(handle, status, mbox_error); 902 903 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION: 904 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error); 905 SMC_RET3(handle, status, mbox_error, retval); 906 907 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION: 908 status = intel_fcs_close_crypto_service_session(x1, &mbox_error); 909 SMC_RET2(handle, status, mbox_error); 910 911 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY: 912 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id); 913 SMC_RET1(handle, status); 914 915 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY: 916 status = intel_fcs_export_crypto_service_key(x1, x2, x3, 917 (uint32_t *) &x4, &mbox_error); 918 SMC_RET4(handle, status, mbox_error, x3, x4); 919 920 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY: 921 status = intel_fcs_remove_crypto_service_key(x1, x2, 922 &mbox_error); 923 SMC_RET2(handle, status, mbox_error); 924 925 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO: 926 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3, 927 (uint32_t *) &x4, &mbox_error); 928 SMC_RET4(handle, status, mbox_error, x3, x4); 929 930 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT: 931 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 932 status = intel_fcs_get_digest_init(x1, x2, x3, 933 x4, x5, &mbox_error); 934 SMC_RET2(handle, status, mbox_error); 935 936 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE: 937 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 938 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 939 status = intel_fcs_get_digest_update_finalize(x1, x2, x3, 940 x4, x5, (uint32_t *) &x6, false, 941 &mbox_error); 942 SMC_RET4(handle, status, mbox_error, x5, x6); 943 944 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE: 945 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 946 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 947 status = intel_fcs_get_digest_update_finalize(x1, x2, x3, 948 x4, x5, (uint32_t *) &x6, true, 949 &mbox_error); 950 SMC_RET4(handle, status, mbox_error, x5, x6); 951 952 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE: 953 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 954 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 955 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 956 x4, x5, (uint32_t *) &x6, false, 957 &mbox_error, &send_id); 958 SMC_RET4(handle, status, mbox_error, x5, x6); 959 960 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE: 961 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 962 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 963 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 964 x4, x5, (uint32_t *) &x6, true, 965 &mbox_error, &send_id); 966 SMC_RET4(handle, status, mbox_error, x5, x6); 967 968 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT: 969 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 970 status = intel_fcs_mac_verify_init(x1, x2, x3, 971 x4, x5, &mbox_error); 972 SMC_RET2(handle, status, mbox_error); 973 974 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE: 975 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 976 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 977 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 978 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, 979 x4, x5, (uint32_t *) &x6, x7, 980 false, &mbox_error); 981 SMC_RET4(handle, status, mbox_error, x5, x6); 982 983 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE: 984 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 985 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 986 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 987 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, 988 x4, x5, (uint32_t *) &x6, x7, 989 true, &mbox_error); 990 SMC_RET4(handle, status, mbox_error, x5, x6); 991 992 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE: 993 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 994 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 995 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 996 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 997 x4, x5, (uint32_t *) &x6, x7, 998 false, &mbox_error, &send_id); 999 SMC_RET4(handle, status, mbox_error, x5, x6); 1000 1001 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE: 1002 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1003 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1004 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1005 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 1006 x4, x5, (uint32_t *) &x6, x7, 1007 true, &mbox_error, &send_id); 1008 SMC_RET4(handle, status, mbox_error, x5, x6); 1009 1010 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 1011 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1012 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3, 1013 x4, x5, &mbox_error); 1014 SMC_RET2(handle, status, mbox_error); 1015 1016 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 1017 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1018 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1019 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 1020 x3, x4, x5, (uint32_t *) &x6, false, 1021 &mbox_error); 1022 SMC_RET4(handle, status, mbox_error, x5, x6); 1023 1024 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 1025 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1026 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1027 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 1028 x3, x4, x5, (uint32_t *) &x6, true, 1029 &mbox_error); 1030 SMC_RET4(handle, status, mbox_error, x5, x6); 1031 1032 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE: 1033 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1034 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1035 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 1036 x2, x3, x4, x5, (uint32_t *) &x6, false, 1037 &mbox_error, &send_id); 1038 SMC_RET4(handle, status, mbox_error, x5, x6); 1039 1040 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE: 1041 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1042 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1043 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 1044 x2, x3, x4, x5, (uint32_t *) &x6, true, 1045 &mbox_error, &send_id); 1046 SMC_RET4(handle, status, mbox_error, x5, x6); 1047 1048 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT: 1049 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1050 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3, 1051 x4, x5, &mbox_error); 1052 SMC_RET2(handle, status, mbox_error); 1053 1054 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE: 1055 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1056 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1057 status = intel_fcs_ecdsa_hash_sign_finalize(x1, x2, x3, 1058 x4, x5, (uint32_t *) &x6, &mbox_error); 1059 SMC_RET4(handle, status, mbox_error, x5, x6); 1060 1061 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 1062 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1063 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3, 1064 x4, x5, &mbox_error); 1065 SMC_RET2(handle, status, mbox_error); 1066 1067 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 1068 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1069 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1070 status = intel_fcs_ecdsa_hash_sig_verify_finalize(x1, x2, x3, 1071 x4, x5, (uint32_t *) &x6, &mbox_error); 1072 SMC_RET4(handle, status, mbox_error, x5, x6); 1073 1074 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 1075 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1076 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3, 1077 x4, x5, &mbox_error); 1078 SMC_RET2(handle, status, mbox_error); 1079 1080 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 1081 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1082 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1083 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1084 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1085 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1086 x7, false, &mbox_error); 1087 SMC_RET4(handle, status, mbox_error, x5, x6); 1088 1089 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE: 1090 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1091 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1092 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1093 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 1094 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1095 x7, false, &mbox_error, &send_id); 1096 SMC_RET4(handle, status, mbox_error, x5, x6); 1097 1098 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE: 1099 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1100 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1101 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1102 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 1103 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1104 x7, true, &mbox_error, &send_id); 1105 SMC_RET4(handle, status, mbox_error, x5, x6); 1106 1107 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 1108 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1109 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1110 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1111 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1112 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1113 x7, true, &mbox_error); 1114 SMC_RET4(handle, status, mbox_error, x5, x6); 1115 1116 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT: 1117 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1118 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3, 1119 x4, x5, &mbox_error); 1120 SMC_RET2(handle, status, mbox_error); 1121 1122 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 1123 status = intel_fcs_ecdsa_get_pubkey_finalize(x1, x2, x3, 1124 (uint32_t *) &x4, &mbox_error); 1125 SMC_RET4(handle, status, mbox_error, x3, x4); 1126 1127 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT: 1128 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1129 status = intel_fcs_ecdh_request_init(x1, x2, x3, 1130 x4, x5, &mbox_error); 1131 SMC_RET2(handle, status, mbox_error); 1132 1133 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE: 1134 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1135 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1136 status = intel_fcs_ecdh_request_finalize(x1, x2, x3, 1137 x4, x5, (uint32_t *) &x6, &mbox_error); 1138 SMC_RET4(handle, status, mbox_error, x5, x6); 1139 1140 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT: 1141 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1142 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5, 1143 &mbox_error); 1144 SMC_RET2(handle, status, mbox_error); 1145 1146 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE: 1147 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1148 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1149 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1150 x5, x6, false, &send_id); 1151 SMC_RET1(handle, status); 1152 1153 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE: 1154 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1155 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1156 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1157 x5, x6, true, &send_id); 1158 SMC_RET1(handle, status); 1159 1160 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 1161 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 1162 &mbox_error); 1163 SMC_RET4(handle, status, mbox_error, x1, retval64); 1164 1165 case INTEL_SIP_SMC_SVC_VERSION: 1166 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 1167 SIP_SVC_VERSION_MAJOR, 1168 SIP_SVC_VERSION_MINOR); 1169 1170 default: 1171 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 1172 cookie, handle, flags); 1173 } 1174 } 1175 1176 uintptr_t sip_smc_handler(uint32_t smc_fid, 1177 u_register_t x1, 1178 u_register_t x2, 1179 u_register_t x3, 1180 u_register_t x4, 1181 void *cookie, 1182 void *handle, 1183 u_register_t flags) 1184 { 1185 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK; 1186 1187 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN && 1188 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) { 1189 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4, 1190 cookie, handle, flags); 1191 } else { 1192 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4, 1193 cookie, handle, flags); 1194 } 1195 } 1196 1197 DECLARE_RT_SVC( 1198 socfpga_sip_svc, 1199 OEN_SIP_START, 1200 OEN_SIP_END, 1201 SMC_TYPE_FAST, 1202 NULL, 1203 sip_smc_handler 1204 ); 1205 1206 DECLARE_RT_SVC( 1207 socfpga_sip_svc_std, 1208 OEN_SIP_START, 1209 OEN_SIP_END, 1210 SMC_TYPE_YIELD, 1211 NULL, 1212 sip_smc_handler 1213 ); 1214