1 /* 2 * Copyright (c) 2023, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef APUSYS_POWER_H 8 #define APUSYS_POWER_H 9 10 #include <platform_def.h> 11 12 enum APU_CLKSRC_ID { 13 PLL_CONN = 0, /* MNOC */ 14 PLL_UP, 15 PLL_VPU, 16 PLL_DLA, 17 PLL_NUM, 18 }; 19 20 enum APU_ARE_ID { 21 APU_ARE0 = 0, 22 APU_ARE1, 23 APU_ARE2, 24 APU_ARE_NUM, 25 }; 26 27 #define APU_POLL_STEP_US (5) 28 29 #define OUT_CLK_FREQ_MIN (1500) 30 #define BASIC_CLK_FREQ (26) 31 #define DDS_SHIFT (14) 32 33 #define APUPLL0_DEFAULT_FREQ (900) 34 #define APUPLL1_DEFAULT_FREQ (832) 35 #define APUPLL2_DEFAULT_FREQ (700) 36 #define APUPLL3_DEFAULT_FREQ (700) 37 38 #define APU_TOP_ON_POLLING_TIMEOUT_US (10000) 39 #define APU_TOP_OFF_POLLING_TIMEOUT_US (5 * APU_TOP_ON_POLLING_TIMEOUT_US) 40 #define APU_ARE_POLLING_TIMEOUT_US (10000) 41 42 /* APU related reg */ 43 #define APU_RPC_BASE (APU_RPCTOP) 44 #define APU_PCU_BASE (APU_PCUTOP) 45 #define APU_ARE0_BASE (APU_ARETOP_ARE0) 46 #define APU_ARE1_BASE (APU_ARETOP_ARE1) 47 #define APU_ARE2_BASE (APU_ARETOP_ARE2) 48 #define APU_AO_CTL_BASE (APU_AO_CTRL) 49 #define APU_PLL_BASE (APU_PLL) 50 #define APU_ACC_BASE (APU_ACC) 51 #define APU_ACX0_RPC_LITE_BASE (APU_ACX0_RPC_LITE) 52 53 /* RPC offset define */ 54 #define APU_RPC_TOP_SEL (0x0004) 55 #define APU_RPC_TOP_SEL_1 (0x0018) 56 #define APU_RPC_HW_CON (0x001c) 57 #define APU_RPC_SW_TYPE0 (0x0200) 58 59 /* RPC control */ 60 #define SRAM_AOC_ISO_CLR BIT(7) 61 #define BUCK_ELS_EN_SET BIT(10) 62 #define BUCK_ELS_EN_CLR BIT(11) 63 #define BUCK_AO_RST_B_SET BIT(12) 64 #define BUCK_AO_RST_B_CLR BIT(13) 65 #define BUCK_PROT_REQ_SET BIT(14) 66 #define BUCK_PROT_REQ_CLR BIT(15) 67 #define SW_TYPE BIT(1) 68 #define RPC_CTRL (0x0000009e) 69 #define RPC_TOP_CTRL (0x0800501e) 70 #define RPC_TOP_CTRL1 BIT(20) 71 72 /* PLL offset define */ 73 #define PLL4H_PLL1_CON1 (0x000c) 74 #define PLL4H_PLL2_CON1 (0x001c) 75 #define PLL4H_PLL3_CON1 (0x002c) 76 #define PLL4H_PLL4_CON1 (0x003c) 77 #define PLL4HPLL_FHCTL_HP_EN (0x0e00) 78 #define PLL4HPLL_FHCTL_CLK_CON (0x0e08) 79 #define PLL4HPLL_FHCTL_RST_CON (0x0e0c) 80 #define PLL4HPLL_FHCTL0_CFG (0x0e3c) 81 #define PLL4HPLL_FHCTL0_DDS (0x0e44) 82 #define PLL4HPLL_FHCTL1_CFG (0x0e50) 83 #define PLL4HPLL_FHCTL1_DDS (0x0e58) 84 #define PLL4HPLL_FHCTL2_CFG (0x0e64) 85 #define PLL4HPLL_FHCTL2_DDS (0x0e6c) 86 #define PLL4HPLL_FHCTL3_CFG (0x0e78) 87 #define PLL4HPLL_FHCTL3_DDS (0x0e80) 88 89 /* PLL control */ 90 #define PLL4H_PLL_HP_EN (0xf) 91 #define PLL4H_PLL_HP_CLKEN (0xf) 92 #define PLL4H_PLL_HP_SWRSTB (0xf) 93 #define FHCTL0_EN BIT(0) 94 #define SFSTR0_EN BIT(2) 95 #define RG_PLL_POSDIV_MASK (0x7) 96 #define RG_PLL_POSDIV_SFT (24) 97 #define FHCTL_PLL_TGL_ORG BIT(31) 98 99 /* ACC offset define */ 100 #define APU_ACC_CONFG_SET0 (0x0000) 101 #define APU_ACC_CONFG_SET1 (0x0004) 102 #define APU_ACC_CONFG_SET2 (0x0008) 103 #define APU_ACC_CONFG_SET3 (0x000c) 104 #define APU_ACC_CONFG_CLR0 (0x0040) 105 #define APU_ACC_CONFG_CLR1 (0x0044) 106 #define APU_ACC_CONFG_CLR2 (0x0048) 107 #define APU_ACC_CONFG_CLR3 (0x004c) 108 #define APU_ACC_CLK_INV_EN_SET (0x00e8) 109 #define APU_ACC_AUTO_CTRL_SET2 (0x0128) 110 #define APU_ACC_AUTO_CTRL_SET3 (0x012c) 111 112 /* ACC control */ 113 #define CGEN_SOC BIT(2) 114 #define HW_CTRL_EN BIT(15) 115 #define CLK_REQ_SW_EN BIT(8) 116 #define CLK_INV_EN (0xaaa8) 117 118 /* ARE offset define */ 119 #define APU_ARE_INI_CTRL (0x0000) 120 #define APU_ARE_GLO_FSM (0x0048) 121 #define APU_ARE_ENTRY0_SRAM_H (0x0c00) 122 #define APU_ARE_ENTRY0_SRAM_L (0x0800) 123 #define APU_ARE_ENTRY1_SRAM_H (0x0c04) 124 #define APU_ARE_ENTRY1_SRAM_L (0x0804) 125 #define APU_ARE_ENTRY2_SRAM_H (0x0c08) 126 #define APU_ARE_ENTRY2_SRAM_L (0x0808) 127 128 /* ARE control */ 129 #define ARE_ENTRY_CFG_H (0x00140000) 130 #define ARE0_ENTRY2_CFG_L (0x004e0804) 131 #define ARE1_ENTRY2_CFG_L (0x004e0806) 132 #define ARE2_ENTRY2_CFG_L (0x004e0807) 133 #define ARE_GLO_FSM_IDLE BIT(0) 134 #define ARE_ENTRY0_SRAM_H_INIT (0x12345678) 135 #define ARE_ENTRY0_SRAM_L_INIT (0x89abcdef) 136 #define ARE_ENTRY1_SRAM_H_INIT (0xfedcba98) 137 #define ARE_ENTRY1_SRAM_L_INIT (0x76543210) 138 #define ARE_CONFG_INI BIT(2) 139 140 /* SPM offset define */ 141 #define APUSYS_BUCK_ISOLATION (0x03ec) 142 143 /* SPM control*/ 144 #define IPU_EXT_BUCK_ISO (0x21) 145 146 /* apu_rcx_ao_ctrl */ 147 #define CSR_DUMMY_0_ADDR (0x0024) 148 149 /* apu_rcx_ao_ctrl control */ 150 #define VCORE_ARE_REQ BIT(2) 151 152 /* PCU offset define */ 153 #define APU_PCU_CTRL_SET (0x0000) 154 #define APU_PCU_BUCK_STEP_SEL (0x0030) 155 #define APU_PCU_BUCK_ON_DAT0_L (0x0080) 156 #define APU_PCU_BUCK_ON_DAT0_H (0x0084) 157 #define APU_PCU_BUCK_ON_DAT1_L (0x0088) 158 #define APU_PCU_BUCK_ON_DAT1_H (0x008c) 159 #define APU_PCU_BUCK_OFF_DAT0_L (0x00a0) 160 #define APU_PCU_BUCK_OFF_DAT0_H (0x00a4) 161 #define APU_PCU_BUCK_OFF_DAT1_L (0x00a8) 162 #define APU_PCU_BUCK_OFF_DAT1_H (0x00ac) 163 #define APU_PCU_BUCK_ON_SLE0 (0x00c0) 164 #define APU_PCU_BUCK_ON_SLE1 (0x00c4) 165 #define APU_PCU_BUCK_ON_SETTLE_TIME (0x012c) 166 167 /* PCU initial data */ 168 #define MT6359P_RG_BUCK_VMODEM_EN_ADDR (0x1688) 169 #define MT6359P_RG_LDO_VSRAM_MD_EN_ADDR (0x1f2e) 170 #define BUCK_VAPU_PMIC_REG_EN_ADDR MT6359P_RG_BUCK_VMODEM_EN_ADDR 171 #define BUCK_VAPU_SRAM_PMIC_REG_EN_ADDR MT6359P_RG_LDO_VSRAM_MD_EN_ADDR 172 173 /* PCU control */ 174 #define AUTO_BUCK_EN BIT(16) 175 #define BUCK_ON_OFF_CMD_EN (0x33) 176 #define BUCK_OFFSET_SFT (16) 177 #define BUCK_ON_CMD (0x1) 178 #define BUCK_OFF_CMD (0x0) 179 #define CMD_OP (0x4) 180 181 /* RPC lite offset define */ 182 #define APU_RPC_SW_TYPE2 (0x0208) 183 #define APU_RPC_SW_TYPE3 (0x020c) 184 #define APU_RPC_SW_TYPE4 (0x0210) 185 #define APU_RPC_SW_TYPE5 (0x0214) 186 #define APU_RPC_SW_TYPE6 (0x0218) 187 #define APU_RPC_SW_TYPE7 (0x021c) 188 #define APU_RPC_SW_TYPE8 (0x0220) 189 #define APU_RPC_SW_TYPE9 (0x0224) 190 191 int apusys_power_init(void); 192 193 #endif /* APUSYS_POWER_H */ 194