1 /* 2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/el3_runtime/context_mgmt.h> 23 #include <lib/el3_runtime/pubsub_events.h> 24 #include <lib/extensions/amu.h> 25 #include <lib/extensions/brbe.h> 26 #include <lib/extensions/mpam.h> 27 #include <lib/extensions/sme.h> 28 #include <lib/extensions/spe.h> 29 #include <lib/extensions/sve.h> 30 #include <lib/extensions/sys_reg_trace.h> 31 #include <lib/extensions/trbe.h> 32 #include <lib/extensions/trf.h> 33 #include <lib/utils.h> 34 35 #if ENABLE_FEAT_TWED 36 /* Make sure delay value fits within the range(0-15) */ 37 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 38 #endif /* ENABLE_FEAT_TWED */ 39 40 static void manage_extensions_secure(cpu_context_t *ctx); 41 42 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 43 { 44 u_register_t sctlr_elx, actlr_elx; 45 46 /* 47 * Initialise SCTLR_EL1 to the reset value corresponding to the target 48 * execution state setting all fields rather than relying on the hw. 49 * Some fields have architecturally UNKNOWN reset values and these are 50 * set to zero. 51 * 52 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 53 * 54 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 55 * required by PSCI specification) 56 */ 57 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 58 if (GET_RW(ep->spsr) == MODE_RW_64) { 59 sctlr_elx |= SCTLR_EL1_RES1; 60 } else { 61 /* 62 * If the target execution state is AArch32 then the following 63 * fields need to be set. 64 * 65 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 66 * instructions are not trapped to EL1. 67 * 68 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 69 * instructions are not trapped to EL1. 70 * 71 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 72 * CP15DMB, CP15DSB, and CP15ISB instructions. 73 */ 74 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 75 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 76 } 77 78 #if ERRATA_A75_764081 79 /* 80 * If workaround of errata 764081 for Cortex-A75 is used then set 81 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 82 */ 83 sctlr_elx |= SCTLR_IESB_BIT; 84 #endif 85 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 86 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 87 88 /* 89 * Base the context ACTLR_EL1 on the current value, as it is 90 * implementation defined. The context restore process will write 91 * the value from the context to the actual register and can cause 92 * problems for processor cores that don't expect certain bits to 93 * be zero. 94 */ 95 actlr_elx = read_actlr_el1(); 96 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 97 } 98 99 /****************************************************************************** 100 * This function performs initializations that are specific to SECURE state 101 * and updates the cpu context specified by 'ctx'. 102 *****************************************************************************/ 103 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 104 { 105 u_register_t scr_el3; 106 el3_state_t *state; 107 108 state = get_el3state_ctx(ctx); 109 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 110 111 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 112 /* 113 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 114 * indicated by the interrupt routing model for BL31. 115 */ 116 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 117 #endif 118 119 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 120 /* Get Memory Tagging Extension support level */ 121 unsigned int mte = get_armv8_5_mte_support(); 122 #endif 123 /* 124 * Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS 125 * is set, or when MTE is only implemented at EL0. 126 */ 127 #if CTX_INCLUDE_MTE_REGS 128 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 129 scr_el3 |= SCR_ATA_BIT; 130 #else 131 if (mte == MTE_IMPLEMENTED_EL0) { 132 scr_el3 |= SCR_ATA_BIT; 133 } 134 #endif /* CTX_INCLUDE_MTE_REGS */ 135 136 /* Enable S-EL2 if the next EL is EL2 and S-EL2 is present */ 137 if ((GET_EL(ep->spsr) == MODE_EL2) && is_feat_sel2_supported()) { 138 if (GET_RW(ep->spsr) != MODE_RW_64) { 139 ERROR("S-EL2 can not be used in AArch32\n."); 140 panic(); 141 } 142 143 scr_el3 |= SCR_EEL2_BIT; 144 } 145 146 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 147 148 /* 149 * Initialize EL1 context registers unless SPMC is running 150 * at S-EL2. 151 */ 152 #if !SPMD_SPM_AT_SEL2 153 setup_el1_context(ctx, ep); 154 #endif 155 156 manage_extensions_secure(ctx); 157 } 158 159 #if ENABLE_RME 160 /****************************************************************************** 161 * This function performs initializations that are specific to REALM state 162 * and updates the cpu context specified by 'ctx'. 163 *****************************************************************************/ 164 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 165 { 166 u_register_t scr_el3; 167 el3_state_t *state; 168 169 state = get_el3state_ctx(ctx); 170 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 171 172 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 173 174 if (is_feat_csv2_2_supported()) { 175 /* Enable access to the SCXTNUM_ELx registers. */ 176 scr_el3 |= SCR_EnSCXT_BIT; 177 } 178 179 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 180 } 181 #endif /* ENABLE_RME */ 182 183 /****************************************************************************** 184 * This function performs initializations that are specific to NON-SECURE state 185 * and updates the cpu context specified by 'ctx'. 186 *****************************************************************************/ 187 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 188 { 189 u_register_t scr_el3; 190 el3_state_t *state; 191 192 state = get_el3state_ctx(ctx); 193 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 194 195 /* SCR_NS: Set the NS bit */ 196 scr_el3 |= SCR_NS_BIT; 197 198 #if !CTX_INCLUDE_PAUTH_REGS 199 /* 200 * If the pointer authentication registers aren't saved during world 201 * switches the value of the registers can be leaked from the Secure to 202 * the Non-secure world. To prevent this, rather than enabling pointer 203 * authentication everywhere, we only enable it in the Non-secure world. 204 * 205 * If the Secure world wants to use pointer authentication, 206 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 207 */ 208 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 209 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 210 211 /* Allow access to Allocation Tags when MTE is implemented. */ 212 scr_el3 |= SCR_ATA_BIT; 213 214 #if HANDLE_EA_EL3_FIRST_NS 215 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 216 scr_el3 |= SCR_EA_BIT; 217 #endif 218 219 #if RAS_TRAP_NS_ERR_REC_ACCESS 220 /* 221 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 222 * and RAS ERX registers from EL1 and EL2(from any security state) 223 * are trapped to EL3. 224 * Set here to trap only for NS EL1/EL2 225 * 226 */ 227 scr_el3 |= SCR_TERR_BIT; 228 #endif 229 230 if (is_feat_csv2_2_supported()) { 231 /* Enable access to the SCXTNUM_ELx registers. */ 232 scr_el3 |= SCR_EnSCXT_BIT; 233 } 234 235 #ifdef IMAGE_BL31 236 /* 237 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 238 * indicated by the interrupt routing model for BL31. 239 */ 240 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 241 #endif 242 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 243 244 /* Initialize EL1 context registers */ 245 setup_el1_context(ctx, ep); 246 247 /* Initialize EL2 context registers */ 248 #if CTX_INCLUDE_EL2_REGS 249 250 /* 251 * Initialize SCTLR_EL2 context register using Endianness value 252 * taken from the entrypoint attribute. 253 */ 254 u_register_t sctlr_el2 = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 255 sctlr_el2 |= SCTLR_EL2_RES1; 256 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2, 257 sctlr_el2); 258 259 /* 260 * Program the ICC_SRE_EL2 to make sure the correct bits are set 261 * when restoring NS context. 262 */ 263 u_register_t icc_sre_el2 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 264 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 265 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_ICC_SRE_EL2, 266 icc_sre_el2); 267 268 /* 269 * Initialize MDCR_EL2.HPMN to its hardware reset value so we don't 270 * throw anyone off who expects this to be sensible. 271 * TODO: A similar thing happens in cm_prepare_el3_exit. They should be 272 * unified with the proper PMU implementation 273 */ 274 u_register_t mdcr_el2 = ((read_pmcr_el0() >> PMCR_EL0_N_SHIFT) & 275 PMCR_EL0_N_MASK); 276 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_MDCR_EL2, mdcr_el2); 277 #endif /* CTX_INCLUDE_EL2_REGS */ 278 } 279 280 /******************************************************************************* 281 * The following function performs initialization of the cpu_context 'ctx' 282 * for first use that is common to all security states, and sets the 283 * initial entrypoint state as specified by the entry_point_info structure. 284 * 285 * The EE and ST attributes are used to configure the endianness and secure 286 * timer availability for the new execution context. 287 ******************************************************************************/ 288 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 289 { 290 u_register_t scr_el3; 291 el3_state_t *state; 292 gp_regs_t *gp_regs; 293 294 /* Clear any residual register values from the context */ 295 zeromem(ctx, sizeof(*ctx)); 296 297 /* 298 * SCR_EL3 was initialised during reset sequence in macro 299 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 300 * affect the next EL. 301 * 302 * The following fields are initially set to zero and then updated to 303 * the required value depending on the state of the SPSR_EL3 and the 304 * Security state and entrypoint attributes of the next EL. 305 */ 306 scr_el3 = read_scr(); 307 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_EA_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 308 SCR_ST_BIT | SCR_HCE_BIT | SCR_NSE_BIT); 309 310 /* 311 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 312 * Exception level as specified by SPSR. 313 */ 314 if (GET_RW(ep->spsr) == MODE_RW_64) { 315 scr_el3 |= SCR_RW_BIT; 316 } 317 318 /* 319 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 320 * Secure timer registers to EL3, from AArch64 state only, if specified 321 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 322 * bit always behaves as 1 (i.e. secure physical timer register access 323 * is not trapped) 324 */ 325 if (EP_GET_ST(ep->h.attr) != 0U) { 326 scr_el3 |= SCR_ST_BIT; 327 } 328 329 /* 330 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 331 * SCR_EL3.HXEn. 332 */ 333 if (is_feat_hcx_supported()) { 334 scr_el3 |= SCR_HXEn_BIT; 335 } 336 337 /* 338 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 339 * registers are trapped to EL3. 340 */ 341 #if ENABLE_FEAT_RNG_TRAP 342 scr_el3 |= SCR_TRNDR_BIT; 343 #endif 344 345 #if FAULT_INJECTION_SUPPORT 346 /* Enable fault injection from lower ELs */ 347 scr_el3 |= SCR_FIEN_BIT; 348 #endif 349 350 /* 351 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 352 */ 353 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 354 scr_el3 |= SCR_TCR2EN_BIT; 355 } 356 357 /* 358 * CPTR_EL3 was initialized out of reset, copy that value to the 359 * context register. 360 */ 361 write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3()); 362 363 /* 364 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 365 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 366 * next mode is Hyp. 367 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 368 * same conditions as HVC instructions and when the processor supports 369 * ARMv8.6-FGT. 370 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 371 * CNTPOFF_EL2 register under the same conditions as HVC instructions 372 * and when the processor supports ECV. 373 */ 374 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 375 || ((GET_RW(ep->spsr) != MODE_RW_64) 376 && (GET_M32(ep->spsr) == MODE32_hyp))) { 377 scr_el3 |= SCR_HCE_BIT; 378 379 if (is_feat_fgt_supported()) { 380 scr_el3 |= SCR_FGTEN_BIT; 381 } 382 383 if (is_feat_ecv_supported()) { 384 scr_el3 |= SCR_ECVEN_BIT; 385 } 386 } 387 388 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 389 if (is_feat_twed_supported()) { 390 /* Set delay in SCR_EL3 */ 391 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 392 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 393 << SCR_TWEDEL_SHIFT); 394 395 /* Enable WFE delay */ 396 scr_el3 |= SCR_TWEDEn_BIT; 397 } 398 399 /* 400 * Populate EL3 state so that we've the right context 401 * before doing ERET 402 */ 403 state = get_el3state_ctx(ctx); 404 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 405 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 406 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 407 408 /* 409 * Store the X0-X7 value from the entrypoint into the context 410 * Use memcpy as we are in control of the layout of the structures 411 */ 412 gp_regs = get_gpregs_ctx(ctx); 413 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 414 } 415 416 /******************************************************************************* 417 * Context management library initialization routine. This library is used by 418 * runtime services to share pointers to 'cpu_context' structures for secure 419 * non-secure and realm states. Management of the structures and their associated 420 * memory is not done by the context management library e.g. the PSCI service 421 * manages the cpu context used for entry from and exit to the non-secure state. 422 * The Secure payload dispatcher service manages the context(s) corresponding to 423 * the secure state. It also uses this library to get access to the non-secure 424 * state cpu context pointers. 425 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 426 * which will be used for programming an entry into a lower EL. The same context 427 * will be used to save state upon exception entry from that EL. 428 ******************************************************************************/ 429 void __init cm_init(void) 430 { 431 /* 432 * The context management library has only global data to intialize, but 433 * that will be done when the BSS is zeroed out. 434 */ 435 } 436 437 /******************************************************************************* 438 * This is the high-level function used to initialize the cpu_context 'ctx' for 439 * first use. It performs initializations that are common to all security states 440 * and initializations specific to the security state specified in 'ep' 441 ******************************************************************************/ 442 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 443 { 444 unsigned int security_state; 445 446 assert(ctx != NULL); 447 448 /* 449 * Perform initializations that are common 450 * to all security states 451 */ 452 setup_context_common(ctx, ep); 453 454 security_state = GET_SECURITY_STATE(ep->h.attr); 455 456 /* Perform security state specific initializations */ 457 switch (security_state) { 458 case SECURE: 459 setup_secure_context(ctx, ep); 460 break; 461 #if ENABLE_RME 462 case REALM: 463 setup_realm_context(ctx, ep); 464 break; 465 #endif 466 case NON_SECURE: 467 setup_ns_context(ctx, ep); 468 break; 469 default: 470 ERROR("Invalid security state\n"); 471 panic(); 472 break; 473 } 474 } 475 476 /******************************************************************************* 477 * Enable architecture extensions on first entry to Non-secure world. 478 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 479 * it is zero. 480 ******************************************************************************/ 481 static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx) 482 { 483 #if IMAGE_BL31 484 if (is_feat_spe_supported()) { 485 spe_enable(el2_unused); 486 } 487 488 if (is_feat_amu_supported()) { 489 amu_enable(el2_unused, ctx); 490 } 491 492 /* Enable SME, SVE, and FPU/SIMD for non-secure world. */ 493 if (is_feat_sme_supported()) { 494 sme_enable(ctx); 495 } else if (is_feat_sve_supported()) { 496 /* Enable SVE and FPU/SIMD for non-secure world. */ 497 sve_enable(ctx); 498 } 499 500 if (is_feat_mpam_supported()) { 501 mpam_enable(el2_unused); 502 } 503 504 if (is_feat_trbe_supported()) { 505 trbe_enable(); 506 } 507 508 if (is_feat_brbe_supported()) { 509 brbe_enable(); 510 } 511 512 if (is_feat_sys_reg_trace_supported()) { 513 sys_reg_trace_enable(ctx); 514 } 515 516 if (is_feat_trf_supported()) { 517 trf_enable(); 518 } 519 #endif 520 } 521 522 /******************************************************************************* 523 * Enable architecture extensions on first entry to Secure world. 524 ******************************************************************************/ 525 static void manage_extensions_secure(cpu_context_t *ctx) 526 { 527 #if IMAGE_BL31 528 529 if (is_feat_sme_supported()) { 530 if (ENABLE_SME_FOR_SWD) { 531 /* 532 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 533 * must ensure SME, SVE, and FPU/SIMD context properly managed. 534 */ 535 sme_enable(ctx); 536 } else { 537 /* 538 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 539 * world can safely use the associated registers. 540 */ 541 sme_disable(ctx); 542 } 543 } else if (is_feat_sve_supported()) { 544 if (ENABLE_SVE_FOR_SWD) { 545 /* 546 * Enable SVE and FPU in secure context, secure manager must 547 * ensure that the SVE and FPU register contexts are properly 548 * managed. 549 */ 550 sve_enable(ctx); 551 } else { 552 /* 553 * Disable SVE and FPU in secure context so non-secure world 554 * can safely use them. 555 */ 556 sve_disable(ctx); 557 } 558 } 559 560 #endif /* IMAGE_BL31 */ 561 } 562 563 /******************************************************************************* 564 * The following function initializes the cpu_context for a CPU specified by 565 * its `cpu_idx` for first use, and sets the initial entrypoint state as 566 * specified by the entry_point_info structure. 567 ******************************************************************************/ 568 void cm_init_context_by_index(unsigned int cpu_idx, 569 const entry_point_info_t *ep) 570 { 571 cpu_context_t *ctx; 572 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 573 cm_setup_context(ctx, ep); 574 } 575 576 /******************************************************************************* 577 * The following function initializes the cpu_context for the current CPU 578 * for first use, and sets the initial entrypoint state as specified by the 579 * entry_point_info structure. 580 ******************************************************************************/ 581 void cm_init_my_context(const entry_point_info_t *ep) 582 { 583 cpu_context_t *ctx; 584 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 585 cm_setup_context(ctx, ep); 586 } 587 588 /******************************************************************************* 589 * Prepare the CPU system registers for first entry into realm, secure, or 590 * normal world. 591 * 592 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 593 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 594 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 595 * For all entries, the EL1 registers are initialized from the cpu_context 596 ******************************************************************************/ 597 void cm_prepare_el3_exit(uint32_t security_state) 598 { 599 u_register_t sctlr_elx, scr_el3, mdcr_el2; 600 cpu_context_t *ctx = cm_get_context(security_state); 601 bool el2_unused = false; 602 uint64_t hcr_el2 = 0U; 603 604 assert(ctx != NULL); 605 606 if (security_state == NON_SECURE) { 607 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 608 CTX_SCR_EL3); 609 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 610 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 611 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 612 CTX_SCTLR_EL1); 613 sctlr_elx &= SCTLR_EE_BIT; 614 sctlr_elx |= SCTLR_EL2_RES1; 615 #if ERRATA_A75_764081 616 /* 617 * If workaround of errata 764081 for Cortex-A75 is used 618 * then set SCTLR_EL2.IESB to enable Implicit Error 619 * Synchronization Barrier. 620 */ 621 sctlr_elx |= SCTLR_IESB_BIT; 622 #endif 623 write_sctlr_el2(sctlr_elx); 624 } else if (el_implemented(2) != EL_IMPL_NONE) { 625 el2_unused = true; 626 627 /* 628 * EL2 present but unused, need to disable safely. 629 * SCTLR_EL2 can be ignored in this case. 630 * 631 * Set EL2 register width appropriately: Set HCR_EL2 632 * field to match SCR_EL3.RW. 633 */ 634 if ((scr_el3 & SCR_RW_BIT) != 0U) 635 hcr_el2 |= HCR_RW_BIT; 636 637 /* 638 * For Armv8.3 pointer authentication feature, disable 639 * traps to EL2 when accessing key registers or using 640 * pointer authentication instructions from lower ELs. 641 */ 642 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 643 644 write_hcr_el2(hcr_el2); 645 646 /* 647 * Initialise CPTR_EL2 setting all fields rather than 648 * relying on the hw. All fields have architecturally 649 * UNKNOWN reset values. 650 * 651 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 652 * accesses to the CPACR_EL1 or CPACR from both 653 * Execution states do not trap to EL2. 654 * 655 * CPTR_EL2.TTA: Set to zero so that Non-secure System 656 * register accesses to the trace registers from both 657 * Execution states do not trap to EL2. 658 * If PE trace unit System registers are not implemented 659 * then this bit is reserved, and must be set to zero. 660 * 661 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 662 * to SIMD and floating-point functionality from both 663 * Execution states do not trap to EL2. 664 */ 665 write_cptr_el2(CPTR_EL2_RESET_VAL & 666 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 667 | CPTR_EL2_TFP_BIT)); 668 669 /* 670 * Initialise CNTHCTL_EL2. All fields are 671 * architecturally UNKNOWN on reset and are set to zero 672 * except for field(s) listed below. 673 * 674 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to 675 * Hyp mode of Non-secure EL0 and EL1 accesses to the 676 * physical timer registers. 677 * 678 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 679 * Hyp mode of Non-secure EL0 and EL1 accesses to the 680 * physical counter registers. 681 */ 682 write_cnthctl_el2(CNTHCTL_RESET_VAL | 683 EL1PCEN_BIT | EL1PCTEN_BIT); 684 685 /* 686 * Initialise CNTVOFF_EL2 to zero as it resets to an 687 * architecturally UNKNOWN value. 688 */ 689 write_cntvoff_el2(0); 690 691 /* 692 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 693 * MPIDR_EL1 respectively. 694 */ 695 write_vpidr_el2(read_midr_el1()); 696 write_vmpidr_el2(read_mpidr_el1()); 697 698 /* 699 * Initialise VTTBR_EL2. All fields are architecturally 700 * UNKNOWN on reset. 701 * 702 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 703 * 2 address translation is disabled, cache maintenance 704 * operations depend on the VMID. 705 * 706 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 707 * translation is disabled. 708 */ 709 write_vttbr_el2(VTTBR_RESET_VAL & 710 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 711 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 712 713 /* 714 * Initialise MDCR_EL2, setting all fields rather than 715 * relying on hw. Some fields are architecturally 716 * UNKNOWN on reset. 717 * 718 * MDCR_EL2.HLP: Set to one so that event counter 719 * overflow, that is recorded in PMOVSCLR_EL0[0-30], 720 * occurs on the increment that changes 721 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is 722 * implemented. This bit is RES0 in versions of the 723 * architecture earlier than ARMv8.5, setting it to 1 724 * doesn't have any effect on them. 725 * 726 * MDCR_EL2.TTRF: Set to zero so that access to Trace 727 * Filter Control register TRFCR_EL1 at EL1 is not 728 * trapped to EL2. This bit is RES0 in versions of 729 * the architecture earlier than ARMv8.4. 730 * 731 * MDCR_EL2.HPMD: Set to one so that event counting is 732 * prohibited at EL2. This bit is RES0 in versions of 733 * the architecture earlier than ARMv8.1, setting it 734 * to 1 doesn't have any effect on them. 735 * 736 * MDCR_EL2.TPMS: Set to zero so that accesses to 737 * Statistical Profiling control registers from EL1 738 * do not trap to EL2. This bit is RES0 when SPE is 739 * not implemented. 740 * 741 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 742 * EL1 System register accesses to the Debug ROM 743 * registers are not trapped to EL2. 744 * 745 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 746 * System register accesses to the powerdown debug 747 * registers are not trapped to EL2. 748 * 749 * MDCR_EL2.TDA: Set to zero so that System register 750 * accesses to the debug registers do not trap to EL2. 751 * 752 * MDCR_EL2.TDE: Set to zero so that debug exceptions 753 * are not routed to EL2. 754 * 755 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 756 * Monitors. 757 * 758 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 759 * EL1 accesses to all Performance Monitors registers 760 * are not trapped to EL2. 761 * 762 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 763 * and EL1 accesses to the PMCR_EL0 or PMCR are not 764 * trapped to EL2. 765 * 766 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 767 * architecturally-defined reset value. 768 * 769 * MDCR_EL2.E2TB: Set to zero so that the trace Buffer 770 * owning exception level is NS-EL1 and, tracing is 771 * prohibited at NS-EL2. These bits are RES0 when 772 * FEAT_TRBE is not implemented. 773 */ 774 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | 775 MDCR_EL2_HPMD) | 776 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 777 >> PMCR_EL0_N_SHIFT)) & 778 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | 779 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | 780 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | 781 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | 782 MDCR_EL2_TPMCR_BIT | 783 MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1)); 784 785 write_mdcr_el2(mdcr_el2); 786 787 /* 788 * Initialise HSTR_EL2. All fields are architecturally 789 * UNKNOWN on reset. 790 * 791 * HSTR_EL2.T<n>: Set all these fields to zero so that 792 * Non-secure EL0 or EL1 accesses to System registers 793 * do not trap to EL2. 794 */ 795 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 796 /* 797 * Initialise CNTHP_CTL_EL2. All fields are 798 * architecturally UNKNOWN on reset. 799 * 800 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 801 * physical timer and prevent timer interrupts. 802 */ 803 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 804 ~(CNTHP_CTL_ENABLE_BIT)); 805 } 806 manage_extensions_nonsecure(el2_unused, ctx); 807 } 808 809 cm_el1_sysregs_context_restore(security_state); 810 cm_set_next_eret_context(security_state); 811 } 812 813 #if CTX_INCLUDE_EL2_REGS 814 815 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 816 { 817 write_ctx_reg(ctx, CTX_HDFGRTR_EL2, read_hdfgrtr_el2()); 818 if (is_feat_amu_supported()) { 819 write_ctx_reg(ctx, CTX_HAFGRTR_EL2, read_hafgrtr_el2()); 820 } 821 write_ctx_reg(ctx, CTX_HDFGWTR_EL2, read_hdfgwtr_el2()); 822 write_ctx_reg(ctx, CTX_HFGITR_EL2, read_hfgitr_el2()); 823 write_ctx_reg(ctx, CTX_HFGRTR_EL2, read_hfgrtr_el2()); 824 write_ctx_reg(ctx, CTX_HFGWTR_EL2, read_hfgwtr_el2()); 825 } 826 827 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 828 { 829 write_hdfgrtr_el2(read_ctx_reg(ctx, CTX_HDFGRTR_EL2)); 830 if (is_feat_amu_supported()) { 831 write_hafgrtr_el2(read_ctx_reg(ctx, CTX_HAFGRTR_EL2)); 832 } 833 write_hdfgwtr_el2(read_ctx_reg(ctx, CTX_HDFGWTR_EL2)); 834 write_hfgitr_el2(read_ctx_reg(ctx, CTX_HFGITR_EL2)); 835 write_hfgrtr_el2(read_ctx_reg(ctx, CTX_HFGRTR_EL2)); 836 write_hfgwtr_el2(read_ctx_reg(ctx, CTX_HFGWTR_EL2)); 837 } 838 839 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 840 { 841 u_register_t mpam_idr = read_mpamidr_el1(); 842 843 write_ctx_reg(ctx, CTX_MPAM2_EL2, read_mpam2_el2()); 844 845 /* 846 * The context registers that we intend to save would be part of the 847 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 848 */ 849 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 850 return; 851 } 852 853 /* 854 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 855 * MPAMIDR_HAS_HCR_BIT == 1. 856 */ 857 write_ctx_reg(ctx, CTX_MPAMHCR_EL2, read_mpamhcr_el2()); 858 write_ctx_reg(ctx, CTX_MPAMVPM0_EL2, read_mpamvpm0_el2()); 859 write_ctx_reg(ctx, CTX_MPAMVPMV_EL2, read_mpamvpmv_el2()); 860 861 /* 862 * The number of MPAMVPM registers is implementation defined, their 863 * number is stored in the MPAMIDR_EL1 register. 864 */ 865 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 866 case 7: 867 write_ctx_reg(ctx, CTX_MPAMVPM7_EL2, read_mpamvpm7_el2()); 868 __fallthrough; 869 case 6: 870 write_ctx_reg(ctx, CTX_MPAMVPM6_EL2, read_mpamvpm6_el2()); 871 __fallthrough; 872 case 5: 873 write_ctx_reg(ctx, CTX_MPAMVPM5_EL2, read_mpamvpm5_el2()); 874 __fallthrough; 875 case 4: 876 write_ctx_reg(ctx, CTX_MPAMVPM4_EL2, read_mpamvpm4_el2()); 877 __fallthrough; 878 case 3: 879 write_ctx_reg(ctx, CTX_MPAMVPM3_EL2, read_mpamvpm3_el2()); 880 __fallthrough; 881 case 2: 882 write_ctx_reg(ctx, CTX_MPAMVPM2_EL2, read_mpamvpm2_el2()); 883 __fallthrough; 884 case 1: 885 write_ctx_reg(ctx, CTX_MPAMVPM1_EL2, read_mpamvpm1_el2()); 886 break; 887 } 888 } 889 890 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 891 { 892 u_register_t mpam_idr = read_mpamidr_el1(); 893 894 write_mpam2_el2(read_ctx_reg(ctx, CTX_MPAM2_EL2)); 895 896 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 897 return; 898 } 899 900 write_mpamhcr_el2(read_ctx_reg(ctx, CTX_MPAMHCR_EL2)); 901 write_mpamvpm0_el2(read_ctx_reg(ctx, CTX_MPAMVPM0_EL2)); 902 write_mpamvpmv_el2(read_ctx_reg(ctx, CTX_MPAMVPMV_EL2)); 903 904 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 905 case 7: 906 write_mpamvpm7_el2(read_ctx_reg(ctx, CTX_MPAMVPM7_EL2)); 907 __fallthrough; 908 case 6: 909 write_mpamvpm6_el2(read_ctx_reg(ctx, CTX_MPAMVPM6_EL2)); 910 __fallthrough; 911 case 5: 912 write_mpamvpm5_el2(read_ctx_reg(ctx, CTX_MPAMVPM5_EL2)); 913 __fallthrough; 914 case 4: 915 write_mpamvpm4_el2(read_ctx_reg(ctx, CTX_MPAMVPM4_EL2)); 916 __fallthrough; 917 case 3: 918 write_mpamvpm3_el2(read_ctx_reg(ctx, CTX_MPAMVPM3_EL2)); 919 __fallthrough; 920 case 2: 921 write_mpamvpm2_el2(read_ctx_reg(ctx, CTX_MPAMVPM2_EL2)); 922 __fallthrough; 923 case 1: 924 write_mpamvpm1_el2(read_ctx_reg(ctx, CTX_MPAMVPM1_EL2)); 925 break; 926 } 927 } 928 929 /******************************************************************************* 930 * Save EL2 sysreg context 931 ******************************************************************************/ 932 void cm_el2_sysregs_context_save(uint32_t security_state) 933 { 934 u_register_t scr_el3 = read_scr(); 935 936 /* 937 * Always save the non-secure and realm EL2 context, only save the 938 * S-EL2 context if S-EL2 is enabled. 939 */ 940 if ((security_state != SECURE) || 941 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 942 cpu_context_t *ctx; 943 el2_sysregs_t *el2_sysregs_ctx; 944 945 ctx = cm_get_context(security_state); 946 assert(ctx != NULL); 947 948 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 949 950 el2_sysregs_context_save_common(el2_sysregs_ctx); 951 #if CTX_INCLUDE_MTE_REGS 952 el2_sysregs_context_save_mte(el2_sysregs_ctx); 953 #endif 954 if (is_feat_mpam_supported()) { 955 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 956 } 957 958 if (is_feat_fgt_supported()) { 959 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 960 } 961 962 if (is_feat_ecv_v2_supported()) { 963 write_ctx_reg(el2_sysregs_ctx, CTX_CNTPOFF_EL2, 964 read_cntpoff_el2()); 965 } 966 967 if (is_feat_vhe_supported()) { 968 write_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2, 969 read_contextidr_el2()); 970 write_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2, 971 read_ttbr1_el2()); 972 } 973 #if RAS_EXTENSION 974 el2_sysregs_context_save_ras(el2_sysregs_ctx); 975 #endif 976 977 if (is_feat_nv2_supported()) { 978 write_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2, 979 read_vncr_el2()); 980 } 981 982 if (is_feat_trf_supported()) { 983 write_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2, read_trfcr_el2()); 984 } 985 986 if (is_feat_csv2_2_supported()) { 987 write_ctx_reg(el2_sysregs_ctx, CTX_SCXTNUM_EL2, 988 read_scxtnum_el2()); 989 } 990 991 if (is_feat_hcx_supported()) { 992 write_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2, read_hcrx_el2()); 993 } 994 if (is_feat_tcr2_supported()) { 995 write_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2, read_tcr2_el2()); 996 } 997 } 998 } 999 1000 /******************************************************************************* 1001 * Restore EL2 sysreg context 1002 ******************************************************************************/ 1003 void cm_el2_sysregs_context_restore(uint32_t security_state) 1004 { 1005 u_register_t scr_el3 = read_scr(); 1006 1007 /* 1008 * Always restore the non-secure and realm EL2 context, only restore the 1009 * S-EL2 context if S-EL2 is enabled. 1010 */ 1011 if ((security_state != SECURE) || 1012 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 1013 cpu_context_t *ctx; 1014 el2_sysregs_t *el2_sysregs_ctx; 1015 1016 ctx = cm_get_context(security_state); 1017 assert(ctx != NULL); 1018 1019 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1020 1021 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1022 #if CTX_INCLUDE_MTE_REGS 1023 el2_sysregs_context_restore_mte(el2_sysregs_ctx); 1024 #endif 1025 if (is_feat_mpam_supported()) { 1026 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1027 } 1028 1029 if (is_feat_fgt_supported()) { 1030 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1031 } 1032 1033 if (is_feat_ecv_v2_supported()) { 1034 write_cntpoff_el2(read_ctx_reg(el2_sysregs_ctx, 1035 CTX_CNTPOFF_EL2)); 1036 } 1037 1038 if (is_feat_vhe_supported()) { 1039 write_contextidr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2)); 1040 write_ttbr1_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2)); 1041 } 1042 #if RAS_EXTENSION 1043 el2_sysregs_context_restore_ras(el2_sysregs_ctx); 1044 #endif 1045 1046 if (is_feat_nv2_supported()) { 1047 write_vncr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2)); 1048 } 1049 if (is_feat_trf_supported()) { 1050 write_trfcr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2)); 1051 } 1052 1053 if (is_feat_csv2_2_supported()) { 1054 write_scxtnum_el2(read_ctx_reg(el2_sysregs_ctx, 1055 CTX_SCXTNUM_EL2)); 1056 } 1057 1058 if (is_feat_hcx_supported()) { 1059 write_hcrx_el2(read_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2)); 1060 } 1061 if (is_feat_tcr2_supported()) { 1062 write_tcr2_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2)); 1063 } 1064 } 1065 } 1066 #endif /* CTX_INCLUDE_EL2_REGS */ 1067 1068 /******************************************************************************* 1069 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1070 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1071 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1072 * cm_prepare_el3_exit function. 1073 ******************************************************************************/ 1074 void cm_prepare_el3_exit_ns(void) 1075 { 1076 #if CTX_INCLUDE_EL2_REGS 1077 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1078 assert(ctx != NULL); 1079 1080 /* Assert that EL2 is used. */ 1081 #if ENABLE_ASSERTIONS 1082 el3_state_t *state = get_el3state_ctx(ctx); 1083 u_register_t scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1084 #endif 1085 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1086 (el_implemented(2U) != EL_IMPL_NONE)); 1087 1088 /* 1089 * Currently some extensions are configured using 1090 * direct register updates. Therefore, do this here 1091 * instead of when setting up context. 1092 */ 1093 manage_extensions_nonsecure(0, ctx); 1094 1095 /* 1096 * Set the NS bit to be able to access the ICC_SRE_EL2 1097 * register when restoring context. 1098 */ 1099 write_scr_el3(read_scr_el3() | SCR_NS_BIT); 1100 1101 /* 1102 * Ensure the NS bit change is committed before the EL2/EL1 1103 * state restoration. 1104 */ 1105 isb(); 1106 1107 /* Restore EL2 and EL1 sysreg contexts */ 1108 cm_el2_sysregs_context_restore(NON_SECURE); 1109 cm_el1_sysregs_context_restore(NON_SECURE); 1110 cm_set_next_eret_context(NON_SECURE); 1111 #else 1112 cm_prepare_el3_exit(NON_SECURE); 1113 #endif /* CTX_INCLUDE_EL2_REGS */ 1114 } 1115 1116 /******************************************************************************* 1117 * The next four functions are used by runtime services to save and restore 1118 * EL1 context on the 'cpu_context' structure for the specified security 1119 * state. 1120 ******************************************************************************/ 1121 void cm_el1_sysregs_context_save(uint32_t security_state) 1122 { 1123 cpu_context_t *ctx; 1124 1125 ctx = cm_get_context(security_state); 1126 assert(ctx != NULL); 1127 1128 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1129 1130 #if IMAGE_BL31 1131 if (security_state == SECURE) 1132 PUBLISH_EVENT(cm_exited_secure_world); 1133 else 1134 PUBLISH_EVENT(cm_exited_normal_world); 1135 #endif 1136 } 1137 1138 void cm_el1_sysregs_context_restore(uint32_t security_state) 1139 { 1140 cpu_context_t *ctx; 1141 1142 ctx = cm_get_context(security_state); 1143 assert(ctx != NULL); 1144 1145 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1146 1147 #if IMAGE_BL31 1148 if (security_state == SECURE) 1149 PUBLISH_EVENT(cm_entering_secure_world); 1150 else 1151 PUBLISH_EVENT(cm_entering_normal_world); 1152 #endif 1153 } 1154 1155 /******************************************************************************* 1156 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1157 * given security state with the given entrypoint 1158 ******************************************************************************/ 1159 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1160 { 1161 cpu_context_t *ctx; 1162 el3_state_t *state; 1163 1164 ctx = cm_get_context(security_state); 1165 assert(ctx != NULL); 1166 1167 /* Populate EL3 state so that ERET jumps to the correct entry */ 1168 state = get_el3state_ctx(ctx); 1169 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1170 } 1171 1172 /******************************************************************************* 1173 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1174 * pertaining to the given security state 1175 ******************************************************************************/ 1176 void cm_set_elr_spsr_el3(uint32_t security_state, 1177 uintptr_t entrypoint, uint32_t spsr) 1178 { 1179 cpu_context_t *ctx; 1180 el3_state_t *state; 1181 1182 ctx = cm_get_context(security_state); 1183 assert(ctx != NULL); 1184 1185 /* Populate EL3 state so that ERET jumps to the correct entry */ 1186 state = get_el3state_ctx(ctx); 1187 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1188 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1189 } 1190 1191 /******************************************************************************* 1192 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1193 * pertaining to the given security state using the value and bit position 1194 * specified in the parameters. It preserves all other bits. 1195 ******************************************************************************/ 1196 void cm_write_scr_el3_bit(uint32_t security_state, 1197 uint32_t bit_pos, 1198 uint32_t value) 1199 { 1200 cpu_context_t *ctx; 1201 el3_state_t *state; 1202 u_register_t scr_el3; 1203 1204 ctx = cm_get_context(security_state); 1205 assert(ctx != NULL); 1206 1207 /* Ensure that the bit position is a valid one */ 1208 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1209 1210 /* Ensure that the 'value' is only a bit wide */ 1211 assert(value <= 1U); 1212 1213 /* 1214 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1215 * and set it to its new value. 1216 */ 1217 state = get_el3state_ctx(ctx); 1218 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1219 scr_el3 &= ~(1UL << bit_pos); 1220 scr_el3 |= (u_register_t)value << bit_pos; 1221 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1222 } 1223 1224 /******************************************************************************* 1225 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1226 * given security state. 1227 ******************************************************************************/ 1228 u_register_t cm_get_scr_el3(uint32_t security_state) 1229 { 1230 cpu_context_t *ctx; 1231 el3_state_t *state; 1232 1233 ctx = cm_get_context(security_state); 1234 assert(ctx != NULL); 1235 1236 /* Populate EL3 state so that ERET jumps to the correct entry */ 1237 state = get_el3state_ctx(ctx); 1238 return read_ctx_reg(state, CTX_SCR_EL3); 1239 } 1240 1241 /******************************************************************************* 1242 * This function is used to program the context that's used for exception 1243 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1244 * the required security state 1245 ******************************************************************************/ 1246 void cm_set_next_eret_context(uint32_t security_state) 1247 { 1248 cpu_context_t *ctx; 1249 1250 ctx = cm_get_context(security_state); 1251 assert(ctx != NULL); 1252 1253 cm_set_next_context(ctx); 1254 } 1255