1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch_def.h> 11 12 #define PLAT_PRIMARY_CPU (0x0) 13 14 #define MT_GIC_BASE (0x0C000000) 15 #define MCUCFG_BASE (0x0C530000) 16 #define MCUCFG_REG_SIZE (0x10000) 17 #define IO_PHYS (0x10000000) 18 19 /* Aggregate of all devices for MMU mapping */ 20 #define MTK_DEV_RNG0_BASE (MT_GIC_BASE) 21 #define MTK_DEV_RNG0_SIZE (0x600000) 22 #define MTK_DEV_RNG1_BASE (IO_PHYS) 23 #define MTK_DEV_RNG1_SIZE (0x10000000) 24 25 #define TOPCKGEN_BASE (IO_PHYS) 26 27 /******************************************************************************* 28 * GPIO related constants 29 ******************************************************************************/ 30 #define GPIO_BASE (IO_PHYS + 0x00005000) 31 #define IOCFG_LM_BASE (IO_PHYS + 0x01B50000) 32 #define IOCFG_RB0_BASE (IO_PHYS + 0x01C50000) 33 #define IOCFG_RB1_BASE (IO_PHYS + 0x01C60000) 34 #define IOCFG_BM0_BASE (IO_PHYS + 0x01D20000) 35 #define IOCFG_BM1_BASE (IO_PHYS + 0x01D30000) 36 #define IOCFG_BM2_BASE (IO_PHYS + 0x01D40000) 37 #define IOCFG_LT0_BASE (IO_PHYS + 0x01E20000) 38 #define IOCFG_LT1_BASE (IO_PHYS + 0x01E30000) 39 #define IOCFG_RT_BASE (IO_PHYS + 0x01F20000) 40 41 /******************************************************************************* 42 * UART related constants 43 ******************************************************************************/ 44 #define UART0_BASE (IO_PHYS + 0x01002000) 45 #define UART_BAUDRATE (115200) 46 47 /******************************************************************************* 48 * CIRQ related constants 49 ******************************************************************************/ 50 #define SYS_CIRQ_BASE (IO_PHYS + 204000) 51 #define MD_WDT_IRQ_BIT_ID (519) 52 #define CIRQ_REG_NUM (19) 53 #define CIRQ_SPI_START (128) 54 #define CIRQ_IRQ_NUM (598) 55 56 /******************************************************************************* 57 * System counter frequency related constants 58 ******************************************************************************/ 59 #define SYS_COUNTER_FREQ_IN_HZ (13000000) 60 #define SYS_COUNTER_FREQ_IN_MHZ (13) 61 62 /******************************************************************************* 63 * Platform binary types for linking 64 ******************************************************************************/ 65 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 66 #define PLATFORM_LINKER_ARCH aarch64 67 68 /******************************************************************************* 69 * Generic platform constants 70 ******************************************************************************/ 71 #define PLATFORM_STACK_SIZE (0x800) 72 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 73 #define SOC_CHIP_ID U(0x8189) 74 75 /******************************************************************************* 76 * Platform memory map related constants 77 ******************************************************************************/ 78 #define TZRAM_BASE (0x54600000) 79 #define TZRAM_SIZE (0x00200000) 80 81 /******************************************************************************* 82 * BL31 specific defines. 83 ******************************************************************************/ 84 /* 85 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 86 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 87 * little space for growth. 88 */ 89 #define BL31_BASE (TZRAM_BASE + 0x1000) 90 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 91 92 /******************************************************************************* 93 * GIC-600 & interrupt handling related constants 94 ******************************************************************************/ 95 /* Base MTK_platform compatible GIC memory map */ 96 #define BASE_GICD_BASE (MT_GIC_BASE) 97 #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 98 #define DEV_IRQ_ID 300 99 100 #define PLAT_MTK_G1S_IRQ_PROPS(grp) \ 101 INTR_PROP_DESC(DEV_IRQ_ID, GIC_HIGHEST_SEC_PRIORITY, grp, \ 102 GIC_INTR_CFG_LEVEL) 103 104 /******************************************************************************* 105 * Platform specific page table and MMU setup constants 106 ******************************************************************************/ 107 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 108 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 109 #define MAX_XLAT_TABLES (16) 110 #define MAX_MMAP_REGIONS (16) 111 112 /******************************************************************************* 113 * SYSTIMER related definitions 114 ******************************************************************************/ 115 #define SYSTIMER_BASE (IO_PHYS + 0x0CC10000) 116 117 #endif /* PLATFORM_DEF_H */ 118