1 /* 2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/debug.h> 9 #include <common/runtime_svc.h> 10 #include <lib/mmio.h> 11 #include <tools_share/uuid.h> 12 13 #include "socfpga_fcs.h" 14 #include "socfpga_mailbox.h" 15 #include "socfpga_reset_manager.h" 16 #include "socfpga_sip_svc.h" 17 18 19 /* Total buffer the driver can hold */ 20 #define FPGA_CONFIG_BUFFER_SIZE 4 21 22 static int current_block, current_buffer; 23 static int read_block, max_blocks; 24 static uint32_t send_id, rcv_id; 25 static uint32_t bytes_per_block, blocks_submitted; 26 static bool bridge_disable; 27 28 /* RSU static variables */ 29 static uint32_t rsu_dcmf_ver[4] = {0}; 30 31 /* RSU Max Retry */ 32 static uint32_t rsu_max_retry; 33 static uint16_t rsu_dcmf_stat[4] = {0}; 34 35 /* SiP Service UUID */ 36 DEFINE_SVC_UUID2(intl_svc_uid, 37 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 38 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 39 40 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 41 uint64_t x1, 42 uint64_t x2, 43 uint64_t x3, 44 uint64_t x4, 45 void *cookie, 46 void *handle, 47 uint64_t flags) 48 { 49 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 50 SMC_RET1(handle, SMC_UNK); 51 } 52 53 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 54 55 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 56 { 57 uint32_t args[3]; 58 59 while (max_blocks > 0 && buffer->size > buffer->size_written) { 60 args[0] = (1<<8); 61 args[1] = buffer->addr + buffer->size_written; 62 if (buffer->size - buffer->size_written <= bytes_per_block) { 63 args[2] = buffer->size - buffer->size_written; 64 current_buffer++; 65 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 66 } else { 67 args[2] = bytes_per_block; 68 } 69 70 buffer->size_written += args[2]; 71 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 72 3U, CMD_INDIRECT); 73 74 buffer->subblocks_sent++; 75 max_blocks--; 76 } 77 78 return !max_blocks; 79 } 80 81 static int intel_fpga_sdm_write_all(void) 82 { 83 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 84 if (intel_fpga_sdm_write_buffer( 85 &fpga_config_buffers[current_buffer])) { 86 break; 87 } 88 } 89 return 0; 90 } 91 92 static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type) 93 { 94 uint32_t ret; 95 96 if (query_type == 1U) { 97 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, false); 98 } else { 99 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, true); 100 } 101 102 if (ret != 0U) { 103 if (ret == MBOX_CFGSTAT_STATE_CONFIG) { 104 return INTEL_SIP_SMC_STATUS_BUSY; 105 } else { 106 return INTEL_SIP_SMC_STATUS_ERROR; 107 } 108 } 109 110 if (bridge_disable) { 111 socfpga_bridges_enable(~0); /* Enable bridge */ 112 bridge_disable = false; 113 } 114 115 return INTEL_SIP_SMC_STATUS_OK; 116 } 117 118 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 119 { 120 int i; 121 122 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 123 if (fpga_config_buffers[i].block_number == current_block) { 124 fpga_config_buffers[i].subblocks_sent--; 125 if (fpga_config_buffers[i].subblocks_sent == 0 126 && fpga_config_buffers[i].size <= 127 fpga_config_buffers[i].size_written) { 128 fpga_config_buffers[i].write_requested = 0; 129 current_block++; 130 *buffer_addr_completed = 131 fpga_config_buffers[i].addr; 132 return 0; 133 } 134 } 135 } 136 137 return -1; 138 } 139 140 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 141 uint32_t *count, uint32_t *job_id) 142 { 143 uint32_t resp[5]; 144 unsigned int resp_len = ARRAY_SIZE(resp); 145 int status = INTEL_SIP_SMC_STATUS_OK; 146 int all_completed = 1; 147 *count = 0; 148 149 while (*count < 3) { 150 151 status = mailbox_read_response(job_id, 152 resp, &resp_len); 153 154 if (status < 0) { 155 break; 156 } 157 158 max_blocks++; 159 160 if (mark_last_buffer_xfer_completed( 161 &completed_addr[*count]) == 0) { 162 *count = *count + 1; 163 } else { 164 break; 165 } 166 } 167 168 if (*count <= 0) { 169 if (status != MBOX_NO_RESPONSE && 170 status != MBOX_TIMEOUT && resp_len != 0) { 171 mailbox_clear_response(); 172 return INTEL_SIP_SMC_STATUS_ERROR; 173 } 174 175 *count = 0; 176 } 177 178 intel_fpga_sdm_write_all(); 179 180 if (*count > 0) { 181 status = INTEL_SIP_SMC_STATUS_OK; 182 } else if (*count == 0) { 183 status = INTEL_SIP_SMC_STATUS_BUSY; 184 } 185 186 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 187 if (fpga_config_buffers[i].write_requested != 0) { 188 all_completed = 0; 189 break; 190 } 191 } 192 193 if (all_completed == 1) { 194 return INTEL_SIP_SMC_STATUS_OK; 195 } 196 197 return status; 198 } 199 200 static int intel_fpga_config_start(uint32_t flag) 201 { 202 uint32_t argument = 0x1; 203 uint32_t response[3]; 204 int status = 0; 205 unsigned int size = 0; 206 unsigned int resp_len = ARRAY_SIZE(response); 207 208 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) { 209 bridge_disable = true; 210 } 211 212 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) { 213 size = 1; 214 bridge_disable = false; 215 } 216 217 mailbox_clear_response(); 218 219 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 220 CMD_CASUAL, NULL, NULL); 221 222 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 223 CMD_CASUAL, response, &resp_len); 224 225 if (status < 0) { 226 bridge_disable = false; 227 return INTEL_SIP_SMC_STATUS_ERROR; 228 } 229 230 max_blocks = response[0]; 231 bytes_per_block = response[1]; 232 233 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 234 fpga_config_buffers[i].size = 0; 235 fpga_config_buffers[i].size_written = 0; 236 fpga_config_buffers[i].addr = 0; 237 fpga_config_buffers[i].write_requested = 0; 238 fpga_config_buffers[i].block_number = 0; 239 fpga_config_buffers[i].subblocks_sent = 0; 240 } 241 242 blocks_submitted = 0; 243 current_block = 0; 244 read_block = 0; 245 current_buffer = 0; 246 247 /* Disable bridge on full reconfiguration */ 248 if (bridge_disable) { 249 socfpga_bridges_disable(~0); 250 } 251 252 return INTEL_SIP_SMC_STATUS_OK; 253 } 254 255 static bool is_fpga_config_buffer_full(void) 256 { 257 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 258 if (!fpga_config_buffers[i].write_requested) { 259 return false; 260 } 261 } 262 return true; 263 } 264 265 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 266 { 267 if (!addr && !size) { 268 return true; 269 } 270 if (size > (UINT64_MAX - addr)) { 271 return false; 272 } 273 if (addr < BL31_LIMIT) { 274 return false; 275 } 276 if (addr + size > DRAM_BASE + DRAM_SIZE) { 277 return false; 278 } 279 280 return true; 281 } 282 283 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 284 { 285 int i; 286 287 intel_fpga_sdm_write_all(); 288 289 if (!is_address_in_ddr_range(mem, size) || 290 is_fpga_config_buffer_full()) { 291 return INTEL_SIP_SMC_STATUS_REJECTED; 292 } 293 294 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 295 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 296 297 if (!fpga_config_buffers[j].write_requested) { 298 fpga_config_buffers[j].addr = mem; 299 fpga_config_buffers[j].size = size; 300 fpga_config_buffers[j].size_written = 0; 301 fpga_config_buffers[j].write_requested = 1; 302 fpga_config_buffers[j].block_number = 303 blocks_submitted++; 304 fpga_config_buffers[j].subblocks_sent = 0; 305 break; 306 } 307 } 308 309 if (is_fpga_config_buffer_full()) { 310 return INTEL_SIP_SMC_STATUS_BUSY; 311 } 312 313 return INTEL_SIP_SMC_STATUS_OK; 314 } 315 316 static int is_out_of_sec_range(uint64_t reg_addr) 317 { 318 #if DEBUG 319 return 0; 320 #endif 321 322 switch (reg_addr) { 323 case(0xF8011100): /* ECCCTRL1 */ 324 case(0xF8011104): /* ECCCTRL2 */ 325 case(0xF8011110): /* ERRINTEN */ 326 case(0xF8011114): /* ERRINTENS */ 327 case(0xF8011118): /* ERRINTENR */ 328 case(0xF801111C): /* INTMODE */ 329 case(0xF8011120): /* INTSTAT */ 330 case(0xF8011124): /* DIAGINTTEST */ 331 case(0xF801112C): /* DERRADDRA */ 332 case(0xFFD12028): /* SDMMCGRP_CTRL */ 333 case(0xFFD12044): /* EMAC0 */ 334 case(0xFFD12048): /* EMAC1 */ 335 case(0xFFD1204C): /* EMAC2 */ 336 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 337 case(0xFFD12094): /* ECC_INT_MASK_SET */ 338 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 339 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 340 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 341 case(0xFFD120C0): /* NOC_TIMEOUT */ 342 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 343 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 344 case(0xFFD120D0): /* NOC_IDLEACK */ 345 case(0xFFD120D4): /* NOC_IDLESTATUS */ 346 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 347 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 348 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 349 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 350 return 0; 351 352 default: 353 break; 354 } 355 356 return -1; 357 } 358 359 /* Secure register access */ 360 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 361 { 362 if (is_out_of_sec_range(reg_addr)) { 363 return INTEL_SIP_SMC_STATUS_ERROR; 364 } 365 366 *retval = mmio_read_32(reg_addr); 367 368 return INTEL_SIP_SMC_STATUS_OK; 369 } 370 371 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 372 uint32_t *retval) 373 { 374 if (is_out_of_sec_range(reg_addr)) { 375 return INTEL_SIP_SMC_STATUS_ERROR; 376 } 377 378 mmio_write_32(reg_addr, val); 379 380 return intel_secure_reg_read(reg_addr, retval); 381 } 382 383 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 384 uint32_t val, uint32_t *retval) 385 { 386 if (!intel_secure_reg_read(reg_addr, retval)) { 387 *retval &= ~mask; 388 *retval |= val & mask; 389 return intel_secure_reg_write(reg_addr, *retval, retval); 390 } 391 392 return INTEL_SIP_SMC_STATUS_ERROR; 393 } 394 395 /* Intel Remote System Update (RSU) services */ 396 uint64_t intel_rsu_update_address; 397 398 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 399 { 400 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 401 return INTEL_SIP_SMC_RSU_ERROR; 402 } 403 404 return INTEL_SIP_SMC_STATUS_OK; 405 } 406 407 static uint32_t intel_rsu_update(uint64_t update_address) 408 { 409 intel_rsu_update_address = update_address; 410 return INTEL_SIP_SMC_STATUS_OK; 411 } 412 413 static uint32_t intel_rsu_notify(uint32_t execution_stage) 414 { 415 if (mailbox_hps_stage_notify(execution_stage) < 0) { 416 return INTEL_SIP_SMC_RSU_ERROR; 417 } 418 419 return INTEL_SIP_SMC_STATUS_OK; 420 } 421 422 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 423 uint32_t *ret_stat) 424 { 425 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 426 return INTEL_SIP_SMC_RSU_ERROR; 427 } 428 429 *ret_stat = respbuf[8]; 430 return INTEL_SIP_SMC_STATUS_OK; 431 } 432 433 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 434 uint64_t dcmf_ver_3_2) 435 { 436 rsu_dcmf_ver[0] = dcmf_ver_1_0; 437 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 438 rsu_dcmf_ver[2] = dcmf_ver_3_2; 439 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 440 441 return INTEL_SIP_SMC_STATUS_OK; 442 } 443 444 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) 445 { 446 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); 447 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); 448 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); 449 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); 450 451 return INTEL_SIP_SMC_STATUS_OK; 452 } 453 454 /* Intel HWMON services */ 455 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval) 456 { 457 if (chan > TEMP_CHANNEL_MAX) { 458 return INTEL_SIP_SMC_STATUS_ERROR; 459 } 460 461 if (mailbox_hwmon_readtemp(chan, retval) < 0) { 462 return INTEL_SIP_SMC_STATUS_ERROR; 463 } 464 465 return INTEL_SIP_SMC_STATUS_OK; 466 } 467 468 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval) 469 { 470 if (chan > VOLT_CHANNEL_MAX) { 471 return INTEL_SIP_SMC_STATUS_ERROR; 472 } 473 474 if (mailbox_hwmon_readvolt(chan, retval) < 0) { 475 return INTEL_SIP_SMC_STATUS_ERROR; 476 } 477 478 return INTEL_SIP_SMC_STATUS_OK; 479 } 480 481 /* Mailbox services */ 482 static uint32_t intel_smc_fw_version(uint32_t *fw_version) 483 { 484 int status; 485 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE; 486 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U}; 487 488 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U, 489 CMD_CASUAL, resp_data, &resp_len); 490 491 if (status < 0) { 492 return INTEL_SIP_SMC_STATUS_ERROR; 493 } 494 495 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) { 496 return INTEL_SIP_SMC_STATUS_ERROR; 497 } 498 499 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK; 500 501 return INTEL_SIP_SMC_STATUS_OK; 502 } 503 504 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 505 unsigned int len, uint32_t urgent, uint64_t response, 506 unsigned int resp_len, int *mbox_status, 507 unsigned int *len_in_resp) 508 { 509 *len_in_resp = 0; 510 *mbox_status = GENERIC_RESPONSE_ERROR; 511 512 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) { 513 return INTEL_SIP_SMC_STATUS_REJECTED; 514 } 515 516 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 517 (uint32_t *) response, &resp_len); 518 519 if (status < 0) { 520 *mbox_status = -status; 521 return INTEL_SIP_SMC_STATUS_ERROR; 522 } 523 524 *mbox_status = 0; 525 *len_in_resp = resp_len; 526 527 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE); 528 529 return INTEL_SIP_SMC_STATUS_OK; 530 } 531 532 static int intel_smc_get_usercode(uint32_t *user_code) 533 { 534 int status; 535 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE; 536 537 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL, 538 0U, CMD_CASUAL, user_code, &resp_len); 539 540 if (status < 0) { 541 return INTEL_SIP_SMC_STATUS_ERROR; 542 } 543 544 return INTEL_SIP_SMC_STATUS_OK; 545 } 546 547 uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size, 548 uint32_t mode, uint32_t *job_id, 549 uint32_t *ret_size, uint32_t *mbox_error) 550 { 551 int status = 0; 552 uint32_t resp_len = size / MBOX_WORD_BYTE; 553 554 if (resp_len > MBOX_DATA_MAX_LEN) { 555 return INTEL_SIP_SMC_STATUS_REJECTED; 556 } 557 558 if (!is_address_in_ddr_range(addr, size)) { 559 return INTEL_SIP_SMC_STATUS_REJECTED; 560 } 561 562 if (mode == SERVICE_COMPLETED_MODE_ASYNC) { 563 status = mailbox_read_response_async(job_id, 564 NULL, (uint32_t *) addr, &resp_len, 0); 565 } else { 566 status = mailbox_read_response(job_id, 567 (uint32_t *) addr, &resp_len); 568 569 if (status == MBOX_NO_RESPONSE) { 570 status = MBOX_BUSY; 571 } 572 } 573 574 if (status == MBOX_NO_RESPONSE) { 575 return INTEL_SIP_SMC_STATUS_NO_RESPONSE; 576 } 577 578 if (status == MBOX_BUSY) { 579 return INTEL_SIP_SMC_STATUS_BUSY; 580 } 581 582 *ret_size = resp_len * MBOX_WORD_BYTE; 583 flush_dcache_range(addr, *ret_size); 584 585 if (status != MBOX_RET_OK) { 586 *mbox_error = -status; 587 return INTEL_SIP_SMC_STATUS_ERROR; 588 } 589 590 return INTEL_SIP_SMC_STATUS_OK; 591 } 592 593 /* Miscellaneous HPS services */ 594 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask) 595 { 596 int status = 0; 597 598 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) { 599 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 600 status = socfpga_bridges_enable((uint32_t)mask); 601 } else { 602 status = socfpga_bridges_enable(~0); 603 } 604 } else { 605 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 606 status = socfpga_bridges_disable((uint32_t)mask); 607 } else { 608 status = socfpga_bridges_disable(~0); 609 } 610 } 611 612 if (status < 0) { 613 return INTEL_SIP_SMC_STATUS_ERROR; 614 } 615 616 return INTEL_SIP_SMC_STATUS_OK; 617 } 618 619 /* 620 * This function is responsible for handling all SiP calls from the NS world 621 */ 622 623 uintptr_t sip_smc_handler_v1(uint32_t smc_fid, 624 u_register_t x1, 625 u_register_t x2, 626 u_register_t x3, 627 u_register_t x4, 628 void *cookie, 629 void *handle, 630 u_register_t flags) 631 { 632 uint32_t retval = 0, completed_addr[3]; 633 uint32_t retval2 = 0; 634 uint32_t mbox_error = 0; 635 uint64_t retval64, rsu_respbuf[9]; 636 int status = INTEL_SIP_SMC_STATUS_OK; 637 int mbox_status; 638 unsigned int len_in_resp; 639 u_register_t x5, x6, x7; 640 641 switch (smc_fid) { 642 case SIP_SVC_UID: 643 /* Return UID to the caller */ 644 SMC_UUID_RET(handle, intl_svc_uid); 645 646 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 647 status = intel_mailbox_fpga_config_isdone(x1); 648 SMC_RET4(handle, status, 0, 0, 0); 649 650 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 651 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 652 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 653 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 654 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 655 656 case INTEL_SIP_SMC_FPGA_CONFIG_START: 657 status = intel_fpga_config_start(x1); 658 SMC_RET4(handle, status, 0, 0, 0); 659 660 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 661 status = intel_fpga_config_write(x1, x2); 662 SMC_RET4(handle, status, 0, 0, 0); 663 664 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 665 status = intel_fpga_config_completed_write(completed_addr, 666 &retval, &rcv_id); 667 switch (retval) { 668 case 1: 669 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 670 completed_addr[0], 0, 0); 671 672 case 2: 673 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 674 completed_addr[0], 675 completed_addr[1], 0); 676 677 case 3: 678 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 679 completed_addr[0], 680 completed_addr[1], 681 completed_addr[2]); 682 683 case 0: 684 SMC_RET4(handle, status, 0, 0, 0); 685 686 default: 687 mailbox_clear_response(); 688 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 689 } 690 691 case INTEL_SIP_SMC_REG_READ: 692 status = intel_secure_reg_read(x1, &retval); 693 SMC_RET3(handle, status, retval, x1); 694 695 case INTEL_SIP_SMC_REG_WRITE: 696 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 697 SMC_RET3(handle, status, retval, x1); 698 699 case INTEL_SIP_SMC_REG_UPDATE: 700 status = intel_secure_reg_update(x1, (uint32_t)x2, 701 (uint32_t)x3, &retval); 702 SMC_RET3(handle, status, retval, x1); 703 704 case INTEL_SIP_SMC_RSU_STATUS: 705 status = intel_rsu_status(rsu_respbuf, 706 ARRAY_SIZE(rsu_respbuf)); 707 if (status) { 708 SMC_RET1(handle, status); 709 } else { 710 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 711 rsu_respbuf[2], rsu_respbuf[3]); 712 } 713 714 case INTEL_SIP_SMC_RSU_UPDATE: 715 status = intel_rsu_update(x1); 716 SMC_RET1(handle, status); 717 718 case INTEL_SIP_SMC_RSU_NOTIFY: 719 status = intel_rsu_notify(x1); 720 SMC_RET1(handle, status); 721 722 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 723 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 724 ARRAY_SIZE(rsu_respbuf), &retval); 725 if (status) { 726 SMC_RET1(handle, status); 727 } else { 728 SMC_RET2(handle, status, retval); 729 } 730 731 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 732 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 733 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 734 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 735 736 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 737 status = intel_rsu_copy_dcmf_version(x1, x2); 738 SMC_RET1(handle, status); 739 740 case INTEL_SIP_SMC_RSU_DCMF_STATUS: 741 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, 742 ((uint64_t)rsu_dcmf_stat[3] << 48) | 743 ((uint64_t)rsu_dcmf_stat[2] << 32) | 744 ((uint64_t)rsu_dcmf_stat[1] << 16) | 745 rsu_dcmf_stat[0]); 746 747 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: 748 status = intel_rsu_copy_dcmf_status(x1); 749 SMC_RET1(handle, status); 750 751 case INTEL_SIP_SMC_RSU_MAX_RETRY: 752 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 753 754 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 755 rsu_max_retry = x1; 756 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 757 758 case INTEL_SIP_SMC_ECC_DBE: 759 status = intel_ecc_dbe_notification(x1); 760 SMC_RET1(handle, status); 761 762 case INTEL_SIP_SMC_SERVICE_COMPLETED: 763 status = intel_smc_service_completed(x1, x2, x3, &rcv_id, 764 &len_in_resp, &mbox_error); 765 SMC_RET4(handle, status, mbox_error, x1, len_in_resp); 766 767 case INTEL_SIP_SMC_FIRMWARE_VERSION: 768 status = intel_smc_fw_version(&retval); 769 SMC_RET2(handle, status, retval); 770 771 case INTEL_SIP_SMC_MBOX_SEND_CMD: 772 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 773 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 774 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6, 775 &mbox_status, &len_in_resp); 776 SMC_RET3(handle, status, mbox_status, len_in_resp); 777 778 case INTEL_SIP_SMC_GET_USERCODE: 779 status = intel_smc_get_usercode(&retval); 780 SMC_RET2(handle, status, retval); 781 782 case INTEL_SIP_SMC_FCS_CRYPTION: 783 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 784 785 if (x1 == FCS_MODE_DECRYPT) { 786 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id); 787 } else if (x1 == FCS_MODE_ENCRYPT) { 788 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id); 789 } else { 790 status = INTEL_SIP_SMC_STATUS_REJECTED; 791 } 792 793 SMC_RET3(handle, status, x4, x5); 794 795 case INTEL_SIP_SMC_FCS_CRYPTION_EXT: 796 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 797 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 798 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 799 800 if (x3 == FCS_MODE_DECRYPT) { 801 status = intel_fcs_decryption_ext(x1, x2, x4, x5, x6, 802 (uint32_t *) &x7, &mbox_error); 803 } else if (x3 == FCS_MODE_ENCRYPT) { 804 status = intel_fcs_encryption_ext(x1, x2, x4, x5, x6, 805 (uint32_t *) &x7, &mbox_error); 806 } else { 807 status = INTEL_SIP_SMC_STATUS_REJECTED; 808 } 809 810 SMC_RET4(handle, status, mbox_error, x6, x7); 811 812 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER: 813 status = intel_fcs_random_number_gen(x1, &retval64, 814 &mbox_error); 815 SMC_RET4(handle, status, mbox_error, x1, retval64); 816 817 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT: 818 status = intel_fcs_random_number_gen_ext(x1, x2, x3, 819 &send_id); 820 SMC_RET1(handle, status); 821 822 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE: 823 status = intel_fcs_send_cert(x1, x2, &send_id); 824 SMC_RET1(handle, status); 825 826 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA: 827 status = intel_fcs_get_provision_data(&send_id); 828 SMC_RET1(handle, status); 829 830 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH: 831 status = intel_fcs_cntr_set_preauth(x1, x2, x3, 832 &mbox_error); 833 SMC_RET2(handle, status, mbox_error); 834 835 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 836 status = intel_hps_set_bridges(x1, x2); 837 SMC_RET1(handle, status); 838 839 case INTEL_SIP_SMC_HWMON_READTEMP: 840 status = intel_hwmon_readtemp(x1, &retval); 841 SMC_RET2(handle, status, retval); 842 843 case INTEL_SIP_SMC_HWMON_READVOLT: 844 status = intel_hwmon_readvolt(x1, &retval); 845 SMC_RET2(handle, status, retval); 846 847 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN: 848 status = intel_fcs_sigma_teardown(x1, &mbox_error); 849 SMC_RET2(handle, status, mbox_error); 850 851 case INTEL_SIP_SMC_FCS_CHIP_ID: 852 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error); 853 SMC_RET4(handle, status, mbox_error, retval, retval2); 854 855 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY: 856 status = intel_fcs_attestation_subkey(x1, x2, x3, 857 (uint32_t *) &x4, &mbox_error); 858 SMC_RET4(handle, status, mbox_error, x3, x4); 859 860 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS: 861 status = intel_fcs_get_measurement(x1, x2, x3, 862 (uint32_t *) &x4, &mbox_error); 863 SMC_RET4(handle, status, mbox_error, x3, x4); 864 865 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT: 866 status = intel_fcs_get_attestation_cert(x1, x2, 867 (uint32_t *) &x3, &mbox_error); 868 SMC_RET4(handle, status, mbox_error, x2, x3); 869 870 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD: 871 status = intel_fcs_create_cert_on_reload(x1, &mbox_error); 872 SMC_RET2(handle, status, mbox_error); 873 874 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION: 875 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error); 876 SMC_RET3(handle, status, mbox_error, retval); 877 878 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION: 879 status = intel_fcs_close_crypto_service_session(x1, &mbox_error); 880 SMC_RET2(handle, status, mbox_error); 881 882 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY: 883 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id); 884 SMC_RET1(handle, status); 885 886 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY: 887 status = intel_fcs_export_crypto_service_key(x1, x2, x3, 888 (uint32_t *) &x4, &mbox_error); 889 SMC_RET4(handle, status, mbox_error, x3, x4); 890 891 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY: 892 status = intel_fcs_remove_crypto_service_key(x1, x2, 893 &mbox_error); 894 SMC_RET2(handle, status, mbox_error); 895 896 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO: 897 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3, 898 (uint32_t *) &x4, &mbox_error); 899 SMC_RET4(handle, status, mbox_error, x3, x4); 900 901 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT: 902 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 903 status = intel_fcs_get_digest_init(x1, x2, x3, 904 x4, x5, &mbox_error); 905 SMC_RET2(handle, status, mbox_error); 906 907 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE: 908 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 909 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 910 status = intel_fcs_get_digest_update_finalize(x1, x2, x3, 911 x4, x5, (uint32_t *) &x6, false, 912 &mbox_error); 913 SMC_RET4(handle, status, mbox_error, x5, x6); 914 915 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE: 916 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 917 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 918 status = intel_fcs_get_digest_update_finalize(x1, x2, x3, 919 x4, x5, (uint32_t *) &x6, true, 920 &mbox_error); 921 SMC_RET4(handle, status, mbox_error, x5, x6); 922 923 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT: 924 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 925 status = intel_fcs_mac_verify_init(x1, x2, x3, 926 x4, x5, &mbox_error); 927 SMC_RET2(handle, status, mbox_error); 928 929 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE: 930 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 931 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 932 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 933 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, 934 x4, x5, (uint32_t *) &x6, x7, 935 false, &mbox_error); 936 SMC_RET4(handle, status, mbox_error, x5, x6); 937 938 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE: 939 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 940 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 941 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 942 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, 943 x4, x5, (uint32_t *) &x6, x7, 944 true, &mbox_error); 945 SMC_RET4(handle, status, mbox_error, x5, x6); 946 947 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 948 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 949 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3, 950 x4, x5, &mbox_error); 951 SMC_RET2(handle, status, mbox_error); 952 953 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 954 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 955 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 956 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 957 x3, x4, x5, (uint32_t *) &x6, false, 958 &mbox_error); 959 SMC_RET4(handle, status, mbox_error, x5, x6); 960 961 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 962 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 963 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 964 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 965 x3, x4, x5, (uint32_t *) &x6, true, 966 &mbox_error); 967 SMC_RET4(handle, status, mbox_error, x5, x6); 968 969 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT: 970 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 971 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3, 972 x4, x5, &mbox_error); 973 SMC_RET2(handle, status, mbox_error); 974 975 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE: 976 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 977 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 978 status = intel_fcs_ecdsa_hash_sign_finalize(x1, x2, x3, 979 x4, x5, (uint32_t *) &x6, &mbox_error); 980 SMC_RET4(handle, status, mbox_error, x5, x6); 981 982 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 983 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 984 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3, 985 x4, x5, &mbox_error); 986 SMC_RET2(handle, status, mbox_error); 987 988 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 989 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 990 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 991 status = intel_fcs_ecdsa_hash_sig_verify_finalize(x1, x2, x3, 992 x4, x5, (uint32_t *) &x6, &mbox_error); 993 SMC_RET4(handle, status, mbox_error, x5, x6); 994 995 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 996 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 997 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3, 998 x4, x5, &mbox_error); 999 SMC_RET2(handle, status, mbox_error); 1000 1001 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 1002 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1003 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1004 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1005 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1006 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1007 x7, false, &mbox_error); 1008 SMC_RET4(handle, status, mbox_error, x5, x6); 1009 1010 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 1011 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1012 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1013 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1014 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1015 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1016 x7, true, &mbox_error); 1017 SMC_RET4(handle, status, mbox_error, x5, x6); 1018 1019 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT: 1020 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1021 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3, 1022 x4, x5, &mbox_error); 1023 SMC_RET2(handle, status, mbox_error); 1024 1025 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 1026 status = intel_fcs_ecdsa_get_pubkey_finalize(x1, x2, x3, 1027 (uint32_t *) &x4, &mbox_error); 1028 SMC_RET4(handle, status, mbox_error, x3, x4); 1029 1030 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT: 1031 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1032 status = intel_fcs_ecdh_request_init(x1, x2, x3, 1033 x4, x5, &mbox_error); 1034 SMC_RET2(handle, status, mbox_error); 1035 1036 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE: 1037 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1038 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1039 status = intel_fcs_ecdh_request_finalize(x1, x2, x3, 1040 x4, x5, (uint32_t *) &x6, &mbox_error); 1041 SMC_RET4(handle, status, mbox_error, x5, x6); 1042 1043 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT: 1044 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1045 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5, 1046 &mbox_error); 1047 SMC_RET2(handle, status, mbox_error); 1048 1049 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE: 1050 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1051 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1052 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1053 x5, x6, false, &send_id); 1054 SMC_RET1(handle, status); 1055 1056 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE: 1057 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1058 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1059 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1060 x5, x6, true, &send_id); 1061 SMC_RET1(handle, status); 1062 1063 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 1064 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 1065 &mbox_error); 1066 SMC_RET4(handle, status, mbox_error, x1, retval64); 1067 1068 case INTEL_SIP_SMC_SVC_VERSION: 1069 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 1070 SIP_SVC_VERSION_MAJOR, 1071 SIP_SVC_VERSION_MINOR); 1072 1073 default: 1074 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 1075 cookie, handle, flags); 1076 } 1077 } 1078 1079 uintptr_t sip_smc_handler(uint32_t smc_fid, 1080 u_register_t x1, 1081 u_register_t x2, 1082 u_register_t x3, 1083 u_register_t x4, 1084 void *cookie, 1085 void *handle, 1086 u_register_t flags) 1087 { 1088 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK; 1089 1090 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN && 1091 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) { 1092 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4, 1093 cookie, handle, flags); 1094 } else { 1095 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4, 1096 cookie, handle, flags); 1097 } 1098 } 1099 1100 DECLARE_RT_SVC( 1101 socfpga_sip_svc, 1102 OEN_SIP_START, 1103 OEN_SIP_END, 1104 SMC_TYPE_FAST, 1105 NULL, 1106 sip_smc_handler 1107 ); 1108 1109 DECLARE_RT_SVC( 1110 socfpga_sip_svc_std, 1111 OEN_SIP_START, 1112 OEN_SIP_END, 1113 SMC_TYPE_YIELD, 1114 NULL, 1115 sip_smc_handler 1116 ); 1117