1 /* 2 * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef PLATFORM_DEF_H 10 #define PLATFORM_DEF_H 11 12 #include <arch.h> 13 #include "def.h" 14 15 /******************************************************************************* 16 * Generic platform constants 17 ******************************************************************************/ 18 19 /* Size of cacheable stacks */ 20 #define PLATFORM_STACK_SIZE U(0x440) 21 22 #define PLATFORM_CLUSTER_COUNT U(4) 23 #define PLATFORM_CORE_COUNT_PER_CLUSTER U(2) /* 2 CPUs per cluster */ 24 25 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * PLATFORM_CORE_COUNT_PER_CLUSTER) 26 27 #define PLAT_MAX_PWR_LVL U(2) 28 #define PLAT_MAX_RET_STATE U(1) 29 #define PLAT_MAX_OFF_STATE U(2) 30 31 /******************************************************************************* 32 * BL31 specific defines. 33 ******************************************************************************/ 34 /* 35 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 36 * present). BL31_BASE is calculated using the current BL31 debug size plus a 37 * little space for growth. 38 */ 39 #ifndef MEM_BASE 40 # define BL31_BASE U(0xBBF00000) 41 # define BL31_LIMIT U(0xBC000000) 42 #else 43 # define BL31_BASE U(MEM_BASE) 44 # define BL31_LIMIT U(MEM_BASE + MEM_SIZE) 45 # ifdef MEM_PROGBITS_SIZE 46 # define BL31_PROGBITS_LIMIT U(MEM_BASE + \ 47 MEM_PROGBITS_SIZE) 48 # endif 49 #endif 50 51 /******************************************************************************* 52 * BL32 specific defines. 53 ******************************************************************************/ 54 #ifndef BL32_MEM_BASE 55 # define BL32_BASE U(0x60000000) 56 # define BL32_LIMIT U(0x80000000) 57 #else 58 # define BL32_BASE U(BL32_MEM_BASE) 59 # define BL32_LIMIT U(BL32_MEM_BASE + BL32_MEM_SIZE) 60 #endif 61 62 /******************************************************************************* 63 * BL33 specific defines. 64 ******************************************************************************/ 65 #ifndef PRELOADED_BL33_BASE 66 # define PLAT_ARM_NS_IMAGE_BASE U(0x8000000) 67 #else 68 # define PLAT_ARM_NS_IMAGE_BASE U(PRELOADED_BL33_BASE) 69 #endif 70 71 /******************************************************************************* 72 * TSP specific defines. 73 ******************************************************************************/ 74 #define TSP_SEC_MEM_BASE BL32_BASE 75 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE) 76 77 /* ID of the secure physical generic timer interrupt used by the TSP */ 78 #define ARM_IRQ_SEC_PHY_TIMER U(29) 79 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 80 81 /******************************************************************************* 82 * Platform specific page table and MMU setup constants 83 ******************************************************************************/ 84 #define PLAT_DDR_LOWMEM_MAX U(0x80000000) 85 86 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32U) 87 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32U) 88 89 #define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000) 90 91 #define PLAT_OCM_BASE U(0xBBF00000) 92 #define PLAT_OCM_LIMIT U(0xBC000000) 93 94 #if defined(TRANSFER_LIST) 95 /* 96 * FIXME: This address should come from firmware before TF-A 97 * Having this to make sure the transfer list functionality works 98 */ 99 #define FW_HANDOFF_BASE U(0x70000000) 100 #define FW_HANDOFF_SIZE U(0x10000) 101 #endif 102 103 #define IS_TFA_IN_OCM(x) ((x >= PLAT_OCM_BASE) && (x < PLAT_OCM_LIMIT)) 104 105 #ifndef MAX_MMAP_REGIONS 106 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 107 #define MAX_MMAP_REGIONS 11 108 #else 109 #define MAX_MMAP_REGIONS 10 110 #endif 111 #endif 112 113 #ifndef MAX_XLAT_TABLES 114 #define MAX_XLAT_TABLES U(12) 115 #endif 116 117 #define CACHE_WRITEBACK_SHIFT U(6) 118 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 119 120 #define PLAT_GICD_BASE_VALUE U(0xE2000000) 121 #define PLAT_GICR_BASE_VALUE U(0xE2060000) 122 123 /* 124 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 125 * terminology. On a GICv2 system or mode, the lists will be merged and treated 126 * as Group 0 interrupts. 127 */ 128 #define PLAT_IPI_IRQ 89 129 #define PLAT_VERSAL_IPI_IRQ PLAT_IPI_IRQ 130 131 #define PLAT_G1S_IRQ_PROPS(grp) \ 132 INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 133 GIC_INTR_CFG_LEVEL) 134 135 #define PLAT_G0_IRQ_PROPS(grp) \ 136 INTR_PROP_DESC(PLAT_VERSAL_IPI_IRQ, GIC_HIGHEST_SEC_PRIORITY, grp, \ 137 GIC_INTR_CFG_EDGE), \ 138 139 #define IRQ_MAX 200U 140 141 #endif /* PLATFORM_DEF_H */ 142