1 /* 2 * Copyright 2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <drivers/clk.h> 7 #include <platform_def.h> 8 #include <s32cc-clk-drv.h> 9 #include <s32cc-clk-ids.h> 10 #include <s32cc-clk-utils.h> 11 12 #define S32CC_FXOSC_FREQ (40U * MHZ) 13 #define S32CC_ARM_PLL_VCO_FREQ (2U * GHZ) 14 #define S32CC_ARM_PLL_PHI0_FREQ (1U * GHZ) 15 #define S32CC_A53_FREQ (1U * GHZ) 16 #define S32CC_XBAR_2X_FREQ (800U * MHZ) 17 #define S32CC_PERIPH_PLL_VCO_FREQ (2U * GHZ) 18 #define S32CC_PERIPH_PLL_PHI3_FREQ UART_CLOCK_HZ 19 20 static int enable_fxosc_clk(void) 21 { 22 int ret; 23 24 ret = clk_set_rate(S32CC_CLK_FXOSC, S32CC_FXOSC_FREQ, NULL); 25 if (ret != 0) { 26 return ret; 27 } 28 29 ret = clk_enable(S32CC_CLK_FXOSC); 30 if (ret != 0) { 31 return ret; 32 } 33 34 return ret; 35 } 36 37 static int enable_arm_pll(void) 38 { 39 int ret; 40 41 ret = clk_set_parent(S32CC_CLK_ARM_PLL_MUX, S32CC_CLK_FXOSC); 42 if (ret != 0) { 43 return ret; 44 } 45 46 ret = clk_set_rate(S32CC_CLK_ARM_PLL_VCO, S32CC_ARM_PLL_VCO_FREQ, NULL); 47 if (ret != 0) { 48 return ret; 49 } 50 51 ret = clk_set_rate(S32CC_CLK_ARM_PLL_PHI0, S32CC_ARM_PLL_PHI0_FREQ, NULL); 52 if (ret != 0) { 53 return ret; 54 } 55 56 ret = clk_enable(S32CC_CLK_ARM_PLL_VCO); 57 if (ret != 0) { 58 return ret; 59 } 60 61 ret = clk_enable(S32CC_CLK_ARM_PLL_PHI0); 62 if (ret != 0) { 63 return ret; 64 } 65 66 return ret; 67 } 68 69 static int enable_periph_pll(void) 70 { 71 int ret; 72 73 ret = clk_set_parent(S32CC_CLK_PERIPH_PLL_MUX, S32CC_CLK_FXOSC); 74 if (ret != 0) { 75 return ret; 76 } 77 78 ret = clk_set_rate(S32CC_CLK_PERIPH_PLL_VCO, S32CC_PERIPH_PLL_VCO_FREQ, NULL); 79 if (ret != 0) { 80 return ret; 81 } 82 83 ret = clk_set_rate(S32CC_CLK_PERIPH_PLL_PHI3, S32CC_PERIPH_PLL_PHI3_FREQ, NULL); 84 if (ret != 0) { 85 return ret; 86 } 87 88 ret = clk_enable(S32CC_CLK_PERIPH_PLL_VCO); 89 if (ret != 0) { 90 return ret; 91 } 92 93 ret = clk_enable(S32CC_CLK_PERIPH_PLL_PHI3); 94 if (ret != 0) { 95 return ret; 96 } 97 98 return ret; 99 } 100 101 static int enable_a53_clk(void) 102 { 103 int ret; 104 105 ret = clk_set_parent(S32CC_CLK_MC_CGM1_MUX0, S32CC_CLK_ARM_PLL_PHI0); 106 if (ret != 0) { 107 return ret; 108 } 109 110 ret = clk_set_rate(S32CC_CLK_A53_CORE, S32CC_A53_FREQ, NULL); 111 if (ret != 0) { 112 return ret; 113 } 114 115 ret = clk_enable(S32CC_CLK_A53_CORE); 116 if (ret != 0) { 117 return ret; 118 } 119 120 return ret; 121 } 122 123 static int enable_xbar_clk(void) 124 { 125 int ret; 126 127 ret = clk_set_parent(S32CC_CLK_MC_CGM0_MUX0, S32CC_CLK_ARM_PLL_DFS1); 128 if (ret != 0) { 129 return ret; 130 } 131 132 ret = clk_set_rate(S32CC_CLK_XBAR_2X, S32CC_XBAR_2X_FREQ, NULL); 133 if (ret != 0) { 134 return ret; 135 } 136 137 ret = clk_enable(S32CC_CLK_ARM_PLL_DFS1); 138 if (ret != 0) { 139 return ret; 140 } 141 142 ret = clk_enable(S32CC_CLK_XBAR_2X); 143 if (ret != 0) { 144 return ret; 145 } 146 147 return ret; 148 } 149 150 static int enable_uart_clk(void) 151 { 152 int ret; 153 154 ret = clk_set_parent(S32CC_CLK_MC_CGM0_MUX8, S32CC_CLK_PERIPH_PLL_PHI3); 155 if (ret != 0) { 156 return ret; 157 } 158 159 ret = clk_enable(S32CC_CLK_LINFLEX_BAUD); 160 if (ret != 0) { 161 return ret; 162 } 163 164 return ret; 165 } 166 167 int s32cc_init_early_clks(void) 168 { 169 int ret; 170 171 s32cc_clk_register_drv(); 172 173 ret = enable_fxosc_clk(); 174 if (ret != 0) { 175 return ret; 176 } 177 178 ret = enable_arm_pll(); 179 if (ret != 0) { 180 return ret; 181 } 182 183 ret = enable_periph_pll(); 184 if (ret != 0) { 185 return ret; 186 } 187 188 ret = enable_a53_clk(); 189 if (ret != 0) { 190 return ret; 191 } 192 193 ret = enable_xbar_clk(); 194 if (ret != 0) { 195 return ret; 196 } 197 198 ret = enable_uart_clk(); 199 if (ret != 0) { 200 return ret; 201 } 202 203 return ret; 204 } 205