1 /* 2 * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/debug.h> 9 #include <common/runtime_svc.h> 10 #include <lib/mmio.h> 11 #include <tools_share/uuid.h> 12 13 #include "socfpga_fcs.h" 14 #include "socfpga_mailbox.h" 15 #include "socfpga_plat_def.h" 16 #include "socfpga_reset_manager.h" 17 #include "socfpga_sip_svc.h" 18 #include "socfpga_system_manager.h" 19 20 /* Total buffer the driver can hold */ 21 #define FPGA_CONFIG_BUFFER_SIZE 4 22 23 static config_type request_type = NO_REQUEST; 24 static int current_block, current_buffer; 25 static int read_block, max_blocks; 26 static uint32_t send_id, rcv_id; 27 static uint32_t bytes_per_block, blocks_submitted; 28 static bool bridge_disable; 29 30 /* RSU static variables */ 31 static uint32_t rsu_dcmf_ver[4] = {0}; 32 static uint16_t rsu_dcmf_stat[4] = {0}; 33 static uint32_t rsu_max_retry; 34 35 /* SiP Service UUID */ 36 DEFINE_SVC_UUID2(intl_svc_uid, 37 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 38 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 39 40 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 41 uint64_t x1, 42 uint64_t x2, 43 uint64_t x3, 44 uint64_t x4, 45 void *cookie, 46 void *handle, 47 uint64_t flags) 48 { 49 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 50 SMC_RET1(handle, SMC_UNK); 51 } 52 53 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 54 55 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 56 { 57 uint32_t args[3]; 58 59 while (max_blocks > 0 && buffer->size > buffer->size_written) { 60 args[0] = (1<<8); 61 args[1] = buffer->addr + buffer->size_written; 62 if (buffer->size - buffer->size_written <= bytes_per_block) { 63 args[2] = buffer->size - buffer->size_written; 64 current_buffer++; 65 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 66 } else { 67 args[2] = bytes_per_block; 68 } 69 70 buffer->size_written += args[2]; 71 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 72 3U, CMD_INDIRECT); 73 74 buffer->subblocks_sent++; 75 max_blocks--; 76 } 77 78 return !max_blocks; 79 } 80 81 static int intel_fpga_sdm_write_all(void) 82 { 83 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 84 if (intel_fpga_sdm_write_buffer( 85 &fpga_config_buffers[current_buffer])) { 86 break; 87 } 88 } 89 return 0; 90 } 91 92 static uint32_t intel_mailbox_fpga_config_isdone(void) 93 { 94 uint32_t ret; 95 96 switch (request_type) { 97 case RECONFIGURATION: 98 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 99 true); 100 break; 101 case BITSTREAM_AUTH: 102 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 103 false); 104 break; 105 default: 106 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, 107 false); 108 break; 109 } 110 111 if (ret != 0U) { 112 if (ret == MBOX_CFGSTAT_STATE_CONFIG) { 113 return INTEL_SIP_SMC_STATUS_BUSY; 114 } else { 115 request_type = NO_REQUEST; 116 return INTEL_SIP_SMC_STATUS_ERROR; 117 } 118 } 119 120 if (bridge_disable != 0U) { 121 socfpga_bridges_enable(~0); /* Enable bridge */ 122 bridge_disable = false; 123 } 124 request_type = NO_REQUEST; 125 126 return INTEL_SIP_SMC_STATUS_OK; 127 } 128 129 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 130 { 131 int i; 132 133 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 134 if (fpga_config_buffers[i].block_number == current_block) { 135 fpga_config_buffers[i].subblocks_sent--; 136 if (fpga_config_buffers[i].subblocks_sent == 0 137 && fpga_config_buffers[i].size <= 138 fpga_config_buffers[i].size_written) { 139 fpga_config_buffers[i].write_requested = 0; 140 current_block++; 141 *buffer_addr_completed = 142 fpga_config_buffers[i].addr; 143 return 0; 144 } 145 } 146 } 147 148 return -1; 149 } 150 151 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 152 uint32_t *count, uint32_t *job_id) 153 { 154 uint32_t resp[5]; 155 unsigned int resp_len = ARRAY_SIZE(resp); 156 int status = INTEL_SIP_SMC_STATUS_OK; 157 int all_completed = 1; 158 *count = 0; 159 160 while (*count < 3) { 161 162 status = mailbox_read_response(job_id, 163 resp, &resp_len); 164 165 if (status < 0) { 166 break; 167 } 168 169 max_blocks++; 170 171 if (mark_last_buffer_xfer_completed( 172 &completed_addr[*count]) == 0) { 173 *count = *count + 1; 174 } else { 175 break; 176 } 177 } 178 179 if (*count <= 0) { 180 if (status != MBOX_NO_RESPONSE && 181 status != MBOX_TIMEOUT && resp_len != 0) { 182 mailbox_clear_response(); 183 request_type = NO_REQUEST; 184 return INTEL_SIP_SMC_STATUS_ERROR; 185 } 186 187 *count = 0; 188 } 189 190 intel_fpga_sdm_write_all(); 191 192 if (*count > 0) { 193 status = INTEL_SIP_SMC_STATUS_OK; 194 } else if (*count == 0) { 195 status = INTEL_SIP_SMC_STATUS_BUSY; 196 } 197 198 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 199 if (fpga_config_buffers[i].write_requested != 0) { 200 all_completed = 0; 201 break; 202 } 203 } 204 205 if (all_completed == 1) { 206 return INTEL_SIP_SMC_STATUS_OK; 207 } 208 209 return status; 210 } 211 212 static int intel_fpga_config_start(uint32_t flag) 213 { 214 uint32_t argument = 0x1; 215 uint32_t response[3]; 216 int status = 0; 217 unsigned int size = 0; 218 unsigned int resp_len = ARRAY_SIZE(response); 219 220 request_type = RECONFIGURATION; 221 222 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) { 223 bridge_disable = true; 224 } 225 226 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) { 227 size = 1; 228 bridge_disable = false; 229 request_type = BITSTREAM_AUTH; 230 } 231 232 mailbox_clear_response(); 233 234 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 235 CMD_CASUAL, NULL, NULL); 236 237 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 238 CMD_CASUAL, response, &resp_len); 239 240 if (status < 0) { 241 bridge_disable = false; 242 request_type = NO_REQUEST; 243 return INTEL_SIP_SMC_STATUS_ERROR; 244 } 245 246 max_blocks = response[0]; 247 bytes_per_block = response[1]; 248 249 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 250 fpga_config_buffers[i].size = 0; 251 fpga_config_buffers[i].size_written = 0; 252 fpga_config_buffers[i].addr = 0; 253 fpga_config_buffers[i].write_requested = 0; 254 fpga_config_buffers[i].block_number = 0; 255 fpga_config_buffers[i].subblocks_sent = 0; 256 } 257 258 blocks_submitted = 0; 259 current_block = 0; 260 read_block = 0; 261 current_buffer = 0; 262 263 /* Disable bridge on full reconfiguration */ 264 if (bridge_disable) { 265 socfpga_bridges_disable(~0); 266 } 267 268 return INTEL_SIP_SMC_STATUS_OK; 269 } 270 271 static bool is_fpga_config_buffer_full(void) 272 { 273 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 274 if (!fpga_config_buffers[i].write_requested) { 275 return false; 276 } 277 } 278 return true; 279 } 280 281 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 282 { 283 if (!addr && !size) { 284 return true; 285 } 286 if (size > (UINT64_MAX - addr)) { 287 return false; 288 } 289 if (addr < BL31_LIMIT) { 290 return false; 291 } 292 if (addr + size > DRAM_BASE + DRAM_SIZE) { 293 return false; 294 } 295 296 return true; 297 } 298 299 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 300 { 301 int i; 302 303 intel_fpga_sdm_write_all(); 304 305 if (!is_address_in_ddr_range(mem, size) || 306 is_fpga_config_buffer_full()) { 307 return INTEL_SIP_SMC_STATUS_REJECTED; 308 } 309 310 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 311 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 312 313 if (!fpga_config_buffers[j].write_requested) { 314 fpga_config_buffers[j].addr = mem; 315 fpga_config_buffers[j].size = size; 316 fpga_config_buffers[j].size_written = 0; 317 fpga_config_buffers[j].write_requested = 1; 318 fpga_config_buffers[j].block_number = 319 blocks_submitted++; 320 fpga_config_buffers[j].subblocks_sent = 0; 321 break; 322 } 323 } 324 325 if (is_fpga_config_buffer_full()) { 326 return INTEL_SIP_SMC_STATUS_BUSY; 327 } 328 329 return INTEL_SIP_SMC_STATUS_OK; 330 } 331 332 static int is_out_of_sec_range(uint64_t reg_addr) 333 { 334 #if DEBUG 335 return 0; 336 #endif 337 338 switch (reg_addr) { 339 case(0xF8011100): /* ECCCTRL1 */ 340 case(0xF8011104): /* ECCCTRL2 */ 341 case(0xF8011110): /* ERRINTEN */ 342 case(0xF8011114): /* ERRINTENS */ 343 case(0xF8011118): /* ERRINTENR */ 344 case(0xF801111C): /* INTMODE */ 345 case(0xF8011120): /* INTSTAT */ 346 case(0xF8011124): /* DIAGINTTEST */ 347 case(0xF801112C): /* DERRADDRA */ 348 case(0xFA000000): /* SMMU SCR0 */ 349 case(0xFA000004): /* SMMU SCR1 */ 350 case(0xFA000400): /* SMMU NSCR0 */ 351 case(0xFA004000): /* SMMU SSD0_REG */ 352 case(0xFA000820): /* SMMU SMR8 */ 353 case(0xFA000c20): /* SMMU SCR8 */ 354 case(0xFA028000): /* SMMU CB8_SCTRL */ 355 case(0xFA001020): /* SMMU CBAR8 */ 356 case(0xFA028030): /* SMMU TCR_LPAE */ 357 case(0xFA028020): /* SMMU CB8_TTBR0_LOW */ 358 case(0xFA028024): /* SMMU CB8_PRRR_HIGH */ 359 case(0xFA028038): /* SMMU CB8_PRRR_MIR0 */ 360 case(0xFA02803C): /* SMMU CB8_PRRR_MIR1 */ 361 case(0xFA028010): /* SMMU_CB8)TCR2 */ 362 case(0xFFD080A4): /* SDM SMMU STREAM ID REG */ 363 case(0xFA001820): /* SMMU_CBA2R8 */ 364 case(0xFA000074): /* SMMU_STLBGSTATUS */ 365 case(0xFA0287F4): /* SMMU_CB8_TLBSTATUS */ 366 case(0xFA000060): /* SMMU_STLBIALL */ 367 case(0xFA000070): /* SMMU_STLBGSYNC */ 368 case(0xFA028618): /* CB8_TLBALL */ 369 case(0xFA0287F0): /* CB8_TLBSYNC */ 370 case(0xFFD12028): /* SDMMCGRP_CTRL */ 371 case(0xFFD12044): /* EMAC0 */ 372 case(0xFFD12048): /* EMAC1 */ 373 case(0xFFD1204C): /* EMAC2 */ 374 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 375 case(0xFFD12094): /* ECC_INT_MASK_SET */ 376 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 377 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 378 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 379 case(0xFFD120C0): /* NOC_TIMEOUT */ 380 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 381 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 382 case(0xFFD120D0): /* NOC_IDLEACK */ 383 case(0xFFD120D4): /* NOC_IDLESTATUS */ 384 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 385 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 386 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 387 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 388 return 0; 389 390 default: 391 break; 392 } 393 394 return -1; 395 } 396 397 /* Secure register access */ 398 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 399 { 400 if (is_out_of_sec_range(reg_addr)) { 401 return INTEL_SIP_SMC_STATUS_ERROR; 402 } 403 404 *retval = mmio_read_32(reg_addr); 405 406 return INTEL_SIP_SMC_STATUS_OK; 407 } 408 409 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 410 uint32_t *retval) 411 { 412 if (is_out_of_sec_range(reg_addr)) { 413 return INTEL_SIP_SMC_STATUS_ERROR; 414 } 415 416 mmio_write_32(reg_addr, val); 417 418 return intel_secure_reg_read(reg_addr, retval); 419 } 420 421 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 422 uint32_t val, uint32_t *retval) 423 { 424 if (!intel_secure_reg_read(reg_addr, retval)) { 425 *retval &= ~mask; 426 *retval |= val & mask; 427 return intel_secure_reg_write(reg_addr, *retval, retval); 428 } 429 430 return INTEL_SIP_SMC_STATUS_ERROR; 431 } 432 433 /* Intel Remote System Update (RSU) services */ 434 uint64_t intel_rsu_update_address; 435 436 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 437 { 438 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 439 return INTEL_SIP_SMC_RSU_ERROR; 440 } 441 442 return INTEL_SIP_SMC_STATUS_OK; 443 } 444 445 static uint32_t intel_rsu_update(uint64_t update_address) 446 { 447 intel_rsu_update_address = update_address; 448 return INTEL_SIP_SMC_STATUS_OK; 449 } 450 451 static uint32_t intel_rsu_notify(uint32_t execution_stage) 452 { 453 if (mailbox_hps_stage_notify(execution_stage) < 0) { 454 return INTEL_SIP_SMC_RSU_ERROR; 455 } 456 457 return INTEL_SIP_SMC_STATUS_OK; 458 } 459 460 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 461 uint32_t *ret_stat) 462 { 463 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 464 return INTEL_SIP_SMC_RSU_ERROR; 465 } 466 467 *ret_stat = respbuf[8]; 468 return INTEL_SIP_SMC_STATUS_OK; 469 } 470 471 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 472 uint64_t dcmf_ver_3_2) 473 { 474 rsu_dcmf_ver[0] = dcmf_ver_1_0; 475 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 476 rsu_dcmf_ver[2] = dcmf_ver_3_2; 477 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 478 479 return INTEL_SIP_SMC_STATUS_OK; 480 } 481 482 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) 483 { 484 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); 485 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); 486 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); 487 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); 488 489 return INTEL_SIP_SMC_STATUS_OK; 490 } 491 492 /* Intel HWMON services */ 493 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval) 494 { 495 if (mailbox_hwmon_readtemp(chan, retval) < 0) { 496 return INTEL_SIP_SMC_STATUS_ERROR; 497 } 498 499 return INTEL_SIP_SMC_STATUS_OK; 500 } 501 502 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval) 503 { 504 if (mailbox_hwmon_readvolt(chan, retval) < 0) { 505 return INTEL_SIP_SMC_STATUS_ERROR; 506 } 507 508 return INTEL_SIP_SMC_STATUS_OK; 509 } 510 511 /* Mailbox services */ 512 static uint32_t intel_smc_fw_version(uint32_t *fw_version) 513 { 514 int status; 515 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE; 516 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U}; 517 518 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U, 519 CMD_CASUAL, resp_data, &resp_len); 520 521 if (status < 0) { 522 return INTEL_SIP_SMC_STATUS_ERROR; 523 } 524 525 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) { 526 return INTEL_SIP_SMC_STATUS_ERROR; 527 } 528 529 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK; 530 531 return INTEL_SIP_SMC_STATUS_OK; 532 } 533 534 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 535 unsigned int len, uint32_t urgent, uint64_t response, 536 unsigned int resp_len, int *mbox_status, 537 unsigned int *len_in_resp) 538 { 539 *len_in_resp = 0; 540 *mbox_status = GENERIC_RESPONSE_ERROR; 541 542 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) { 543 return INTEL_SIP_SMC_STATUS_REJECTED; 544 } 545 546 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 547 (uint32_t *) response, &resp_len); 548 549 if (status < 0) { 550 *mbox_status = -status; 551 return INTEL_SIP_SMC_STATUS_ERROR; 552 } 553 554 *mbox_status = 0; 555 *len_in_resp = resp_len; 556 557 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE); 558 559 return INTEL_SIP_SMC_STATUS_OK; 560 } 561 562 static int intel_smc_get_usercode(uint32_t *user_code) 563 { 564 int status; 565 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE; 566 567 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL, 568 0U, CMD_CASUAL, user_code, &resp_len); 569 570 if (status < 0) { 571 return INTEL_SIP_SMC_STATUS_ERROR; 572 } 573 574 return INTEL_SIP_SMC_STATUS_OK; 575 } 576 577 uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size, 578 uint32_t mode, uint32_t *job_id, 579 uint32_t *ret_size, uint32_t *mbox_error) 580 { 581 int status = 0; 582 uint32_t resp_len = size / MBOX_WORD_BYTE; 583 584 if (resp_len > MBOX_DATA_MAX_LEN) { 585 return INTEL_SIP_SMC_STATUS_REJECTED; 586 } 587 588 if (!is_address_in_ddr_range(addr, size)) { 589 return INTEL_SIP_SMC_STATUS_REJECTED; 590 } 591 592 if (mode == SERVICE_COMPLETED_MODE_ASYNC) { 593 status = mailbox_read_response_async(job_id, 594 NULL, (uint32_t *) addr, &resp_len, 0); 595 } else { 596 status = mailbox_read_response(job_id, 597 (uint32_t *) addr, &resp_len); 598 599 if (status == MBOX_NO_RESPONSE) { 600 status = MBOX_BUSY; 601 } 602 } 603 604 if (status == MBOX_NO_RESPONSE) { 605 return INTEL_SIP_SMC_STATUS_NO_RESPONSE; 606 } 607 608 if (status == MBOX_BUSY) { 609 return INTEL_SIP_SMC_STATUS_BUSY; 610 } 611 612 *ret_size = resp_len * MBOX_WORD_BYTE; 613 flush_dcache_range(addr, *ret_size); 614 615 if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 || 616 status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) { 617 *mbox_error = -status; 618 } else if (status != MBOX_RET_OK) { 619 *mbox_error = -status; 620 return INTEL_SIP_SMC_STATUS_ERROR; 621 } 622 623 return INTEL_SIP_SMC_STATUS_OK; 624 } 625 626 /* Miscellaneous HPS services */ 627 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask) 628 { 629 int status = 0; 630 631 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) { 632 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 633 status = socfpga_bridges_enable((uint32_t)mask); 634 } else { 635 status = socfpga_bridges_enable(~0); 636 } 637 } else { 638 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 639 status = socfpga_bridges_disable((uint32_t)mask); 640 } else { 641 status = socfpga_bridges_disable(~0); 642 } 643 } 644 645 if (status < 0) { 646 return INTEL_SIP_SMC_STATUS_ERROR; 647 } 648 649 return INTEL_SIP_SMC_STATUS_OK; 650 } 651 652 /* 653 * This function is responsible for handling all SiP calls from the NS world 654 */ 655 656 uintptr_t sip_smc_handler_v1(uint32_t smc_fid, 657 u_register_t x1, 658 u_register_t x2, 659 u_register_t x3, 660 u_register_t x4, 661 void *cookie, 662 void *handle, 663 u_register_t flags) 664 { 665 uint32_t retval = 0, completed_addr[3]; 666 uint32_t retval2 = 0; 667 uint32_t mbox_error = 0; 668 uint64_t retval64, rsu_respbuf[9]; 669 int status = INTEL_SIP_SMC_STATUS_OK; 670 int mbox_status; 671 unsigned int len_in_resp; 672 u_register_t x5, x6, x7; 673 674 switch (smc_fid) { 675 case SIP_SVC_UID: 676 /* Return UID to the caller */ 677 SMC_UUID_RET(handle, intl_svc_uid); 678 679 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 680 status = intel_mailbox_fpga_config_isdone(); 681 SMC_RET4(handle, status, 0, 0, 0); 682 683 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 684 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 685 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 686 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 687 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 688 689 case INTEL_SIP_SMC_FPGA_CONFIG_START: 690 status = intel_fpga_config_start(x1); 691 SMC_RET4(handle, status, 0, 0, 0); 692 693 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 694 status = intel_fpga_config_write(x1, x2); 695 SMC_RET4(handle, status, 0, 0, 0); 696 697 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 698 status = intel_fpga_config_completed_write(completed_addr, 699 &retval, &rcv_id); 700 switch (retval) { 701 case 1: 702 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 703 completed_addr[0], 0, 0); 704 705 case 2: 706 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 707 completed_addr[0], 708 completed_addr[1], 0); 709 710 case 3: 711 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 712 completed_addr[0], 713 completed_addr[1], 714 completed_addr[2]); 715 716 case 0: 717 SMC_RET4(handle, status, 0, 0, 0); 718 719 default: 720 mailbox_clear_response(); 721 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 722 } 723 724 case INTEL_SIP_SMC_REG_READ: 725 status = intel_secure_reg_read(x1, &retval); 726 SMC_RET3(handle, status, retval, x1); 727 728 case INTEL_SIP_SMC_REG_WRITE: 729 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 730 SMC_RET3(handle, status, retval, x1); 731 732 case INTEL_SIP_SMC_REG_UPDATE: 733 status = intel_secure_reg_update(x1, (uint32_t)x2, 734 (uint32_t)x3, &retval); 735 SMC_RET3(handle, status, retval, x1); 736 737 case INTEL_SIP_SMC_RSU_STATUS: 738 status = intel_rsu_status(rsu_respbuf, 739 ARRAY_SIZE(rsu_respbuf)); 740 if (status) { 741 SMC_RET1(handle, status); 742 } else { 743 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 744 rsu_respbuf[2], rsu_respbuf[3]); 745 } 746 747 case INTEL_SIP_SMC_RSU_UPDATE: 748 status = intel_rsu_update(x1); 749 SMC_RET1(handle, status); 750 751 case INTEL_SIP_SMC_RSU_NOTIFY: 752 status = intel_rsu_notify(x1); 753 SMC_RET1(handle, status); 754 755 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 756 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 757 ARRAY_SIZE(rsu_respbuf), &retval); 758 if (status) { 759 SMC_RET1(handle, status); 760 } else { 761 SMC_RET2(handle, status, retval); 762 } 763 764 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 765 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 766 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 767 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 768 769 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 770 status = intel_rsu_copy_dcmf_version(x1, x2); 771 SMC_RET1(handle, status); 772 773 case INTEL_SIP_SMC_RSU_DCMF_STATUS: 774 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, 775 ((uint64_t)rsu_dcmf_stat[3] << 48) | 776 ((uint64_t)rsu_dcmf_stat[2] << 32) | 777 ((uint64_t)rsu_dcmf_stat[1] << 16) | 778 rsu_dcmf_stat[0]); 779 780 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: 781 status = intel_rsu_copy_dcmf_status(x1); 782 SMC_RET1(handle, status); 783 784 case INTEL_SIP_SMC_RSU_MAX_RETRY: 785 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 786 787 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 788 rsu_max_retry = x1; 789 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 790 791 case INTEL_SIP_SMC_ECC_DBE: 792 status = intel_ecc_dbe_notification(x1); 793 SMC_RET1(handle, status); 794 795 case INTEL_SIP_SMC_SERVICE_COMPLETED: 796 status = intel_smc_service_completed(x1, x2, x3, &rcv_id, 797 &len_in_resp, &mbox_error); 798 SMC_RET4(handle, status, mbox_error, x1, len_in_resp); 799 800 case INTEL_SIP_SMC_FIRMWARE_VERSION: 801 status = intel_smc_fw_version(&retval); 802 SMC_RET2(handle, status, retval); 803 804 case INTEL_SIP_SMC_MBOX_SEND_CMD: 805 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 806 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 807 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6, 808 &mbox_status, &len_in_resp); 809 SMC_RET3(handle, status, mbox_status, len_in_resp); 810 811 case INTEL_SIP_SMC_GET_USERCODE: 812 status = intel_smc_get_usercode(&retval); 813 SMC_RET2(handle, status, retval); 814 815 case INTEL_SIP_SMC_FCS_CRYPTION: 816 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 817 818 if (x1 == FCS_MODE_DECRYPT) { 819 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id); 820 } else if (x1 == FCS_MODE_ENCRYPT) { 821 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id); 822 } else { 823 status = INTEL_SIP_SMC_STATUS_REJECTED; 824 } 825 826 SMC_RET3(handle, status, x4, x5); 827 828 case INTEL_SIP_SMC_FCS_CRYPTION_EXT: 829 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 830 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 831 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 832 833 if (x3 == FCS_MODE_DECRYPT) { 834 status = intel_fcs_decryption_ext(x1, x2, x4, x5, x6, 835 (uint32_t *) &x7, &mbox_error); 836 } else if (x3 == FCS_MODE_ENCRYPT) { 837 status = intel_fcs_encryption_ext(x1, x2, x4, x5, x6, 838 (uint32_t *) &x7, &mbox_error); 839 } else { 840 status = INTEL_SIP_SMC_STATUS_REJECTED; 841 } 842 843 SMC_RET4(handle, status, mbox_error, x6, x7); 844 845 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER: 846 status = intel_fcs_random_number_gen(x1, &retval64, 847 &mbox_error); 848 SMC_RET4(handle, status, mbox_error, x1, retval64); 849 850 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT: 851 status = intel_fcs_random_number_gen_ext(x1, x2, x3, 852 &send_id); 853 SMC_RET1(handle, status); 854 855 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE: 856 status = intel_fcs_send_cert(x1, x2, &send_id); 857 SMC_RET1(handle, status); 858 859 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA: 860 status = intel_fcs_get_provision_data(&send_id); 861 SMC_RET1(handle, status); 862 863 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH: 864 status = intel_fcs_cntr_set_preauth(x1, x2, x3, 865 &mbox_error); 866 SMC_RET2(handle, status, mbox_error); 867 868 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 869 status = intel_hps_set_bridges(x1, x2); 870 SMC_RET1(handle, status); 871 872 case INTEL_SIP_SMC_HWMON_READTEMP: 873 status = intel_hwmon_readtemp(x1, &retval); 874 SMC_RET2(handle, status, retval); 875 876 case INTEL_SIP_SMC_HWMON_READVOLT: 877 status = intel_hwmon_readvolt(x1, &retval); 878 SMC_RET2(handle, status, retval); 879 880 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN: 881 status = intel_fcs_sigma_teardown(x1, &mbox_error); 882 SMC_RET2(handle, status, mbox_error); 883 884 case INTEL_SIP_SMC_FCS_CHIP_ID: 885 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error); 886 SMC_RET4(handle, status, mbox_error, retval, retval2); 887 888 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY: 889 status = intel_fcs_attestation_subkey(x1, x2, x3, 890 (uint32_t *) &x4, &mbox_error); 891 SMC_RET4(handle, status, mbox_error, x3, x4); 892 893 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS: 894 status = intel_fcs_get_measurement(x1, x2, x3, 895 (uint32_t *) &x4, &mbox_error); 896 SMC_RET4(handle, status, mbox_error, x3, x4); 897 898 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT: 899 status = intel_fcs_get_attestation_cert(x1, x2, 900 (uint32_t *) &x3, &mbox_error); 901 SMC_RET4(handle, status, mbox_error, x2, x3); 902 903 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD: 904 status = intel_fcs_create_cert_on_reload(x1, &mbox_error); 905 SMC_RET2(handle, status, mbox_error); 906 907 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION: 908 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error); 909 SMC_RET3(handle, status, mbox_error, retval); 910 911 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION: 912 status = intel_fcs_close_crypto_service_session(x1, &mbox_error); 913 SMC_RET2(handle, status, mbox_error); 914 915 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY: 916 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id); 917 SMC_RET1(handle, status); 918 919 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY: 920 status = intel_fcs_export_crypto_service_key(x1, x2, x3, 921 (uint32_t *) &x4, &mbox_error); 922 SMC_RET4(handle, status, mbox_error, x3, x4); 923 924 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY: 925 status = intel_fcs_remove_crypto_service_key(x1, x2, 926 &mbox_error); 927 SMC_RET2(handle, status, mbox_error); 928 929 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO: 930 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3, 931 (uint32_t *) &x4, &mbox_error); 932 SMC_RET4(handle, status, mbox_error, x3, x4); 933 934 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT: 935 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 936 status = intel_fcs_get_digest_init(x1, x2, x3, 937 x4, x5, &mbox_error); 938 SMC_RET2(handle, status, mbox_error); 939 940 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE: 941 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 942 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 943 status = intel_fcs_get_digest_update_finalize(x1, x2, x3, 944 x4, x5, (uint32_t *) &x6, false, 945 &mbox_error); 946 SMC_RET4(handle, status, mbox_error, x5, x6); 947 948 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE: 949 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 950 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 951 status = intel_fcs_get_digest_update_finalize(x1, x2, x3, 952 x4, x5, (uint32_t *) &x6, true, 953 &mbox_error); 954 SMC_RET4(handle, status, mbox_error, x5, x6); 955 956 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE: 957 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 958 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 959 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 960 x4, x5, (uint32_t *) &x6, false, 961 &mbox_error, &send_id); 962 SMC_RET4(handle, status, mbox_error, x5, x6); 963 964 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE: 965 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 966 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 967 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 968 x4, x5, (uint32_t *) &x6, true, 969 &mbox_error, &send_id); 970 SMC_RET4(handle, status, mbox_error, x5, x6); 971 972 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT: 973 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 974 status = intel_fcs_mac_verify_init(x1, x2, x3, 975 x4, x5, &mbox_error); 976 SMC_RET2(handle, status, mbox_error); 977 978 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE: 979 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 980 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 981 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 982 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, 983 x4, x5, (uint32_t *) &x6, x7, 984 false, &mbox_error); 985 SMC_RET4(handle, status, mbox_error, x5, x6); 986 987 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE: 988 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 989 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 990 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 991 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, 992 x4, x5, (uint32_t *) &x6, x7, 993 true, &mbox_error); 994 SMC_RET4(handle, status, mbox_error, x5, x6); 995 996 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE: 997 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 998 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 999 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1000 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 1001 x4, x5, (uint32_t *) &x6, x7, 1002 false, &mbox_error, &send_id); 1003 SMC_RET4(handle, status, mbox_error, x5, x6); 1004 1005 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE: 1006 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1007 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1008 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1009 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 1010 x4, x5, (uint32_t *) &x6, x7, 1011 true, &mbox_error, &send_id); 1012 SMC_RET4(handle, status, mbox_error, x5, x6); 1013 1014 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 1015 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1016 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3, 1017 x4, x5, &mbox_error); 1018 SMC_RET2(handle, status, mbox_error); 1019 1020 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 1021 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1022 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1023 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 1024 x3, x4, x5, (uint32_t *) &x6, false, 1025 &mbox_error); 1026 SMC_RET4(handle, status, mbox_error, x5, x6); 1027 1028 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 1029 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1030 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1031 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 1032 x3, x4, x5, (uint32_t *) &x6, true, 1033 &mbox_error); 1034 SMC_RET4(handle, status, mbox_error, x5, x6); 1035 1036 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE: 1037 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1038 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1039 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 1040 x2, x3, x4, x5, (uint32_t *) &x6, false, 1041 &mbox_error, &send_id); 1042 SMC_RET4(handle, status, mbox_error, x5, x6); 1043 1044 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE: 1045 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1046 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1047 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 1048 x2, x3, x4, x5, (uint32_t *) &x6, true, 1049 &mbox_error, &send_id); 1050 SMC_RET4(handle, status, mbox_error, x5, x6); 1051 1052 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT: 1053 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1054 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3, 1055 x4, x5, &mbox_error); 1056 SMC_RET2(handle, status, mbox_error); 1057 1058 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE: 1059 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1060 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1061 status = intel_fcs_ecdsa_hash_sign_finalize(x1, x2, x3, 1062 x4, x5, (uint32_t *) &x6, &mbox_error); 1063 SMC_RET4(handle, status, mbox_error, x5, x6); 1064 1065 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 1066 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1067 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3, 1068 x4, x5, &mbox_error); 1069 SMC_RET2(handle, status, mbox_error); 1070 1071 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 1072 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1073 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1074 status = intel_fcs_ecdsa_hash_sig_verify_finalize(x1, x2, x3, 1075 x4, x5, (uint32_t *) &x6, &mbox_error); 1076 SMC_RET4(handle, status, mbox_error, x5, x6); 1077 1078 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 1079 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1080 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3, 1081 x4, x5, &mbox_error); 1082 SMC_RET2(handle, status, mbox_error); 1083 1084 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 1085 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1086 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1087 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1088 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1089 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1090 x7, false, &mbox_error); 1091 SMC_RET4(handle, status, mbox_error, x5, x6); 1092 1093 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE: 1094 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1095 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1096 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1097 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 1098 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1099 x7, false, &mbox_error, &send_id); 1100 SMC_RET4(handle, status, mbox_error, x5, x6); 1101 1102 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE: 1103 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1104 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1105 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1106 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 1107 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1108 x7, true, &mbox_error, &send_id); 1109 SMC_RET4(handle, status, mbox_error, x5, x6); 1110 1111 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 1112 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1113 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1114 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1115 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1116 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1117 x7, true, &mbox_error); 1118 SMC_RET4(handle, status, mbox_error, x5, x6); 1119 1120 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT: 1121 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1122 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3, 1123 x4, x5, &mbox_error); 1124 SMC_RET2(handle, status, mbox_error); 1125 1126 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 1127 status = intel_fcs_ecdsa_get_pubkey_finalize(x1, x2, x3, 1128 (uint32_t *) &x4, &mbox_error); 1129 SMC_RET4(handle, status, mbox_error, x3, x4); 1130 1131 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT: 1132 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1133 status = intel_fcs_ecdh_request_init(x1, x2, x3, 1134 x4, x5, &mbox_error); 1135 SMC_RET2(handle, status, mbox_error); 1136 1137 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE: 1138 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1139 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1140 status = intel_fcs_ecdh_request_finalize(x1, x2, x3, 1141 x4, x5, (uint32_t *) &x6, &mbox_error); 1142 SMC_RET4(handle, status, mbox_error, x5, x6); 1143 1144 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT: 1145 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1146 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5, 1147 &mbox_error); 1148 SMC_RET2(handle, status, mbox_error); 1149 1150 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE: 1151 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1152 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1153 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1154 x5, x6, false, &send_id); 1155 SMC_RET1(handle, status); 1156 1157 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE: 1158 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1159 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1160 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1161 x5, x6, true, &send_id); 1162 SMC_RET1(handle, status); 1163 1164 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 1165 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 1166 &mbox_error); 1167 SMC_RET4(handle, status, mbox_error, x1, retval64); 1168 1169 case INTEL_SIP_SMC_SVC_VERSION: 1170 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 1171 SIP_SVC_VERSION_MAJOR, 1172 SIP_SVC_VERSION_MINOR); 1173 1174 default: 1175 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 1176 cookie, handle, flags); 1177 } 1178 } 1179 1180 uintptr_t sip_smc_handler(uint32_t smc_fid, 1181 u_register_t x1, 1182 u_register_t x2, 1183 u_register_t x3, 1184 u_register_t x4, 1185 void *cookie, 1186 void *handle, 1187 u_register_t flags) 1188 { 1189 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK; 1190 1191 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN && 1192 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) { 1193 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4, 1194 cookie, handle, flags); 1195 } else { 1196 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4, 1197 cookie, handle, flags); 1198 } 1199 } 1200 1201 DECLARE_RT_SVC( 1202 socfpga_sip_svc, 1203 OEN_SIP_START, 1204 OEN_SIP_END, 1205 SMC_TYPE_FAST, 1206 NULL, 1207 sip_smc_handler 1208 ); 1209 1210 DECLARE_RT_SVC( 1211 socfpga_sip_svc_std, 1212 OEN_SIP_START, 1213 OEN_SIP_END, 1214 SMC_TYPE_YIELD, 1215 NULL, 1216 sip_smc_handler 1217 ); 1218