1 /* 2 * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP2_DEF_H 8 #define STM32MP2_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #ifndef __ASSEMBLER__ 12 #include <drivers/st/bsec.h> 13 #endif 14 #include <drivers/st/stm32mp25_rcc.h> 15 #ifndef __ASSEMBLER__ 16 #include <drivers/st/stm32mp2_clk.h> 17 #endif 18 #include <drivers/st/stm32mp2_pwr.h> 19 #include <dt-bindings/clock/stm32mp25-clks.h> 20 #include <dt-bindings/clock/stm32mp25-clksrc.h> 21 #include <dt-bindings/gpio/stm32-gpio.h> 22 #include <dt-bindings/reset/stm32mp25-resets.h> 23 24 #ifndef __ASSEMBLER__ 25 #include <boot_api.h> 26 #include <stm32mp2_private.h> 27 #include <stm32mp_common.h> 28 #include <stm32mp_dt.h> 29 #include <stm32mp_shared_resources.h> 30 #endif 31 32 /******************************************************************************* 33 * CHIP ID 34 ******************************************************************************/ 35 #define STM32MP2_CHIP_ID U(0x505) 36 37 #define STM32MP251A_PART_NB U(0x400B3E6D) 38 #define STM32MP251C_PART_NB U(0x000B306D) 39 #define STM32MP251D_PART_NB U(0xC00B3E6D) 40 #define STM32MP251F_PART_NB U(0x800B306D) 41 #define STM32MP253A_PART_NB U(0x400B3E0C) 42 #define STM32MP253C_PART_NB U(0x000B300C) 43 #define STM32MP253D_PART_NB U(0xC00B3E0C) 44 #define STM32MP253F_PART_NB U(0x800B300C) 45 #define STM32MP255A_PART_NB U(0x40082E00) 46 #define STM32MP255C_PART_NB U(0x00082000) 47 #define STM32MP255D_PART_NB U(0xC0082E00) 48 #define STM32MP255F_PART_NB U(0x80082000) 49 #define STM32MP257A_PART_NB U(0x40002E00) 50 #define STM32MP257C_PART_NB U(0x00002000) 51 #define STM32MP257D_PART_NB U(0xC0002E00) 52 #define STM32MP257F_PART_NB U(0x80002000) 53 54 #define STM32MP2_REV_A U(0x08) 55 #define STM32MP2_REV_B U(0x10) 56 #define STM32MP2_REV_X U(0x12) 57 #define STM32MP2_REV_Y U(0x11) 58 #define STM32MP2_REV_Z U(0x09) 59 60 /******************************************************************************* 61 * PACKAGE ID 62 ******************************************************************************/ 63 #define STM32MP25_PKG_CUSTOM U(0) 64 #define STM32MP25_PKG_AL_VFBGA361 U(1) 65 #define STM32MP25_PKG_AK_VFBGA424 U(3) 66 #define STM32MP25_PKG_AI_TFBGA436 U(5) 67 #define STM32MP25_PKG_UNKNOWN U(7) 68 69 /******************************************************************************* 70 * STM32MP2 memory map related constants 71 ******************************************************************************/ 72 #define STM32MP_SYSRAM_BASE U(0x0E000000) 73 #define STM32MP_SYSRAM_SIZE U(0x00040000) 74 75 /* DDR configuration */ 76 #define STM32MP_DDR_BASE U(0x80000000) 77 #define STM32MP_DDR_MAX_SIZE UL(0x100000000) /* Max 4GB */ 78 79 /* DDR power initializations */ 80 #ifndef __ASSEMBLER__ 81 enum ddr_type { 82 STM32MP_DDR3, 83 STM32MP_DDR4, 84 STM32MP_LPDDR4 85 }; 86 #endif 87 88 /* Section used inside TF binaries */ 89 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */ 90 /* 512 Bytes reserved for header */ 91 #define STM32MP_HEADER_SIZE U(0x00000200) 92 #define STM32MP_HEADER_BASE (STM32MP_SYSRAM_BASE + \ 93 STM32MP_PARAM_LOAD_SIZE) 94 95 /* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */ 96 #define STM32MP_HEADER_RESERVED_SIZE U(0x3000) 97 98 #define STM32MP_BINARY_BASE (STM32MP_SYSRAM_BASE + \ 99 STM32MP_PARAM_LOAD_SIZE + \ 100 STM32MP_HEADER_SIZE) 101 102 #define STM32MP_BINARY_SIZE (STM32MP_SYSRAM_SIZE - \ 103 (STM32MP_PARAM_LOAD_SIZE + \ 104 STM32MP_HEADER_SIZE)) 105 106 #define STM32MP_BL2_RO_SIZE U(0x00020000) /* 128 KB */ 107 #define STM32MP_BL2_SIZE U(0x00029000) /* 164 KB for BL2 */ 108 109 #define STM32MP_BL2_BASE (STM32MP_SYSRAM_BASE + \ 110 STM32MP_SYSRAM_SIZE - \ 111 STM32MP_BL2_SIZE) 112 113 #define STM32MP_BL2_RO_BASE STM32MP_BL2_BASE 114 115 #define STM32MP_BL2_RW_BASE (STM32MP_BL2_RO_BASE + \ 116 STM32MP_BL2_RO_SIZE) 117 118 #define STM32MP_BL2_RW_SIZE (STM32MP_SYSRAM_BASE + \ 119 STM32MP_SYSRAM_SIZE - \ 120 STM32MP_BL2_RW_BASE) 121 122 /* BL2 and BL32/sp_min require 4 tables */ 123 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */ 124 125 /* 126 * MAX_MMAP_REGIONS is usually: 127 * BL stm32mp2_mmap size + mmap regions in *_plat_arch_setup 128 */ 129 #define MAX_MMAP_REGIONS 6 130 131 /* DTB initialization value */ 132 #define STM32MP_BL2_DTB_SIZE U(0x00006000) /* 24 KB for DTB */ 133 134 #define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \ 135 STM32MP_BL2_DTB_SIZE) 136 137 #if defined(IMAGE_BL2) 138 #define STM32MP_DTB_SIZE STM32MP_BL2_DTB_SIZE 139 #define STM32MP_DTB_BASE STM32MP_BL2_DTB_BASE 140 #endif 141 142 #define STM32MP_FW_CONFIG_MAX_SIZE PAGE_SIZE 143 #define STM32MP_FW_CONFIG_BASE STM32MP_SYSRAM_BASE 144 145 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x04000000)) 146 #define STM32MP_BL33_MAX_SIZE U(0x400000) 147 #define STM32MP_HW_CONFIG_BASE (STM32MP_BL33_BASE + \ 148 STM32MP_BL33_MAX_SIZE) 149 #define STM32MP_HW_CONFIG_MAX_SIZE U(0x40000) 150 151 /******************************************************************************* 152 * STM32MP2 device/io map related constants (used for MMU) 153 ******************************************************************************/ 154 #define STM32MP_DEVICE_BASE U(0x40000000) 155 #define STM32MP_DEVICE_SIZE U(0x40000000) 156 157 /******************************************************************************* 158 * STM32MP2 RCC 159 ******************************************************************************/ 160 #define RCC_BASE U(0x44200000) 161 162 /******************************************************************************* 163 * STM32MP2 PWR 164 ******************************************************************************/ 165 #define PWR_BASE U(0x44210000) 166 167 /******************************************************************************* 168 * STM32MP2 GPIO 169 ******************************************************************************/ 170 #define GPIOA_BASE U(0x44240000) 171 #define GPIOB_BASE U(0x44250000) 172 #define GPIOC_BASE U(0x44260000) 173 #define GPIOD_BASE U(0x44270000) 174 #define GPIOE_BASE U(0x44280000) 175 #define GPIOF_BASE U(0x44290000) 176 #define GPIOG_BASE U(0x442A0000) 177 #define GPIOH_BASE U(0x442B0000) 178 #define GPIOI_BASE U(0x442C0000) 179 #define GPIOJ_BASE U(0x442D0000) 180 #define GPIOK_BASE U(0x442E0000) 181 #define GPIOZ_BASE U(0x46200000) 182 #define GPIO_BANK_OFFSET U(0x10000) 183 184 #define STM32MP_GPIOS_PIN_MAX_COUNT 16 185 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 186 187 /******************************************************************************* 188 * STM32MP2 UART 189 ******************************************************************************/ 190 #define USART1_BASE U(0x40330000) 191 #define USART2_BASE U(0x400E0000) 192 #define USART3_BASE U(0x400F0000) 193 #define UART4_BASE U(0x40100000) 194 #define UART5_BASE U(0x40110000) 195 #define USART6_BASE U(0x40220000) 196 #define UART7_BASE U(0x40370000) 197 #define UART8_BASE U(0x40380000) 198 #define UART9_BASE U(0x402C0000) 199 #define STM32MP_NB_OF_UART U(9) 200 201 /* For UART crash console */ 202 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 203 /* USART2 on HSI@64MHz, TX on GPIOA4 Alternate 6 */ 204 #define STM32MP_DEBUG_USART_BASE USART2_BASE 205 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOA_BASE 206 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_GPIOACFGR 207 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_GPIOxCFGR_GPIOxEN 208 #define DEBUG_UART_TX_GPIO_PORT 4 209 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 210 #define DEBUG_UART_TX_CLKSRC_REG RCC_XBAR8CFGR 211 #define DEBUG_UART_TX_CLKSRC XBAR_SRC_HSI 212 #define DEBUG_UART_TX_EN_REG RCC_USART2CFGR 213 #define DEBUG_UART_TX_EN RCC_UARTxCFGR_UARTxEN 214 #define DEBUG_UART_RST_REG RCC_USART2CFGR 215 #define DEBUG_UART_RST_BIT RCC_UARTxCFGR_UARTxRST 216 #define DEBUG_UART_PREDIV_CFGR RCC_PREDIV8CFGR 217 #define DEBUG_UART_FINDIV_CFGR RCC_FINDIV8CFGR 218 219 /******************************************************************************* 220 * STM32MP2 SDMMC 221 ******************************************************************************/ 222 #define STM32MP_SDMMC1_BASE U(0x48220000) 223 #define STM32MP_SDMMC2_BASE U(0x48230000) 224 #define STM32MP_SDMMC3_BASE U(0x48240000) 225 226 /******************************************************************************* 227 * STM32MP2 BSEC / OTP 228 ******************************************************************************/ 229 /* 230 * 367 available OTPs, the other are masked 231 * - ECIES key: 368 to 375 (only readable by bootrom) 232 * - HWKEY: 376 to 383 (never reloadable or readable) 233 */ 234 #define STM32MP2_OTP_MAX_ID U(0x16F) 235 #define STM32MP2_MID_OTP_START U(0x80) 236 #define STM32MP2_UPPER_OTP_START U(0x100) 237 238 /* OTP labels */ 239 #define PART_NUMBER_OTP "part-number-otp" 240 #define REVISION_OTP "rev_otp" 241 #define PACKAGE_OTP "package-otp" 242 #define HCONF1_OTP "otp124" 243 #define NAND_OTP "otp16" 244 #define NAND2_OTP "otp20" 245 #define BOARD_ID_OTP "board-id" 246 #define UID_OTP "uid-otp" 247 #define LIFECYCLE2_OTP "otp18" 248 #define PKH_OTP "otp144" 249 #define ENCKEY_OTP "otp260" 250 251 /* OTP mask */ 252 /* PACKAGE */ 253 #define PACKAGE_OTP_PKG_MASK GENMASK_32(2, 0) 254 #define PACKAGE_OTP_PKG_SHIFT U(0) 255 256 /* IWDG OTP */ 257 #define HCONF1_OTP_IWDG_HW_POS U(0) 258 #define HCONF1_OTP_IWDG_FZ_STOP_POS U(1) 259 #define HCONF1_OTP_IWDG_FZ_STANDBY_POS U(2) 260 261 /* NAND OTP */ 262 /* NAND parameter storage flag */ 263 #define NAND_PARAM_STORED_IN_OTP BIT_32(31) 264 265 /* NAND page size in bytes */ 266 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29) 267 #define NAND_PAGE_SIZE_SHIFT U(29) 268 #define NAND_PAGE_SIZE_2K U(0) 269 #define NAND_PAGE_SIZE_4K U(1) 270 #define NAND_PAGE_SIZE_8K U(2) 271 272 /* NAND block size in pages */ 273 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27) 274 #define NAND_BLOCK_SIZE_SHIFT U(27) 275 #define NAND_BLOCK_SIZE_64_PAGES U(0) 276 #define NAND_BLOCK_SIZE_128_PAGES U(1) 277 #define NAND_BLOCK_SIZE_256_PAGES U(2) 278 279 /* NAND number of block (in unit of 256 blocks) */ 280 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19) 281 #define NAND_BLOCK_NB_SHIFT U(19) 282 #define NAND_BLOCK_NB_UNIT U(256) 283 284 /* NAND bus width in bits */ 285 #define NAND_WIDTH_MASK BIT_32(18) 286 #define NAND_WIDTH_SHIFT U(18) 287 288 /* NAND number of ECC bits per 512 bytes */ 289 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15) 290 #define NAND_ECC_BIT_NB_SHIFT U(15) 291 #define NAND_ECC_BIT_NB_UNSET U(0) 292 #define NAND_ECC_BIT_NB_1_BITS U(1) 293 #define NAND_ECC_BIT_NB_4_BITS U(2) 294 #define NAND_ECC_BIT_NB_8_BITS U(3) 295 #define NAND_ECC_ON_DIE U(4) 296 297 /* NAND number of planes */ 298 #define NAND_PLANE_BIT_NB_MASK BIT_32(14) 299 300 /* NAND2 OTP */ 301 #define NAND2_PAGE_SIZE_SHIFT U(16) 302 303 /* NAND2 config distribution */ 304 #define NAND2_CONFIG_DISTRIB BIT_32(0) 305 #define NAND2_PNAND_NAND2_SNAND_NAND1 U(0) 306 #define NAND2_PNAND_NAND1_SNAND_NAND2 U(1) 307 308 /* MONOTONIC OTP */ 309 #define MAX_MONOTONIC_VALUE U(32) 310 311 /* UID OTP */ 312 #define UID_WORD_NB U(3) 313 314 /* Lifecycle OTP */ 315 #define SECURE_BOOT_CLOSED_SECURE GENMASK_32(3, 0) 316 317 /******************************************************************************* 318 * STM32MP2 TAMP 319 ******************************************************************************/ 320 #define PLAT_MAX_TAMP_INT U(5) 321 #define PLAT_MAX_TAMP_EXT U(3) 322 #define TAMP_BASE U(0x46010000) 323 #define TAMP_SMCR (TAMP_BASE + U(0x20)) 324 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 325 #define TAMP_BKP_REG_CLK CK_BUS_RTC 326 #define TAMP_BKP_SEC_NUMBER U(10) 327 #define TAMP_COUNTR U(0x40) 328 329 #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) 330 static inline uintptr_t tamp_bkpr(uint32_t idx) 331 { 332 return TAMP_BKP_REGISTER_BASE + (idx << 2); 333 } 334 #endif 335 336 /******************************************************************************* 337 * STM32MP2 DDRCTRL 338 ******************************************************************************/ 339 #define DDRCTRL_BASE U(0x48040000) 340 341 /******************************************************************************* 342 * STM32MP2 DDRDBG 343 ******************************************************************************/ 344 #define DDRDBG_BASE U(0x48050000) 345 346 /******************************************************************************* 347 * STM32MP2 DDRPHYC 348 ******************************************************************************/ 349 #define DDRPHYC_BASE U(0x48C00000) 350 351 /******************************************************************************* 352 * Miscellaneous STM32MP1 peripherals base address 353 ******************************************************************************/ 354 #define BSEC_BASE U(0x44000000) 355 #define DBGMCU_BASE U(0x4A010000) 356 #define HASH_BASE U(0x42010000) 357 #define RTC_BASE U(0x46000000) 358 #define STGEN_BASE U(0x48080000) 359 #define SYSCFG_BASE U(0x44230000) 360 361 /******************************************************************************* 362 * STM32MP CA35SSC 363 ******************************************************************************/ 364 #define A35SSC_BASE U(0x48800000) 365 366 /******************************************************************************* 367 * REGULATORS 368 ******************************************************************************/ 369 /* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */ 370 #define PLAT_NB_RDEVS U(19) 371 /* 2 FIXED */ 372 #define PLAT_NB_FIXED_REGUS U(2) 373 /* No GPIO regu */ 374 #define PLAT_NB_GPIO_REGUS U(0) 375 376 /******************************************************************************* 377 * Device Tree defines 378 ******************************************************************************/ 379 #define DT_BSEC_COMPAT "st,stm32mp25-bsec" 380 #define DT_DDR_COMPAT "st,stm32mp2-ddr" 381 #define DT_PWR_COMPAT "st,stm32mp25-pwr" 382 #define DT_RCC_CLK_COMPAT "st,stm32mp25-rcc" 383 #define DT_SDMMC2_COMPAT "st,stm32mp25-sdmmc2" 384 #define DT_UART_COMPAT "st,stm32h7-uart" 385 386 #endif /* STM32MP2_DEF_H */ 387