1/* 2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/* If SCMI power domain control is enabled */ 8#if TC_SCMI_PD_CTRL_EN 9#define GPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 1) 10#define DPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 2) 11#endif /* TC_SCMI_PD_CTRL_EN */ 12 13/* Use SCMI controlled clocks */ 14#if TC_DPU_USE_SCMI_CLK 15#define DPU_CLK_ATTR1 \ 16 clocks = <&scmi_clk 0>; \ 17 clock-names = "aclk" 18 19#define DPU_CLK_ATTR2 \ 20 clocks = <&scmi_clk 1>; \ 21 clock-names = "pxclk" 22 23#define DPU_CLK_ATTR3 \ 24 clocks = <&scmi_clk 2>; \ 25 clock-names = "pxclk" \ 26/* Use fixed clocks */ 27#else /* !TC_DPU_USE_SCMI_CLK */ 28#define DPU_CLK_ATTR1 \ 29 clocks = <&dpu_aclk>; \ 30 clock-names = "aclk" 31 32#define DPU_CLK_ATTR2 \ 33 clocks = <&dpu_pixel_clk>, <&dpu_aclk>; \ 34 clock-names = "pxclk", "aclk" 35 36#define DPU_CLK_ATTR3 DPU_CLK_ATTR2 37#endif /* !TC_DPU_USE_SCMI_CLK */ 38 39/ { 40 compatible = "arm,tc"; 41 interrupt-parent = <&gic>; 42 #address-cells = <2>; 43 #size-cells = <2>; 44 45 aliases { 46 serial0 = &os_uart; 47 }; 48 49 chosen { 50 /* 51 * Add some dummy entropy for Linux so it 52 * doesn't delay the boot waiting for it. 53 */ 54 rng-seed = <0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 55 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 56 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 57 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 58 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 59 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 60 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 61 0x01 0x02 0x04 0x05 0x06 0x07 0x08 >; 62 }; 63 64 cpus { 65 #address-cells = <1>; 66 #size-cells = <0>; 67 68 cpu-map { 69 cluster0 { 70 core0 { 71 cpu = <&CPU0>; 72 }; 73 core1 { 74 cpu = <&CPU1>; 75 }; 76 core2 { 77 cpu = <&CPU2>; 78 }; 79 core3 { 80 cpu = <&CPU3>; 81 }; 82 core4 { 83 cpu = <&CPU4>; 84 }; 85 core5 { 86 cpu = <&CPU5>; 87 }; 88 core6 { 89 cpu = <&CPU6>; 90 }; 91 core7 { 92 cpu = <&CPU7>; 93 }; 94 }; 95 }; 96 97 /* 98 * The timings below are just to demonstrate working cpuidle. 99 * These values may be inaccurate. 100 */ 101 idle-states { 102 entry-method = "psci"; 103 104 CPU_SLEEP_0: cpu-sleep-0 { 105 compatible = "arm,idle-state"; 106 arm,psci-suspend-param = <0x0010000>; 107 local-timer-stop; 108 entry-latency-us = <300>; 109 exit-latency-us = <1200>; 110 min-residency-us = <2000>; 111 }; 112 CLUSTER_SLEEP_0: cluster-sleep-0 { 113 compatible = "arm,idle-state"; 114 arm,psci-suspend-param = <0x1010000>; 115 local-timer-stop; 116 entry-latency-us = <400>; 117 exit-latency-us = <1200>; 118 min-residency-us = <2500>; 119 }; 120 }; 121 122 amus { 123 amu: amu-0 { 124 #address-cells = <1>; 125 #size-cells = <0>; 126 127 mpmm_gear0: counter@0 { 128 reg = <0>; 129 enable-at-el3; 130 }; 131 132 mpmm_gear1: counter@1 { 133 reg = <1>; 134 enable-at-el3; 135 }; 136 137 mpmm_gear2: counter@2 { 138 reg = <2>; 139 enable-at-el3; 140 }; 141 }; 142 }; 143 144 CPU0:cpu@0 { 145 device_type = "cpu"; 146 compatible = "arm,armv8"; 147 reg = <0x0>; 148 enable-method = "psci"; 149 clocks = <&scmi_dvfs 0>; 150 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 151 capacity-dmips-mhz = <LIT_CAPACITY>; 152 amu = <&amu>; 153 supports-mpmm; 154 }; 155 156 CPU1:cpu@100 { 157 device_type = "cpu"; 158 compatible = "arm,armv8"; 159 reg = <0x100>; 160 enable-method = "psci"; 161 clocks = <&scmi_dvfs 0>; 162 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 163 capacity-dmips-mhz = <LIT_CAPACITY>; 164 amu = <&amu>; 165 supports-mpmm; 166 }; 167 168 CPU2:cpu@200 { 169 device_type = "cpu"; 170 compatible = "arm,armv8"; 171 reg = <0x200>; 172 enable-method = "psci"; 173 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 174 amu = <&amu>; 175 supports-mpmm; 176 }; 177 178 CPU3:cpu@300 { 179 device_type = "cpu"; 180 compatible = "arm,armv8"; 181 reg = <0x300>; 182 enable-method = "psci"; 183 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 184 amu = <&amu>; 185 supports-mpmm; 186 }; 187 188 CPU4:cpu@400 { 189 device_type = "cpu"; 190 compatible = "arm,armv8"; 191 reg = <0x400>; 192 enable-method = "psci"; 193 clocks = <&scmi_dvfs 1>; 194 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 195 capacity-dmips-mhz = <MID_CAPACITY>; 196 amu = <&amu>; 197 supports-mpmm; 198 }; 199 200 CPU5:cpu@500 { 201 device_type = "cpu"; 202 compatible = "arm,armv8"; 203 reg = <0x500>; 204 enable-method = "psci"; 205 clocks = <&scmi_dvfs 1>; 206 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 207 capacity-dmips-mhz = <MID_CAPACITY>; 208 amu = <&amu>; 209 supports-mpmm; 210 }; 211 212 CPU6:cpu@600 { 213 device_type = "cpu"; 214 compatible = "arm,armv8"; 215 reg = <0x600>; 216 enable-method = "psci"; 217 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 218 amu = <&amu>; 219 supports-mpmm; 220 }; 221 222 CPU7:cpu@700 { 223 device_type = "cpu"; 224 compatible = "arm,armv8"; 225 reg = <0x700>; 226 enable-method = "psci"; 227 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 228 amu = <&amu>; 229 supports-mpmm; 230 }; 231 }; 232 233 reserved-memory { 234 #address-cells = <2>; 235 #size-cells = <2>; 236 ranges; 237 238 linux,cma { 239 compatible = "shared-dma-pool"; 240 reusable; 241 size = <0x0 0x8000000>; 242 linux,cma-default; 243 }; 244 245 optee { 246 compatible = "restricted-dma-pool"; 247 reg = <0x0 TC_NS_OPTEE_BASE 0x0 TC_NS_OPTEE_SIZE>; 248 }; 249 250 fwu_mm { 251 reg = <0x0 TC_NS_FWU_BASE 0x0 TC_NS_FWU_SIZE>; 252 no-map; 253 }; 254 }; 255 256 memory { 257 device_type = "memory"; 258 reg = <0x0 TC_NS_DRAM1_BASE 0x0 TC_NS_DRAM1_SIZE>, 259 <HI(PLAT_ARM_DRAM2_BASE) LO(PLAT_ARM_DRAM2_BASE) 260 HI(TC_NS_DRAM2_SIZE) LO(TC_NS_DRAM2_SIZE)>; 261 }; 262 263 psci { 264 compatible = "arm,psci-1.0", "arm,psci-0.2"; 265 method = "smc"; 266 }; 267 268 cpu-pmu-little { 269 compatible = LIT_CPU_PMU_COMPATIBLE; 270 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition_little>; 271 status = "okay"; 272 }; 273 274 cpu-pmu-mid { 275 compatible = MID_CPU_PMU_COMPATIBLE; 276 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition_mid>; 277 status = "okay"; 278 }; 279 280 cpu-pmu-big { 281 compatible = BIG_CPU_PMU_COMPATIBLE; 282 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition_big>; 283 status = "okay"; 284 }; 285 286 sram: sram@6000000 { 287 compatible = "mmio-sram"; 288 reg = <0x0 PLAT_ARM_NSRAM_BASE 0x0 PLAT_ARM_NSRAM_SIZE>; 289 290 #address-cells = <1>; 291 #size-cells = <1>; 292 ranges = <0 0x0 PLAT_ARM_NSRAM_BASE PLAT_ARM_NSRAM_SIZE>; 293 294 cpu_scp_scmi_a2p: scp-shmem@0 { 295 compatible = "arm,scmi-shmem"; 296 reg = <0x0 0x80>; 297 }; 298 }; 299 300 mbox_db_rx: mhu@MHU_RX_ADDR { 301 compatible = MHU_RX_COMPAT; 302 reg = <0x0 ADDRESSIFY(MHU_RX_ADDR) 0x0 MHU_OFFSET>; 303 clocks = <&soc_refclk>; 304 clock-names = "apb_pclk"; 305 #mbox-cells = <MHU_MBOX_CELLS>; 306 interrupts = <GIC_SPI MHU_RX_INT_NUM IRQ_TYPE_LEVEL_HIGH 0>; 307 interrupt-names = MHU_RX_INT_NAME; 308 }; 309 310 mbox_db_tx: mhu@MHU_TX_ADDR { 311 compatible = MHU_TX_COMPAT; 312 reg = <0x0 ADDRESSIFY(MHU_TX_ADDR) 0x0 MHU_OFFSET>; 313 clocks = <&soc_refclk>; 314 clock-names = "apb_pclk"; 315 #mbox-cells = <MHU_MBOX_CELLS>; 316 interrupt-names = MHU_TX_INT_NAME; 317 }; 318 319 firmware { 320 scmi { 321 compatible = "arm,scmi"; 322 mbox-names = "tx", "rx"; 323 #address-cells = <1>; 324 #size-cells = <0>; 325 326#if TC_SCMI_PD_CTRL_EN 327 scmi_devpd: protocol@11 { 328 reg = <0x11>; 329 #power-domain-cells = <1>; 330 }; 331#endif /* TC_SCMI_PD_CTRL_EN */ 332 333 scmi_dvfs: protocol@13 { 334 reg = <0x13>; 335 #clock-cells = <1>; 336 }; 337 338 scmi_clk: protocol@14 { 339 reg = <0x14>; 340 #clock-cells = <1>; 341 }; 342 }; 343 }; 344 345 gic: interrupt-controller@GIC_CTRL_ADDR { 346 compatible = "arm,gic-v3"; 347 #address-cells = <2>; 348 #interrupt-cells = <4>; 349 #size-cells = <2>; 350 ranges; 351 interrupt-controller; 352 reg = <0x0 0x30000000 0 0x10000>, /* GICD */ 353 <0x0 0x30080000 0 GIC_GICR_OFFSET>; /* GICR */ 354 interrupts = <GIC_PPI 0x9 IRQ_TYPE_LEVEL_LOW 0>; 355 }; 356 357 timer { 358 compatible = "arm,armv8-timer"; 359 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 360 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 361 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 362 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 363 }; 364 365 spe-pmu-mid { 366 compatible = "arm,statistical-profiling-extension-v1"; 367 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_HIGH &ppi_partition_mid>; 368 status = "disabled"; 369 }; 370 371 spe-pmu-big { 372 compatible = "arm,statistical-profiling-extension-v1"; 373 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_HIGH &ppi_partition_big>; 374 status = "disabled"; 375 }; 376 377 soc_refclk: refclk { 378 compatible = "fixed-clock"; 379 #clock-cells = <0>; 380 clock-frequency = <1000000000>; 381 clock-output-names = "apb_pclk"; 382 }; 383 384 soc_refclk60mhz: refclk60mhz { 385 compatible = "fixed-clock"; 386 #clock-cells = <0>; 387 clock-frequency = <60000000>; 388 clock-output-names = "iofpga_clk"; 389 }; 390 391 soc_uartclk: uartclk { 392 compatible = "fixed-clock"; 393 #clock-cells = <0>; 394 clock-frequency = <UARTCLK_FREQ>; 395 clock-output-names = "uartclk"; 396 }; 397 398 /* soc_uart0 on FPGA, ap_ns_uart on FVP */ 399 os_uart: serial@2a400000 { 400 compatible = "arm,pl011", "arm,primecell"; 401 reg = <0x0 0x2A400000 0x0 UART_OFFSET>; 402 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH 0>; 403 clocks = <&soc_uartclk>, <&soc_refclk>; 404 clock-names = "uartclk", "apb_pclk"; 405 status = "okay"; 406 }; 407 408#if !TC_DPU_USE_SCMI_CLK 409 dpu_aclk: dpu_aclk { 410 compatible = "fixed-clock"; 411 #clock-cells = <0>; 412 clock-frequency = <VENCODER_TIMING_CLK>; 413 clock-output-names = "fpga:dpu_aclk"; 414 }; 415 416 dpu_pixel_clk: dpu-pixel-clk { 417 compatible = "fixed-clock"; 418 #clock-cells = <0>; 419 clock-frequency = <VENCODER_TIMING_CLK>; 420 clock-output-names = "pxclk"; 421 }; 422#endif /* !TC_DPU_USE_SCMI_CLK */ 423 424 vencoder { 425 compatible = "drm,virtual-encoder"; 426 port { 427 vencoder_in: endpoint { 428 remote-endpoint = <&dp_pl0_out0>; 429 }; 430 }; 431 432 display-timings { 433 timing-panel { 434 VENCODER_TIMING; 435 }; 436 }; 437 438 }; 439 440 ethernet: ethernet@18000000 { 441 reg = <0x0 0x18000000 0x0 0x10000>; 442 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 443 444 reg-io-width = <2>; 445 smsc,irq-push-pull; 446 }; 447 448 bp_clock24mhz: clock24mhz { 449 compatible = "fixed-clock"; 450 #clock-cells = <0>; 451 clock-frequency = <24000000>; 452 clock-output-names = "bp:clock24mhz"; 453 }; 454 455 456 sysreg: sysreg@1c010000 { 457 compatible = "arm,vexpress-sysreg"; 458 reg = <0x0 0x001c010000 0x0 0x1000>; 459 gpio-controller; 460 #gpio-cells = <2>; 461 }; 462 463 fixed_3v3: v2m-3v3 { 464 compatible = "regulator-fixed"; 465 regulator-name = "3V3"; 466 regulator-min-microvolt = <3300000>; 467 regulator-max-microvolt = <3300000>; 468 regulator-always-on; 469 }; 470 471 mmci: mmci@1c050000 { 472 compatible = "arm,pl180", "arm,primecell"; 473 reg = <0x0 0x001c050000 0x0 0x1000>; 474 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>, 475 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; 476 wp-gpios = <&sysreg 1 0>; 477 bus-width = <4>; 478 max-frequency = <25000000>; 479 vmmc-supply = <&fixed_3v3>; 480 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; 481 clock-names = "mclk", "apb_pclk"; 482 }; 483 484 gpu_clk: gpu_clk { 485 compatible = "fixed-clock"; 486 #clock-cells = <0>; 487 clock-frequency = <1000000000>; 488 }; 489 490 gpu_core_clk: gpu_core_clk { 491 compatible = "fixed-clock"; 492 #clock-cells = <0>; 493 clock-frequency = <1000000000>; 494 }; 495 496 gpu: gpu@2d000000 { 497 compatible = "arm,mali-midgard"; 498 reg = <0x0 0x2d000000 0x0 0x200000>; 499 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>, 500 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>, 501 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 502 interrupt-names = "JOB", "MMU", "GPU"; 503 clocks = <&gpu_core_clk>; 504 clock-names = "shadercores"; 505#if TC_SCMI_PD_CTRL_EN 506 power-domains = <&scmi_devpd GPU_SCMI_PD_IDX>; 507 scmi-perf-domain = <3>; 508#endif /* TC_SCMI_PD_CTRL_EN */ 509 510 pbha { 511 int-id-override = <0 0x22>, <2 0x23>, <4 0x23>, <7 0x22>, 512 <8 0x22>, <9 0x22>, <10 0x22>, <11 0x22>, 513 <12 0x22>, <13 0x22>, <16 0x22>, <17 0x32>, 514 <18 0x32>, <19 0x22>, <20 0x22>, <21 0x32>, 515 <22 0x32>, <24 0x22>, <28 0x32>; 516 propagate-bits = <0x0f>; 517 }; 518 }; 519 520 power_model_simple { 521 /* 522 * Numbers used are irrelevant to Titan, 523 * it helps suppressing the kernel warnings. 524 */ 525 compatible = "arm,mali-simple-power-model"; 526 static-coefficient = <2427750>; 527 dynamic-coefficient = <4687>; 528 ts = <20000 2000 (-20) 2>; 529 thermal-zone = ""; 530 }; 531 532 smmu_600: smmu@2ce00000 { 533 compatible = "arm,smmu-v3"; 534 reg = <0 0x2ce00000 0 0x20000>; 535 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING 0>, 536 <GIC_SPI 74 IRQ_TYPE_EDGE_RISING 0>, 537 <GIC_SPI 76 IRQ_TYPE_EDGE_RISING 0>, 538 <GIC_SPI 77 IRQ_TYPE_EDGE_RISING 0>; 539 interrupt-names = "eventq", "priq", "cmdq-sync", "gerror"; 540 #iommu-cells = <1>; 541 status = "disabled"; 542 }; 543 544 smmu_700: iommu@3f000000 { 545 #iommu-cells = <1>; 546 compatible = "arm,smmu-v3"; 547 reg = <0x0 0x3f000000 0x0 0x5000000>; 548 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING 0>, 549 <GIC_SPI 229 IRQ_TYPE_EDGE_RISING 0>, 550 <GIC_SPI 230 IRQ_TYPE_EDGE_RISING 0>; 551 interrupt-names = "eventq", "cmdq-sync", "gerror"; 552 dma-coherent; 553 status = "disabled"; 554 }; 555 556 smmu_700_dpu: iommu@4002a00000 { 557 #iommu-cells = <1>; 558 compatible = "arm,smmu-v3"; 559 reg = <HI(0x4002a00000) LO(0x4002a00000) 0x0 0x5000000>; 560 interrupts = <GIC_SPI 481 IRQ_TYPE_EDGE_RISING 0>, 561 <GIC_SPI 482 IRQ_TYPE_EDGE_RISING 0>, 562 <GIC_SPI 483 IRQ_TYPE_EDGE_RISING 0>; 563 interrupt-names = "eventq", "cmdq-sync", "gerror"; 564 dma-coherent; 565 status = "disabled"; 566 }; 567 568 dp0: display@DPU_ADDR { 569 #address-cells = <1>; 570 #size-cells = <0>; 571 compatible = "arm,mali-d71"; 572 reg = <HI(ADDRESSIFY(DPU_ADDR)) LO(ADDRESSIFY(DPU_ADDR)) 0 0x20000>; 573 interrupts = <GIC_SPI DPU_IRQ IRQ_TYPE_LEVEL_HIGH 0>; 574 interrupt-names = "DPU"; 575 DPU_CLK_ATTR1; 576 577 pl0: pipeline@0 { 578 reg = <0>; 579 DPU_CLK_ATTR2; 580 pl_id = <0>; 581 ports { 582 #address-cells = <1>; 583 #size-cells = <0>; 584 port@0 { 585 reg = <0>; 586 dp_pl0_out0: endpoint { 587 remote-endpoint = <&vencoder_in>; 588 }; 589 }; 590 }; 591 }; 592 593 pl1: pipeline@1 { 594 reg = <1>; 595 DPU_CLK_ATTR3; 596 pl_id = <1>; 597 ports { 598 #address-cells = <1>; 599 #size-cells = <0>; 600 port@0 { 601 reg = <0>; 602 }; 603 }; 604 }; 605 }; 606 607 /* 608 * L3 cache in the DSU is the Memory System Component (MSC) 609 * The MPAM registers are accessed through utility bus in the DSU 610 */ 611 msc0 { 612 compatible = "arm,mpam-msc"; 613 reg = <MPAM_ADDR 0x0 0x2000>; 614 }; 615 616 ete0 { 617 compatible = "arm,embedded-trace-extension"; 618 cpu = <&CPU0>; 619 }; 620 621 ete1 { 622 compatible = "arm,embedded-trace-extension"; 623 cpu = <&CPU1>; 624 }; 625 626 ete2 { 627 compatible = "arm,embedded-trace-extension"; 628 cpu = <&CPU2>; 629 }; 630 631 ete3 { 632 compatible = "arm,embedded-trace-extension"; 633 cpu = <&CPU3>; 634 }; 635 636 ete4 { 637 compatible = "arm,embedded-trace-extension"; 638 cpu = <&CPU4>; 639 }; 640 641 ete5 { 642 compatible = "arm,embedded-trace-extension"; 643 cpu = <&CPU5>; 644 }; 645 646 ete6 { 647 compatible = "arm,embedded-trace-extension"; 648 cpu = <&CPU6>; 649 }; 650 651 ete7 { 652 compatible = "arm,embedded-trace-extension"; 653 cpu = <&CPU7>; 654 }; 655 656 trbe { 657 compatible = "arm,trace-buffer-extension"; 658 interrupts = <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW 0>; 659 }; 660 661 trusty { 662 #size-cells = <0x02>; 663 #address-cells = <0x02>; 664 ranges = <0x00>; 665 compatible = "android,trusty-v1"; 666 667 virtio { 668 compatible = "android,trusty-virtio-v1"; 669 }; 670 671 test { 672 compatible = "android,trusty-test-v1"; 673 }; 674 675 log { 676 compatible = "android,trusty-log-v1"; 677 }; 678 679 irq { 680 ipi-range = <0x08 0x0f 0x08>; 681 interrupt-ranges = <0x00 0x0f 0x00 0x10 0x1f 0x01 0x20 0x3f 0x02>; 682 interrupt-templates = <0x01 0x00 0x8001 0x01 0x01 0x04 0x8001 0x01 0x00 0x04>; 683 compatible = "android,trusty-irq-v1"; 684 }; 685 }; 686 687 /* used in U-boot, Linux doesn't care */ 688 arm_ffa { 689 compatible = "arm,ffa"; 690 method = "smc"; 691 }; 692}; 693