1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) 2023-2024, STMicroelectronics - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/clock/stm32mp25-clks.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/reset/stm32mp25-resets.h> 10 11/ { 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a35"; 21 device_type = "cpu"; 22 reg = <0>; 23 enable-method = "psci"; 24 }; 25 }; 26 27 clocks { 28 clk_hse: clk-hse { 29 #clock-cells = <0>; 30 compatible = "fixed-clock"; 31 clock-frequency = <48000000>; 32 }; 33 34 clk_hsi: clk-hsi { 35 #clock-cells = <0>; 36 compatible = "fixed-clock"; 37 clock-frequency = <64000000>; 38 }; 39 40 clk_lse: clk-lse { 41 #clock-cells = <0>; 42 compatible = "fixed-clock"; 43 clock-frequency = <32768>; 44 }; 45 46 clk_lsi: clk-lsi { 47 #clock-cells = <0>; 48 compatible = "fixed-clock"; 49 clock-frequency = <32000>; 50 }; 51 52 clk_msi: clk-msi { 53 #clock-cells = <0>; 54 compatible = "fixed-clock"; 55 clock-frequency = <16000000>; 56 }; 57 }; 58 59 intc: interrupt-controller@4ac00000 { 60 compatible = "arm,cortex-a7-gic"; 61 #interrupt-cells = <3>; 62 #address-cells = <1>; 63 interrupt-controller; 64 reg = <0x0 0x4ac10000 0x0 0x1000>, 65 <0x0 0x4ac20000 0x0 0x2000>, 66 <0x0 0x4ac40000 0x0 0x2000>, 67 <0x0 0x4ac60000 0x0 0x2000>; 68 }; 69 70 timer { 71 compatible = "arm,armv8-timer"; 72 interrupt-parent = <&intc>; 73 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 74 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 75 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 76 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 77 always-on; 78 }; 79 80 soc@0 { 81 compatible = "simple-bus"; 82 #address-cells = <1>; 83 #size-cells = <1>; 84 interrupt-parent = <&intc>; 85 ranges = <0x0 0x0 0x0 0x80000000>; 86 87 rifsc: rifsc@42080000 { 88 compatible = "st,stm32mp25-rifsc"; 89 reg = <0x42080000 0x1000>; 90 #address-cells = <1>; 91 #size-cells = <1>; 92 93 usart2: serial@400e0000 { 94 compatible = "st,stm32h7-uart"; 95 reg = <0x400e0000 0x400>; 96 clocks = <&rcc CK_KER_USART2>; 97 resets = <&rcc USART2_R>; 98 status = "disabled"; 99 }; 100 101 sdmmc1: mmc@48220000 { 102 compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; 103 arm,primecell-periphid = <0x00353180>; 104 reg = <0x48220000 0x400>, <0x44230400 0x8>; 105 clocks = <&rcc CK_KER_SDMMC1>; 106 clock-names = "apb_pclk"; 107 resets = <&rcc SDMMC1_R>; 108 cap-sd-highspeed; 109 cap-mmc-highspeed; 110 max-frequency = <120000000>; 111 status = "disabled"; 112 }; 113 114 sdmmc2: mmc@48230000 { 115 compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; 116 arm,primecell-periphid = <0x00353180>; 117 reg = <0x48230000 0x400>, <0x44230800 0x8>; 118 clocks = <&rcc CK_KER_SDMMC2>; 119 clock-names = "apb_pclk"; 120 resets = <&rcc SDMMC2_R>; 121 cap-sd-highspeed; 122 cap-mmc-highspeed; 123 max-frequency = <120000000>; 124 status = "disabled"; 125 }; 126 }; 127 128 bsec: efuse@44000000 { 129 compatible = "st,stm32mp25-bsec"; 130 reg = <0x44000000 0x400>; 131 #address-cells = <1>; 132 #size-cells = <1>; 133 134 uid_otp: uid-otp@14 { 135 reg = <0x14 0xc>; 136 }; 137 part_number_otp: part-number-otp@24 { 138 reg = <0x24 0x4>; 139 }; 140 nand_otp: otp16@40 { 141 reg = <0x40 0x4>; 142 }; 143 lifecycle2_otp: otp18@48 { 144 reg = <0x48 0x4>; 145 }; 146 nand2_otp: otp20@50 { 147 reg = <0x50 0x4>; 148 }; 149 rev_otp@198 { 150 reg = <0x198 0x4>; 151 }; 152 package_otp: package-otp@1e8 { 153 reg = <0x1e8 0x1>; 154 }; 155 hconf1_otp: otp124@1f0 { 156 reg = <0x1f0 0x4>; 157 }; 158 pkh_otp: otp144@240 { 159 reg = <0x240 0x20>; 160 }; 161 oem_fip_enc_key: otp260@410 { 162 reg = <0x410 0x20>; 163 }; 164 }; 165 166 rcc: rcc@44200000 { 167 compatible = "st,stm32mp25-rcc"; 168 reg = <0x44200000 0x10000>; 169 #clock-cells = <1>; 170 #reset-cells = <1>; 171 }; 172 173 pwr: pwr@44210000 { 174 compatible = "st,stm32mp25-pwr"; 175 reg = <0x44210000 0x400>; 176 177 vddio1: vddio1 { 178 regulator-name = "vddio1"; 179 }; 180 181 vddio2: vddio2 { 182 regulator-name = "vddio2"; 183 }; 184 185 vddio3: vddio3 { 186 regulator-name = "vddio3"; 187 }; 188 189 vddio4: vddio4 { 190 regulator-name = "vddio4"; 191 }; 192 193 vddio: vddio { 194 regulator-name = "vddio"; 195 }; 196 }; 197 198 syscfg: syscon@44230000 { 199 compatible = "st,stm32mp25-syscfg", "syscon"; 200 reg = <0x44230000 0x10000>; 201 }; 202 203 pinctrl: pinctrl@44240000 { 204 #address-cells = <1>; 205 #size-cells = <1>; 206 compatible = "st,stm32mp257-pinctrl"; 207 ranges = <0 0x44240000 0xa0400>; 208 209 gpioa: gpio@44240000 { 210 gpio-controller; 211 #gpio-cells = <2>; 212 interrupt-controller; 213 #interrupt-cells = <2>; 214 reg = <0x0 0x400>; 215 clocks = <&rcc CK_BUS_GPIOA>; 216 st,bank-name = "GPIOA"; 217 status = "disabled"; 218 }; 219 220 gpiob: gpio@44250000 { 221 gpio-controller; 222 #gpio-cells = <2>; 223 interrupt-controller; 224 #interrupt-cells = <2>; 225 reg = <0x10000 0x400>; 226 clocks = <&rcc CK_BUS_GPIOB>; 227 st,bank-name = "GPIOB"; 228 status = "disabled"; 229 }; 230 231 gpioc: gpio@44260000 { 232 gpio-controller; 233 #gpio-cells = <2>; 234 interrupt-controller; 235 #interrupt-cells = <2>; 236 reg = <0x20000 0x400>; 237 clocks = <&rcc CK_BUS_GPIOC>; 238 st,bank-name = "GPIOC"; 239 status = "disabled"; 240 }; 241 242 gpiod: gpio@44270000 { 243 gpio-controller; 244 #gpio-cells = <2>; 245 interrupt-controller; 246 #interrupt-cells = <2>; 247 reg = <0x30000 0x400>; 248 clocks = <&rcc CK_BUS_GPIOD>; 249 st,bank-name = "GPIOD"; 250 status = "disabled"; 251 }; 252 253 gpioe: gpio@44280000 { 254 gpio-controller; 255 #gpio-cells = <2>; 256 interrupt-controller; 257 #interrupt-cells = <2>; 258 reg = <0x40000 0x400>; 259 clocks = <&rcc CK_BUS_GPIOE>; 260 st,bank-name = "GPIOE"; 261 status = "disabled"; 262 }; 263 264 gpiof: gpio@44290000 { 265 gpio-controller; 266 #gpio-cells = <2>; 267 interrupt-controller; 268 #interrupt-cells = <2>; 269 reg = <0x50000 0x400>; 270 clocks = <&rcc CK_BUS_GPIOF>; 271 st,bank-name = "GPIOF"; 272 status = "disabled"; 273 }; 274 275 gpiog: gpio@442a0000 { 276 gpio-controller; 277 #gpio-cells = <2>; 278 interrupt-controller; 279 #interrupt-cells = <2>; 280 reg = <0x60000 0x400>; 281 clocks = <&rcc CK_BUS_GPIOG>; 282 st,bank-name = "GPIOG"; 283 status = "disabled"; 284 }; 285 286 gpioh: gpio@442b0000 { 287 gpio-controller; 288 #gpio-cells = <2>; 289 interrupt-controller; 290 #interrupt-cells = <2>; 291 reg = <0x70000 0x400>; 292 clocks = <&rcc CK_BUS_GPIOH>; 293 st,bank-name = "GPIOH"; 294 status = "disabled"; 295 }; 296 297 gpioi: gpio@442c0000 { 298 gpio-controller; 299 #gpio-cells = <2>; 300 interrupt-controller; 301 #interrupt-cells = <2>; 302 reg = <0x80000 0x400>; 303 clocks = <&rcc CK_BUS_GPIOI>; 304 st,bank-name = "GPIOI"; 305 status = "disabled"; 306 }; 307 308 gpioj: gpio@442d0000 { 309 gpio-controller; 310 #gpio-cells = <2>; 311 interrupt-controller; 312 #interrupt-cells = <2>; 313 reg = <0x90000 0x400>; 314 clocks = <&rcc CK_BUS_GPIOJ>; 315 st,bank-name = "GPIOJ"; 316 status = "disabled"; 317 }; 318 319 gpiok: gpio@442e0000 { 320 gpio-controller; 321 #gpio-cells = <2>; 322 interrupt-controller; 323 #interrupt-cells = <2>; 324 reg = <0xa0000 0x400>; 325 clocks = <&rcc CK_BUS_GPIOK>; 326 st,bank-name = "GPIOK"; 327 status = "disabled"; 328 }; 329 }; 330 331 pinctrl_z: pinctrl@46200000 { 332 #address-cells = <1>; 333 #size-cells = <1>; 334 compatible = "st,stm32mp257-z-pinctrl"; 335 ranges = <0 0x46200000 0x400>; 336 337 gpioz: gpio@46200000 { 338 gpio-controller; 339 #gpio-cells = <2>; 340 interrupt-controller; 341 #interrupt-cells = <2>; 342 reg = <0 0x400>; 343 clocks = <&rcc CK_BUS_GPIOZ>; 344 st,bank-name = "GPIOZ"; 345 st,bank-ioport = <11>; 346 status = "disabled"; 347 }; 348 349 }; 350 }; 351}; 352