1 /* 2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/debug.h> 9 #include <common/runtime_svc.h> 10 #include <lib/mmio.h> 11 #include <tools_share/uuid.h> 12 13 #include "socfpga_fcs.h" 14 #include "socfpga_mailbox.h" 15 #include "socfpga_reset_manager.h" 16 #include "socfpga_sip_svc.h" 17 18 19 /* Total buffer the driver can hold */ 20 #define FPGA_CONFIG_BUFFER_SIZE 4 21 22 static config_type request_type = NO_REQUEST; 23 static int current_block, current_buffer; 24 static int read_block, max_blocks; 25 static uint32_t send_id, rcv_id; 26 static uint32_t bytes_per_block, blocks_submitted; 27 static bool bridge_disable; 28 29 /* RSU static variables */ 30 static uint32_t rsu_dcmf_ver[4] = {0}; 31 static uint16_t rsu_dcmf_stat[4] = {0}; 32 static uint32_t rsu_max_retry; 33 34 /* SiP Service UUID */ 35 DEFINE_SVC_UUID2(intl_svc_uid, 36 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 37 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 38 39 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 40 uint64_t x1, 41 uint64_t x2, 42 uint64_t x3, 43 uint64_t x4, 44 void *cookie, 45 void *handle, 46 uint64_t flags) 47 { 48 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 49 SMC_RET1(handle, SMC_UNK); 50 } 51 52 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 53 54 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 55 { 56 uint32_t args[3]; 57 58 while (max_blocks > 0 && buffer->size > buffer->size_written) { 59 args[0] = (1<<8); 60 args[1] = buffer->addr + buffer->size_written; 61 if (buffer->size - buffer->size_written <= bytes_per_block) { 62 args[2] = buffer->size - buffer->size_written; 63 current_buffer++; 64 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 65 } else { 66 args[2] = bytes_per_block; 67 } 68 69 buffer->size_written += args[2]; 70 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 71 3U, CMD_INDIRECT); 72 73 buffer->subblocks_sent++; 74 max_blocks--; 75 } 76 77 return !max_blocks; 78 } 79 80 static int intel_fpga_sdm_write_all(void) 81 { 82 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 83 if (intel_fpga_sdm_write_buffer( 84 &fpga_config_buffers[current_buffer])) { 85 break; 86 } 87 } 88 return 0; 89 } 90 91 static uint32_t intel_mailbox_fpga_config_isdone(void) 92 { 93 uint32_t ret; 94 95 switch (request_type) { 96 case RECONFIGURATION: 97 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 98 true); 99 break; 100 case BITSTREAM_AUTH: 101 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 102 false); 103 break; 104 default: 105 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, 106 false); 107 break; 108 } 109 110 if (ret != 0U) { 111 if (ret == MBOX_CFGSTAT_STATE_CONFIG) { 112 return INTEL_SIP_SMC_STATUS_BUSY; 113 } else { 114 request_type = NO_REQUEST; 115 return INTEL_SIP_SMC_STATUS_ERROR; 116 } 117 } 118 119 if (bridge_disable != 0U) { 120 socfpga_bridges_enable(~0); /* Enable bridge */ 121 bridge_disable = false; 122 } 123 request_type = NO_REQUEST; 124 125 return INTEL_SIP_SMC_STATUS_OK; 126 } 127 128 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 129 { 130 int i; 131 132 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 133 if (fpga_config_buffers[i].block_number == current_block) { 134 fpga_config_buffers[i].subblocks_sent--; 135 if (fpga_config_buffers[i].subblocks_sent == 0 136 && fpga_config_buffers[i].size <= 137 fpga_config_buffers[i].size_written) { 138 fpga_config_buffers[i].write_requested = 0; 139 current_block++; 140 *buffer_addr_completed = 141 fpga_config_buffers[i].addr; 142 return 0; 143 } 144 } 145 } 146 147 return -1; 148 } 149 150 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 151 uint32_t *count, uint32_t *job_id) 152 { 153 uint32_t resp[5]; 154 unsigned int resp_len = ARRAY_SIZE(resp); 155 int status = INTEL_SIP_SMC_STATUS_OK; 156 int all_completed = 1; 157 *count = 0; 158 159 while (*count < 3) { 160 161 status = mailbox_read_response(job_id, 162 resp, &resp_len); 163 164 if (status < 0) { 165 break; 166 } 167 168 max_blocks++; 169 170 if (mark_last_buffer_xfer_completed( 171 &completed_addr[*count]) == 0) { 172 *count = *count + 1; 173 } else { 174 break; 175 } 176 } 177 178 if (*count <= 0) { 179 if (status != MBOX_NO_RESPONSE && 180 status != MBOX_TIMEOUT && resp_len != 0) { 181 mailbox_clear_response(); 182 request_type = NO_REQUEST; 183 return INTEL_SIP_SMC_STATUS_ERROR; 184 } 185 186 *count = 0; 187 } 188 189 intel_fpga_sdm_write_all(); 190 191 if (*count > 0) { 192 status = INTEL_SIP_SMC_STATUS_OK; 193 } else if (*count == 0) { 194 status = INTEL_SIP_SMC_STATUS_BUSY; 195 } 196 197 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 198 if (fpga_config_buffers[i].write_requested != 0) { 199 all_completed = 0; 200 break; 201 } 202 } 203 204 if (all_completed == 1) { 205 return INTEL_SIP_SMC_STATUS_OK; 206 } 207 208 return status; 209 } 210 211 static int intel_fpga_config_start(uint32_t flag) 212 { 213 uint32_t argument = 0x1; 214 uint32_t response[3]; 215 int status = 0; 216 unsigned int size = 0; 217 unsigned int resp_len = ARRAY_SIZE(response); 218 219 request_type = RECONFIGURATION; 220 221 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) { 222 bridge_disable = true; 223 } 224 225 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) { 226 size = 1; 227 bridge_disable = false; 228 request_type = BITSTREAM_AUTH; 229 } 230 231 mailbox_clear_response(); 232 233 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 234 CMD_CASUAL, NULL, NULL); 235 236 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 237 CMD_CASUAL, response, &resp_len); 238 239 if (status < 0) { 240 bridge_disable = false; 241 request_type = NO_REQUEST; 242 return INTEL_SIP_SMC_STATUS_ERROR; 243 } 244 245 max_blocks = response[0]; 246 bytes_per_block = response[1]; 247 248 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 249 fpga_config_buffers[i].size = 0; 250 fpga_config_buffers[i].size_written = 0; 251 fpga_config_buffers[i].addr = 0; 252 fpga_config_buffers[i].write_requested = 0; 253 fpga_config_buffers[i].block_number = 0; 254 fpga_config_buffers[i].subblocks_sent = 0; 255 } 256 257 blocks_submitted = 0; 258 current_block = 0; 259 read_block = 0; 260 current_buffer = 0; 261 262 /* Disable bridge on full reconfiguration */ 263 if (bridge_disable) { 264 socfpga_bridges_disable(~0); 265 } 266 267 return INTEL_SIP_SMC_STATUS_OK; 268 } 269 270 static bool is_fpga_config_buffer_full(void) 271 { 272 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 273 if (!fpga_config_buffers[i].write_requested) { 274 return false; 275 } 276 } 277 return true; 278 } 279 280 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 281 { 282 if (!addr && !size) { 283 return true; 284 } 285 if (size > (UINT64_MAX - addr)) { 286 return false; 287 } 288 if (addr < BL31_LIMIT) { 289 return false; 290 } 291 if (addr + size > DRAM_BASE + DRAM_SIZE) { 292 return false; 293 } 294 295 return true; 296 } 297 298 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 299 { 300 int i; 301 302 intel_fpga_sdm_write_all(); 303 304 if (!is_address_in_ddr_range(mem, size) || 305 is_fpga_config_buffer_full()) { 306 return INTEL_SIP_SMC_STATUS_REJECTED; 307 } 308 309 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 310 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 311 312 if (!fpga_config_buffers[j].write_requested) { 313 fpga_config_buffers[j].addr = mem; 314 fpga_config_buffers[j].size = size; 315 fpga_config_buffers[j].size_written = 0; 316 fpga_config_buffers[j].write_requested = 1; 317 fpga_config_buffers[j].block_number = 318 blocks_submitted++; 319 fpga_config_buffers[j].subblocks_sent = 0; 320 break; 321 } 322 } 323 324 if (is_fpga_config_buffer_full()) { 325 return INTEL_SIP_SMC_STATUS_BUSY; 326 } 327 328 return INTEL_SIP_SMC_STATUS_OK; 329 } 330 331 static int is_out_of_sec_range(uint64_t reg_addr) 332 { 333 #if DEBUG 334 return 0; 335 #endif 336 337 switch (reg_addr) { 338 case(0xF8011100): /* ECCCTRL1 */ 339 case(0xF8011104): /* ECCCTRL2 */ 340 case(0xF8011110): /* ERRINTEN */ 341 case(0xF8011114): /* ERRINTENS */ 342 case(0xF8011118): /* ERRINTENR */ 343 case(0xF801111C): /* INTMODE */ 344 case(0xF8011120): /* INTSTAT */ 345 case(0xF8011124): /* DIAGINTTEST */ 346 case(0xF801112C): /* DERRADDRA */ 347 case(0xFA000000): /* SMMU SCR0 */ 348 case(0xFA000004): /* SMMU SCR1 */ 349 case(0xFA000400): /* SMMU NSCR0 */ 350 case(0xFA004000): /* SMMU SSD0_REG */ 351 case(0xFA000820): /* SMMU SMR8 */ 352 case(0xFA000c20): /* SMMU SCR8 */ 353 case(0xFA028000): /* SMMU CB8_SCTRL */ 354 case(0xFA001020): /* SMMU CBAR8 */ 355 case(0xFA028030): /* SMMU TCR_LPAE */ 356 case(0xFA028020): /* SMMU CB8_TTBR0_LOW */ 357 case(0xFA028024): /* SMMU CB8_PRRR_HIGH */ 358 case(0xFA028038): /* SMMU CB8_PRRR_MIR0 */ 359 case(0xFA02803C): /* SMMU CB8_PRRR_MIR1 */ 360 case(0xFA028010): /* SMMU_CB8)TCR2 */ 361 case(0xFFD080A4): /* SDM SMMU STREAM ID REG */ 362 case(0xFA001820): /* SMMU_CBA2R8 */ 363 case(0xFA000074): /* SMMU_STLBGSTATUS */ 364 case(0xFA0287F4): /* SMMU_CB8_TLBSTATUS */ 365 case(0xFA000060): /* SMMU_STLBIALL */ 366 case(0xFA000070): /* SMMU_STLBGSYNC */ 367 case(0xFA028618): /* CB8_TLBALL */ 368 case(0xFA0287F0): /* CB8_TLBSYNC */ 369 case(0xFFD12028): /* SDMMCGRP_CTRL */ 370 case(0xFFD12044): /* EMAC0 */ 371 case(0xFFD12048): /* EMAC1 */ 372 case(0xFFD1204C): /* EMAC2 */ 373 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 374 case(0xFFD12094): /* ECC_INT_MASK_SET */ 375 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 376 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 377 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 378 case(0xFFD120C0): /* NOC_TIMEOUT */ 379 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 380 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 381 case(0xFFD120D0): /* NOC_IDLEACK */ 382 case(0xFFD120D4): /* NOC_IDLESTATUS */ 383 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 384 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 385 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 386 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 387 return 0; 388 389 default: 390 break; 391 } 392 393 return -1; 394 } 395 396 /* Secure register access */ 397 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 398 { 399 if (is_out_of_sec_range(reg_addr)) { 400 return INTEL_SIP_SMC_STATUS_ERROR; 401 } 402 403 *retval = mmio_read_32(reg_addr); 404 405 return INTEL_SIP_SMC_STATUS_OK; 406 } 407 408 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 409 uint32_t *retval) 410 { 411 if (is_out_of_sec_range(reg_addr)) { 412 return INTEL_SIP_SMC_STATUS_ERROR; 413 } 414 415 mmio_write_32(reg_addr, val); 416 417 return intel_secure_reg_read(reg_addr, retval); 418 } 419 420 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 421 uint32_t val, uint32_t *retval) 422 { 423 if (!intel_secure_reg_read(reg_addr, retval)) { 424 *retval &= ~mask; 425 *retval |= val & mask; 426 return intel_secure_reg_write(reg_addr, *retval, retval); 427 } 428 429 return INTEL_SIP_SMC_STATUS_ERROR; 430 } 431 432 /* Intel Remote System Update (RSU) services */ 433 uint64_t intel_rsu_update_address; 434 435 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 436 { 437 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 438 return INTEL_SIP_SMC_RSU_ERROR; 439 } 440 441 return INTEL_SIP_SMC_STATUS_OK; 442 } 443 444 static uint32_t intel_rsu_update(uint64_t update_address) 445 { 446 if (update_address > SIZE_MAX) { 447 return INTEL_SIP_SMC_STATUS_REJECTED; 448 } 449 450 intel_rsu_update_address = update_address; 451 return INTEL_SIP_SMC_STATUS_OK; 452 } 453 454 static uint32_t intel_rsu_notify(uint32_t execution_stage) 455 { 456 if (mailbox_hps_stage_notify(execution_stage) < 0) { 457 return INTEL_SIP_SMC_RSU_ERROR; 458 } 459 460 return INTEL_SIP_SMC_STATUS_OK; 461 } 462 463 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 464 uint32_t *ret_stat) 465 { 466 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 467 return INTEL_SIP_SMC_RSU_ERROR; 468 } 469 470 *ret_stat = respbuf[8]; 471 return INTEL_SIP_SMC_STATUS_OK; 472 } 473 474 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 475 uint64_t dcmf_ver_3_2) 476 { 477 rsu_dcmf_ver[0] = dcmf_ver_1_0; 478 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 479 rsu_dcmf_ver[2] = dcmf_ver_3_2; 480 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 481 482 return INTEL_SIP_SMC_STATUS_OK; 483 } 484 485 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) 486 { 487 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); 488 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); 489 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); 490 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); 491 492 return INTEL_SIP_SMC_STATUS_OK; 493 } 494 495 /* Intel HWMON services */ 496 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval) 497 { 498 if (mailbox_hwmon_readtemp(chan, retval) < 0) { 499 return INTEL_SIP_SMC_STATUS_ERROR; 500 } 501 502 return INTEL_SIP_SMC_STATUS_OK; 503 } 504 505 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval) 506 { 507 if (mailbox_hwmon_readvolt(chan, retval) < 0) { 508 return INTEL_SIP_SMC_STATUS_ERROR; 509 } 510 511 return INTEL_SIP_SMC_STATUS_OK; 512 } 513 514 /* Mailbox services */ 515 static uint32_t intel_smc_fw_version(uint32_t *fw_version) 516 { 517 int status; 518 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE; 519 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U}; 520 521 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U, 522 CMD_CASUAL, resp_data, &resp_len); 523 524 if (status < 0) { 525 return INTEL_SIP_SMC_STATUS_ERROR; 526 } 527 528 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) { 529 return INTEL_SIP_SMC_STATUS_ERROR; 530 } 531 532 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK; 533 534 return INTEL_SIP_SMC_STATUS_OK; 535 } 536 537 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 538 unsigned int len, uint32_t urgent, uint64_t response, 539 unsigned int resp_len, int *mbox_status, 540 unsigned int *len_in_resp) 541 { 542 *len_in_resp = 0; 543 *mbox_status = GENERIC_RESPONSE_ERROR; 544 545 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) { 546 return INTEL_SIP_SMC_STATUS_REJECTED; 547 } 548 549 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 550 (uint32_t *) response, &resp_len); 551 552 if (status < 0) { 553 *mbox_status = -status; 554 return INTEL_SIP_SMC_STATUS_ERROR; 555 } 556 557 *mbox_status = 0; 558 *len_in_resp = resp_len; 559 560 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE); 561 562 return INTEL_SIP_SMC_STATUS_OK; 563 } 564 565 static int intel_smc_get_usercode(uint32_t *user_code) 566 { 567 int status; 568 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE; 569 570 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL, 571 0U, CMD_CASUAL, user_code, &resp_len); 572 573 if (status < 0) { 574 return INTEL_SIP_SMC_STATUS_ERROR; 575 } 576 577 return INTEL_SIP_SMC_STATUS_OK; 578 } 579 580 uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size, 581 uint32_t mode, uint32_t *job_id, 582 uint32_t *ret_size, uint32_t *mbox_error) 583 { 584 int status = 0; 585 uint32_t resp_len = size / MBOX_WORD_BYTE; 586 587 if (resp_len > MBOX_DATA_MAX_LEN) { 588 return INTEL_SIP_SMC_STATUS_REJECTED; 589 } 590 591 if (!is_address_in_ddr_range(addr, size)) { 592 return INTEL_SIP_SMC_STATUS_REJECTED; 593 } 594 595 if (mode == SERVICE_COMPLETED_MODE_ASYNC) { 596 status = mailbox_read_response_async(job_id, 597 NULL, (uint32_t *) addr, &resp_len, 0); 598 } else { 599 status = mailbox_read_response(job_id, 600 (uint32_t *) addr, &resp_len); 601 602 if (status == MBOX_NO_RESPONSE) { 603 status = MBOX_BUSY; 604 } 605 } 606 607 if (status == MBOX_NO_RESPONSE) { 608 return INTEL_SIP_SMC_STATUS_NO_RESPONSE; 609 } 610 611 if (status == MBOX_BUSY) { 612 return INTEL_SIP_SMC_STATUS_BUSY; 613 } 614 615 *ret_size = resp_len * MBOX_WORD_BYTE; 616 flush_dcache_range(addr, *ret_size); 617 618 if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 || 619 status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) { 620 *mbox_error = -status; 621 } else if (status != MBOX_RET_OK) { 622 *mbox_error = -status; 623 return INTEL_SIP_SMC_STATUS_ERROR; 624 } 625 626 return INTEL_SIP_SMC_STATUS_OK; 627 } 628 629 /* Miscellaneous HPS services */ 630 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask) 631 { 632 int status = 0; 633 634 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) { 635 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 636 status = socfpga_bridges_enable((uint32_t)mask); 637 } else { 638 status = socfpga_bridges_enable(~0); 639 } 640 } else { 641 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 642 status = socfpga_bridges_disable((uint32_t)mask); 643 } else { 644 status = socfpga_bridges_disable(~0); 645 } 646 } 647 648 if (status < 0) { 649 return INTEL_SIP_SMC_STATUS_ERROR; 650 } 651 652 return INTEL_SIP_SMC_STATUS_OK; 653 } 654 655 /* 656 * This function is responsible for handling all SiP calls from the NS world 657 */ 658 659 uintptr_t sip_smc_handler_v1(uint32_t smc_fid, 660 u_register_t x1, 661 u_register_t x2, 662 u_register_t x3, 663 u_register_t x4, 664 void *cookie, 665 void *handle, 666 u_register_t flags) 667 { 668 uint32_t retval = 0, completed_addr[3]; 669 uint32_t retval2 = 0; 670 uint32_t mbox_error = 0; 671 uint64_t retval64, rsu_respbuf[9]; 672 int status = INTEL_SIP_SMC_STATUS_OK; 673 int mbox_status; 674 unsigned int len_in_resp; 675 u_register_t x5, x6, x7; 676 677 switch (smc_fid) { 678 case SIP_SVC_UID: 679 /* Return UID to the caller */ 680 SMC_UUID_RET(handle, intl_svc_uid); 681 682 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 683 status = intel_mailbox_fpga_config_isdone(); 684 SMC_RET4(handle, status, 0, 0, 0); 685 686 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 687 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 688 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 689 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 690 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 691 692 case INTEL_SIP_SMC_FPGA_CONFIG_START: 693 status = intel_fpga_config_start(x1); 694 SMC_RET4(handle, status, 0, 0, 0); 695 696 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 697 status = intel_fpga_config_write(x1, x2); 698 SMC_RET4(handle, status, 0, 0, 0); 699 700 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 701 status = intel_fpga_config_completed_write(completed_addr, 702 &retval, &rcv_id); 703 switch (retval) { 704 case 1: 705 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 706 completed_addr[0], 0, 0); 707 708 case 2: 709 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 710 completed_addr[0], 711 completed_addr[1], 0); 712 713 case 3: 714 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 715 completed_addr[0], 716 completed_addr[1], 717 completed_addr[2]); 718 719 case 0: 720 SMC_RET4(handle, status, 0, 0, 0); 721 722 default: 723 mailbox_clear_response(); 724 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 725 } 726 727 case INTEL_SIP_SMC_REG_READ: 728 status = intel_secure_reg_read(x1, &retval); 729 SMC_RET3(handle, status, retval, x1); 730 731 case INTEL_SIP_SMC_REG_WRITE: 732 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 733 SMC_RET3(handle, status, retval, x1); 734 735 case INTEL_SIP_SMC_REG_UPDATE: 736 status = intel_secure_reg_update(x1, (uint32_t)x2, 737 (uint32_t)x3, &retval); 738 SMC_RET3(handle, status, retval, x1); 739 740 case INTEL_SIP_SMC_RSU_STATUS: 741 status = intel_rsu_status(rsu_respbuf, 742 ARRAY_SIZE(rsu_respbuf)); 743 if (status) { 744 SMC_RET1(handle, status); 745 } else { 746 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 747 rsu_respbuf[2], rsu_respbuf[3]); 748 } 749 750 case INTEL_SIP_SMC_RSU_UPDATE: 751 status = intel_rsu_update(x1); 752 SMC_RET1(handle, status); 753 754 case INTEL_SIP_SMC_RSU_NOTIFY: 755 status = intel_rsu_notify(x1); 756 SMC_RET1(handle, status); 757 758 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 759 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 760 ARRAY_SIZE(rsu_respbuf), &retval); 761 if (status) { 762 SMC_RET1(handle, status); 763 } else { 764 SMC_RET2(handle, status, retval); 765 } 766 767 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 768 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 769 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 770 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 771 772 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 773 status = intel_rsu_copy_dcmf_version(x1, x2); 774 SMC_RET1(handle, status); 775 776 case INTEL_SIP_SMC_RSU_DCMF_STATUS: 777 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, 778 ((uint64_t)rsu_dcmf_stat[3] << 48) | 779 ((uint64_t)rsu_dcmf_stat[2] << 32) | 780 ((uint64_t)rsu_dcmf_stat[1] << 16) | 781 rsu_dcmf_stat[0]); 782 783 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: 784 status = intel_rsu_copy_dcmf_status(x1); 785 SMC_RET1(handle, status); 786 787 case INTEL_SIP_SMC_RSU_MAX_RETRY: 788 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 789 790 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 791 rsu_max_retry = x1; 792 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 793 794 case INTEL_SIP_SMC_ECC_DBE: 795 status = intel_ecc_dbe_notification(x1); 796 SMC_RET1(handle, status); 797 798 case INTEL_SIP_SMC_SERVICE_COMPLETED: 799 status = intel_smc_service_completed(x1, x2, x3, &rcv_id, 800 &len_in_resp, &mbox_error); 801 SMC_RET4(handle, status, mbox_error, x1, len_in_resp); 802 803 case INTEL_SIP_SMC_FIRMWARE_VERSION: 804 status = intel_smc_fw_version(&retval); 805 SMC_RET2(handle, status, retval); 806 807 case INTEL_SIP_SMC_MBOX_SEND_CMD: 808 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 809 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 810 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6, 811 &mbox_status, &len_in_resp); 812 SMC_RET3(handle, status, mbox_status, len_in_resp); 813 814 case INTEL_SIP_SMC_GET_USERCODE: 815 status = intel_smc_get_usercode(&retval); 816 SMC_RET2(handle, status, retval); 817 818 case INTEL_SIP_SMC_FCS_CRYPTION: 819 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 820 821 if (x1 == FCS_MODE_DECRYPT) { 822 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id); 823 } else if (x1 == FCS_MODE_ENCRYPT) { 824 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id); 825 } else { 826 status = INTEL_SIP_SMC_STATUS_REJECTED; 827 } 828 829 SMC_RET3(handle, status, x4, x5); 830 831 case INTEL_SIP_SMC_FCS_CRYPTION_EXT: 832 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 833 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 834 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 835 836 if (x3 == FCS_MODE_DECRYPT) { 837 status = intel_fcs_decryption_ext(x1, x2, x4, x5, x6, 838 (uint32_t *) &x7, &mbox_error); 839 } else if (x3 == FCS_MODE_ENCRYPT) { 840 status = intel_fcs_encryption_ext(x1, x2, x4, x5, x6, 841 (uint32_t *) &x7, &mbox_error); 842 } else { 843 status = INTEL_SIP_SMC_STATUS_REJECTED; 844 } 845 846 SMC_RET4(handle, status, mbox_error, x6, x7); 847 848 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER: 849 status = intel_fcs_random_number_gen(x1, &retval64, 850 &mbox_error); 851 SMC_RET4(handle, status, mbox_error, x1, retval64); 852 853 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT: 854 status = intel_fcs_random_number_gen_ext(x1, x2, x3, 855 &send_id); 856 SMC_RET1(handle, status); 857 858 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE: 859 status = intel_fcs_send_cert(x1, x2, &send_id); 860 SMC_RET1(handle, status); 861 862 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA: 863 status = intel_fcs_get_provision_data(&send_id); 864 SMC_RET1(handle, status); 865 866 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH: 867 status = intel_fcs_cntr_set_preauth(x1, x2, x3, 868 &mbox_error); 869 SMC_RET2(handle, status, mbox_error); 870 871 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 872 status = intel_hps_set_bridges(x1, x2); 873 SMC_RET1(handle, status); 874 875 case INTEL_SIP_SMC_HWMON_READTEMP: 876 status = intel_hwmon_readtemp(x1, &retval); 877 SMC_RET2(handle, status, retval); 878 879 case INTEL_SIP_SMC_HWMON_READVOLT: 880 status = intel_hwmon_readvolt(x1, &retval); 881 SMC_RET2(handle, status, retval); 882 883 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN: 884 status = intel_fcs_sigma_teardown(x1, &mbox_error); 885 SMC_RET2(handle, status, mbox_error); 886 887 case INTEL_SIP_SMC_FCS_CHIP_ID: 888 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error); 889 SMC_RET4(handle, status, mbox_error, retval, retval2); 890 891 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY: 892 status = intel_fcs_attestation_subkey(x1, x2, x3, 893 (uint32_t *) &x4, &mbox_error); 894 SMC_RET4(handle, status, mbox_error, x3, x4); 895 896 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS: 897 status = intel_fcs_get_measurement(x1, x2, x3, 898 (uint32_t *) &x4, &mbox_error); 899 SMC_RET4(handle, status, mbox_error, x3, x4); 900 901 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT: 902 status = intel_fcs_get_attestation_cert(x1, x2, 903 (uint32_t *) &x3, &mbox_error); 904 SMC_RET4(handle, status, mbox_error, x2, x3); 905 906 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD: 907 status = intel_fcs_create_cert_on_reload(x1, &mbox_error); 908 SMC_RET2(handle, status, mbox_error); 909 910 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION: 911 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error); 912 SMC_RET3(handle, status, mbox_error, retval); 913 914 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION: 915 status = intel_fcs_close_crypto_service_session(x1, &mbox_error); 916 SMC_RET2(handle, status, mbox_error); 917 918 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY: 919 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id); 920 SMC_RET1(handle, status); 921 922 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY: 923 status = intel_fcs_export_crypto_service_key(x1, x2, x3, 924 (uint32_t *) &x4, &mbox_error); 925 SMC_RET4(handle, status, mbox_error, x3, x4); 926 927 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY: 928 status = intel_fcs_remove_crypto_service_key(x1, x2, 929 &mbox_error); 930 SMC_RET2(handle, status, mbox_error); 931 932 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO: 933 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3, 934 (uint32_t *) &x4, &mbox_error); 935 SMC_RET4(handle, status, mbox_error, x3, x4); 936 937 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT: 938 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 939 status = intel_fcs_get_digest_init(x1, x2, x3, 940 x4, x5, &mbox_error); 941 SMC_RET2(handle, status, mbox_error); 942 943 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE: 944 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 945 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 946 status = intel_fcs_get_digest_update_finalize(x1, x2, x3, 947 x4, x5, (uint32_t *) &x6, false, 948 &mbox_error); 949 SMC_RET4(handle, status, mbox_error, x5, x6); 950 951 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE: 952 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 953 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 954 status = intel_fcs_get_digest_update_finalize(x1, x2, x3, 955 x4, x5, (uint32_t *) &x6, true, 956 &mbox_error); 957 SMC_RET4(handle, status, mbox_error, x5, x6); 958 959 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE: 960 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 961 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 962 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 963 x4, x5, (uint32_t *) &x6, false, 964 &mbox_error, &send_id); 965 SMC_RET4(handle, status, mbox_error, x5, x6); 966 967 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE: 968 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 969 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 970 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 971 x4, x5, (uint32_t *) &x6, true, 972 &mbox_error, &send_id); 973 SMC_RET4(handle, status, mbox_error, x5, x6); 974 975 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT: 976 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 977 status = intel_fcs_mac_verify_init(x1, x2, x3, 978 x4, x5, &mbox_error); 979 SMC_RET2(handle, status, mbox_error); 980 981 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE: 982 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 983 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 984 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 985 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, 986 x4, x5, (uint32_t *) &x6, x7, 987 false, &mbox_error); 988 SMC_RET4(handle, status, mbox_error, x5, x6); 989 990 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE: 991 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 992 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 993 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 994 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, 995 x4, x5, (uint32_t *) &x6, x7, 996 true, &mbox_error); 997 SMC_RET4(handle, status, mbox_error, x5, x6); 998 999 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE: 1000 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1001 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1002 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1003 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 1004 x4, x5, (uint32_t *) &x6, x7, 1005 false, &mbox_error, &send_id); 1006 SMC_RET4(handle, status, mbox_error, x5, x6); 1007 1008 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE: 1009 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1010 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1011 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1012 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 1013 x4, x5, (uint32_t *) &x6, x7, 1014 true, &mbox_error, &send_id); 1015 SMC_RET4(handle, status, mbox_error, x5, x6); 1016 1017 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 1018 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1019 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3, 1020 x4, x5, &mbox_error); 1021 SMC_RET2(handle, status, mbox_error); 1022 1023 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 1024 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1025 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1026 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 1027 x3, x4, x5, (uint32_t *) &x6, false, 1028 &mbox_error); 1029 SMC_RET4(handle, status, mbox_error, x5, x6); 1030 1031 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 1032 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1033 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1034 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 1035 x3, x4, x5, (uint32_t *) &x6, true, 1036 &mbox_error); 1037 SMC_RET4(handle, status, mbox_error, x5, x6); 1038 1039 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE: 1040 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1041 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1042 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 1043 x2, x3, x4, x5, (uint32_t *) &x6, false, 1044 &mbox_error, &send_id); 1045 SMC_RET4(handle, status, mbox_error, x5, x6); 1046 1047 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE: 1048 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1049 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1050 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 1051 x2, x3, x4, x5, (uint32_t *) &x6, true, 1052 &mbox_error, &send_id); 1053 SMC_RET4(handle, status, mbox_error, x5, x6); 1054 1055 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT: 1056 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1057 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3, 1058 x4, x5, &mbox_error); 1059 SMC_RET2(handle, status, mbox_error); 1060 1061 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE: 1062 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1063 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1064 status = intel_fcs_ecdsa_hash_sign_finalize(x1, x2, x3, 1065 x4, x5, (uint32_t *) &x6, &mbox_error); 1066 SMC_RET4(handle, status, mbox_error, x5, x6); 1067 1068 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 1069 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1070 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3, 1071 x4, x5, &mbox_error); 1072 SMC_RET2(handle, status, mbox_error); 1073 1074 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 1075 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1076 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1077 status = intel_fcs_ecdsa_hash_sig_verify_finalize(x1, x2, x3, 1078 x4, x5, (uint32_t *) &x6, &mbox_error); 1079 SMC_RET4(handle, status, mbox_error, x5, x6); 1080 1081 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 1082 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1083 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3, 1084 x4, x5, &mbox_error); 1085 SMC_RET2(handle, status, mbox_error); 1086 1087 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 1088 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1089 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1090 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1091 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1092 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1093 x7, false, &mbox_error); 1094 SMC_RET4(handle, status, mbox_error, x5, x6); 1095 1096 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE: 1097 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1098 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1099 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1100 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 1101 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1102 x7, false, &mbox_error, &send_id); 1103 SMC_RET4(handle, status, mbox_error, x5, x6); 1104 1105 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE: 1106 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1107 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1108 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1109 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 1110 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1111 x7, true, &mbox_error, &send_id); 1112 SMC_RET4(handle, status, mbox_error, x5, x6); 1113 1114 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 1115 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1116 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1117 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1118 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1119 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1120 x7, true, &mbox_error); 1121 SMC_RET4(handle, status, mbox_error, x5, x6); 1122 1123 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT: 1124 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1125 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3, 1126 x4, x5, &mbox_error); 1127 SMC_RET2(handle, status, mbox_error); 1128 1129 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 1130 status = intel_fcs_ecdsa_get_pubkey_finalize(x1, x2, x3, 1131 (uint32_t *) &x4, &mbox_error); 1132 SMC_RET4(handle, status, mbox_error, x3, x4); 1133 1134 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT: 1135 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1136 status = intel_fcs_ecdh_request_init(x1, x2, x3, 1137 x4, x5, &mbox_error); 1138 SMC_RET2(handle, status, mbox_error); 1139 1140 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE: 1141 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1142 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1143 status = intel_fcs_ecdh_request_finalize(x1, x2, x3, 1144 x4, x5, (uint32_t *) &x6, &mbox_error); 1145 SMC_RET4(handle, status, mbox_error, x5, x6); 1146 1147 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT: 1148 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1149 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5, 1150 &mbox_error); 1151 SMC_RET2(handle, status, mbox_error); 1152 1153 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE: 1154 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1155 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1156 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1157 x5, x6, false, &send_id); 1158 SMC_RET1(handle, status); 1159 1160 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE: 1161 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1162 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1163 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1164 x5, x6, true, &send_id); 1165 SMC_RET1(handle, status); 1166 1167 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 1168 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 1169 &mbox_error); 1170 SMC_RET4(handle, status, mbox_error, x1, retval64); 1171 1172 case INTEL_SIP_SMC_SVC_VERSION: 1173 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 1174 SIP_SVC_VERSION_MAJOR, 1175 SIP_SVC_VERSION_MINOR); 1176 1177 default: 1178 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 1179 cookie, handle, flags); 1180 } 1181 } 1182 1183 uintptr_t sip_smc_handler(uint32_t smc_fid, 1184 u_register_t x1, 1185 u_register_t x2, 1186 u_register_t x3, 1187 u_register_t x4, 1188 void *cookie, 1189 void *handle, 1190 u_register_t flags) 1191 { 1192 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK; 1193 1194 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN && 1195 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) { 1196 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4, 1197 cookie, handle, flags); 1198 } else { 1199 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4, 1200 cookie, handle, flags); 1201 } 1202 } 1203 1204 DECLARE_RT_SVC( 1205 socfpga_sip_svc, 1206 OEN_SIP_START, 1207 OEN_SIP_END, 1208 SMC_TYPE_FAST, 1209 NULL, 1210 sip_smc_handler 1211 ); 1212 1213 DECLARE_RT_SVC( 1214 socfpga_sip_svc_std, 1215 OEN_SIP_START, 1216 OEN_SIP_END, 1217 SMC_TYPE_YIELD, 1218 NULL, 1219 sip_smc_handler 1220 ); 1221