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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Drockchip-mipi-dphy-rx0.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC MIPI RX0 D-PHY Device Tree Bindings
10 - Helen Koike <helen.koike@collabora.com>
11 - Ezequiel Garcia <ezequiel@collabora.com>
14 The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to
19 const: rockchip,rk3399-mipi-dphy-rx0
23 - description: MIPI D-PHY ref clock
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H A Drockchip,px30-dsi-dphy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip MIPI DPHY with additional LVDS/TTL modes
10 - Heiko Stuebner <heiko@sntech.de>
13 "#phy-cells":
18 - rockchip,px30-dsi-dphy
19 - rockchip,rk3128-dsi-dphy
20 - rockchip,rk3368-dsi-dphy
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H A Dphy-rockchip-inno-mipi-dphy.txt1 ROCKCHIP MIPI DPHY WITH INNO IP BLOCK
4 - compatible : must be one of:
5 "rockchip,rk1808-mipi-dphy";
6 "rockchip,rv1126-mipi-dphy";
7 - reg : the address offset of register for mipi-dphy configuration.
8 - #phy-cells : must be 0. See ./phy-bindings.txt for details.
9 - clocks and clock-names:
10 - the "pclk" clock is required by the phy module, used to register
12 - the "ref" clock is used to get the rate of the reference clock
14 - clock-output-names: from common clock binding.
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H A Dmixel,mipi-dsi-phy.txt3 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
4 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
8 - compatible: Must be:
9 - "fsl,imx8mq-mipi-dphy"
10 - clocks: Must contain an entry for each entry in clock-names.
11 - clock-names: Must contain the following entries:
12 - "phy_ref": phandle and specifier referring to the DPHY ref clock
13 - reg: the register range of the PHY controller
14 - #phy-cells: number of cells in PHY, as defined in
15 Documentation/devicetree/bindings/phy/phy-bindings.txt
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H A Dsamsung-phy.txt1 Samsung S5P/Exynos SoC series MIPI CSIS/DSIM DPHY
2 -------------------------------------------------
5 - compatible : should be one of the listed compatibles:
6 - "samsung,s5pv210-mipi-video-phy"
7 - "samsung,exynos5420-mipi-video-phy"
8 - "samsung,exynos5433-mipi-video-phy"
9 - #phy-cells : from the generic phy bindings, must be 1;
12 - syscon - phandle to the PMU system controller
15 - samsung,pmu-syscon - phandle to the PMU system controller
16 - samsung,disp-sysreg - phandle to the DISP system registers controller
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/
H A Drockchip-mipi-dphy.txt1 Rockchip SoC MIPI RX D-PHY
2 -------------------------------------------------------------
5 - compatible: value should be one of the following
6 "rockchip,rk1808-mipi-dphy-rx"
7 "rockchip,rk3288-mipi-dphy"
8 "rockchip,rk3326-mipi-dphy"
9 "rockchip,rk3368-mipi-dphy"
10 "rockchip,rk3399-mipi-dphy"
11 "rockchip,rv1126-csi-dphy"
12 - clocks : list of clock specifiers, corresponding to entries in
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H A Dimx.txt5 ---------------------------
12 - compatible : "fsl,imx-capture-subsystem";
13 - ports : Should contain a list of phandles pointing to camera
18 capture-subsystem {
19 compatible = "fsl,imx-capture-subsystem";
25 --------------
27 This is the device node for the MIPI CSI-2 Receiver core in the i.MX
28 SoC. This is a Synopsys Designware MIPI CSI-2 host controller core
29 combined with a D-PHY core mixed into the same register block. In
30 addition this device consists of an i.MX-specific "CSI2IPU gasket"
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/rockchip/
H A Ddw_mipi_dsi_rockchip.txt5 - #address-cells: Should be <1>.
6 - #size-cells: Should be <0>.
7 - compatible: one of
8 "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"
9 "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"
10 "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"
11 - reg: Represent the physical address range of the controller.
12 - interrupts: Represent the controller's interrupt to the CPU(s).
13 - clocks, clock-names: Phandles to the controller's pll reference
14 clock(ref) when using an internal dphy and APB clock(pclk).
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/bridge/
H A Dnwl-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Northwest Logic MIPI-DSI controller on i.MX SoCs
10 - Guido Gúnther <agx@sigxcpu.org>
11 - Robert Chiras <robert.chiras@nxp.com>
14 NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
15 the SOCs NWL MIPI-DSI host controller.
18 - $ref: ../dsi-controller.yaml#
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/
H A Dallwinner,sun6i-a31-mipi-dsi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 MIPI-DSI Controller Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - allwinner,sun6i-a31-mipi-dsi
17 - allwinner,sun50i-a64-mipi-dsi
29 - description: Bus Clock
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/OK3568_Linux_fs/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-dphy-rx0.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Rockchip MIPI Synopsys DPHY RX0 driver
11 * chromeos-4.4 branch.
14 * Jacob Chen <jacob2.chen@rock-chips.com>
15 * Shunqian Zheng <zhengsq@rock-chips.com>
26 #include <linux/phy/phy-mipi-dphy.h>
65 "dphy-ref",
66 "dphy-cfg",
111 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
163 const struct dphy_reg *reg = &priv->drv_data->regs[index]; in rk_dphy_write_grf()
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H A Dphy-rockchip-mipi-rx.c2 * Rockchip MIPI RX Synopsys/Innosilicon DPHY driver
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
46 #include <media/media-entity.h>
47 #include <media/v4l2-ctrls.h>
48 #include <media/v4l2-fwnode.h>
49 #include <media/v4l2-subdev.h>
50 #include <media/v4l2-device.h>
129 /* Configure the count time of the THS-SETTLE by protocol. */
341 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
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H A Dphy-rockchip-inno-dsidphy.c1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
11 #include <linux/clk-provider.h>
19 #include <linux/phy/phy-mipi-dphy.h>
312 orig = readl(inno->phy_base + reg); in phy_update_bits()
315 writel(tmp, inno->phy_base + reg); in phy_update_bits()
323 orig = readl(inno->host_base + reg); in host_update_bits()
326 writel(tmp, inno->host_base + reg); in host_update_bits()
332 unsigned long prate = clk_get_rate(inno->ref_clk); in inno_dsidphy_pll_calc_rate()
343 * PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2 in inno_dsidphy_pll_calc_rate()
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H A Dphy-rockchip-samsung-dcphy.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Guochun Huang <hero.huang@rock-chips.com>
19 #include <media/v4l2-ctrls.h>
20 #include <media/v4l2-fwnode.h>
21 #include <media/v4l2-subdev.h>
22 #include <media/v4l2-device.h>
23 #include "phy-rockchip-csi2-dphy-common.h"
24 #include "phy-rockchip-samsung-dcphy.h"
1278 csi_dphy->dphy_param.lp_vol_ref != 3 && in samsung_mipi_dcphy_bias_block_enable()
1279 csi_dphy->dphy_param.lp_vol_ref < 0x7) { in samsung_mipi_dcphy_bias_block_enable()
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H A Dphy-rockchip-inno-mipi-dphy.c17 #include <linux/clk-provider.h>
280 regmap_update_bits(inno->regmap, reg, mask, val); in inno_update_bits()
327 switch (inno->lanes) { in inno_mipi_dphy_lane_enable()
354 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv)); in inno_mipi_dphy_pll_enable()
356 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv >> 8)); in inno_mipi_dphy_pll_enable()
358 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv)); in inno_mipi_dphy_pll_enable()
380 timing->clkmiss = 0; in mipi_dphy_timing_get_default()
382 * The D-PHY spec define the clk post min time is 60ns + 52UI and in mipi_dphy_timing_get_default()
385 timing->clkpost = 200 + 52 * period / PSEC_PER_NSEC; in mipi_dphy_timing_get_default()
386 timing->clkpre = 8 * period / PSEC_PER_NSEC; in mipi_dphy_timing_get_default()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/
H A Drockchip-mipi-csi-tx.c1 // SPDX-License-Identifier: GPL-2.0+
30 #include "rockchip-mipi-csi-tx.h"
74 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
77 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
78 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0x1f)
111 /* The table is based on 27MHz DPHY pll reference clock. */
180 const u32 field = csi->pdata->csi0_grf_reg_fields[index]; in grf_field_write()
184 if (!field || !csi->grf) in grf_field_write()
191 regmap_write(csi->grf, reg, (val << lsb) | (GENMASK(msb, lsb) << 16)); in grf_field_write()
196 writel(v, csi->regs + offset); in csi_writel()
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H A Ddw-mipi-dsi-rockchip.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Chris Zhong <zyw@rock-chips.com>
6 * Nickey Yang <nickey.yang@rock-chips.com>
41 #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
93 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
96 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
97 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf)
285 /* dual-channel */
289 /* optional external dphy */
315 /* The table is based on 27MHz DPHY pll reference clock. */
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3399.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/soc/rockchip-system-status.h>
14 #include <dt-bindings/suspend/rockchip-rk3399.h>
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H A Drk3562.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3562-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/rk3562-power.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/soc/rockchip-system-status.h>
14 #include <dt-bindings/suspend/rockchip-rk3562.h>
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/allwinner/
H A Dsun50i-a64.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
7 #include <dt-bindings/clock/sun8i-de2.h>
8 #include <dt-bindings/clock/sun8i-r-ccu.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/reset/sun50i-a64-ccu.h>
11 #include <dt-bindings/reset/sun8i-de2.h>
12 #include <dt-bindings/reset/sun8i-r-ccu.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/freescale/
H A Dimx8mq.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
7 #include <dt-bindings/clock/imx8mq-clock.h>
8 #include <dt-bindings/power/imx8mq-power.h>
9 #include <dt-bindings/reset/imx8mq-reset.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include "dt-bindings/input/input.h"
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include "imx8mq-pinfunc.h"
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/bridge/
H A Dnwl-dsi.c1 // SPDX-License-Identifier: GPL-2.0+
33 #include "nwl-dsi.h"
35 #define DRV_NAME "nwl-dsi"
85 * 2. Configure DSI Host and DPHY and enable DPHY
136 int ret = dsi->error; in nwl_dsi_clear_error()
138 dsi->error = 0; in nwl_dsi_clear_error()
146 if (dsi->error) in nwl_dsi_write()
149 ret = regmap_write(dsi->regmap, reg, val); in nwl_dsi_write()
151 DRM_DEV_ERROR(dsi->dev, in nwl_dsi_write()
154 dsi->error = ret; in nwl_dsi_write()
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/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drk3562.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3562-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/rk3562-power.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/soc/rockchip-system-status.h>
14 #include <dt-bindings/thermal/thermal.h>
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_7nm.c2 * SPDX-License-Identifier: GPL-2.0
13 void __iomem *base = phy->base; in dsi_phy_hw_v4_0_is_pll_on()
24 void __iomem *lane_base = phy->lane_base; in dsi_phy_hw_v4_0_config_lpcdrx()
45 void __iomem *lane_base = phy->lane_base; in dsi_phy_hw_v4_0_lane_settings()
47 if (phy->cfg->type == MSM_DSI_PHY_7NM_V4_1) in dsi_phy_hw_v4_0_lane_settings()
79 struct msm_dsi_dphy_timing *timing = &phy->timing; in dsi_7nm_phy_enable()
80 void __iomem *base = phy->base; in dsi_7nm_phy_enable()
89 DRM_DEV_ERROR(&phy->pdev->dev, in dsi_7nm_phy_enable()
90 "%s: D-PHY timing calculation failed\n", __func__); in dsi_7nm_phy_enable()
91 return -EINVAL; in dsi_7nm_phy_enable()
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi14 #include <dt-bindings/clock/mt8173-clk.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/memory/mt8173-larb-port.h>
18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/power/mt8173-power.h>
20 #include <dt-bindings/reset/mt8173-resets.h>
21 #include <dt-bindings/gce/mt8173-gce.h>
22 #include <dt-bindings/thermal/thermal.h>
23 #include "mt8173-pinfunc.h"
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