1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Rockchip MIPI DPHY with additional LVDS/TTL modes 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Heiko Stuebner <heiko@sntech.de> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunproperties: 13*4882a593Smuzhiyun "#phy-cells": 14*4882a593Smuzhiyun const: 0 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun compatible: 17*4882a593Smuzhiyun enum: 18*4882a593Smuzhiyun - rockchip,px30-dsi-dphy 19*4882a593Smuzhiyun - rockchip,rk3128-dsi-dphy 20*4882a593Smuzhiyun - rockchip,rk3368-dsi-dphy 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun reg: 23*4882a593Smuzhiyun maxItems: 1 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun clocks: 26*4882a593Smuzhiyun items: 27*4882a593Smuzhiyun - description: PLL reference clock 28*4882a593Smuzhiyun - description: Module clock 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun clock-names: 31*4882a593Smuzhiyun items: 32*4882a593Smuzhiyun - const: ref 33*4882a593Smuzhiyun - const: pclk 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun power-domains: 36*4882a593Smuzhiyun maxItems: 1 37*4882a593Smuzhiyun description: phandle to the associated power domain 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun resets: 40*4882a593Smuzhiyun items: 41*4882a593Smuzhiyun - description: exclusive PHY reset line 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun reset-names: 44*4882a593Smuzhiyun items: 45*4882a593Smuzhiyun - const: apb 46*4882a593Smuzhiyun 47*4882a593Smuzhiyunrequired: 48*4882a593Smuzhiyun - "#phy-cells" 49*4882a593Smuzhiyun - compatible 50*4882a593Smuzhiyun - reg 51*4882a593Smuzhiyun - clocks 52*4882a593Smuzhiyun - clock-names 53*4882a593Smuzhiyun - resets 54*4882a593Smuzhiyun - reset-names 55*4882a593Smuzhiyun 56*4882a593SmuzhiyunadditionalProperties: false 57*4882a593Smuzhiyun 58*4882a593Smuzhiyunexamples: 59*4882a593Smuzhiyun - | 60*4882a593Smuzhiyun dsi_dphy: phy@ff2e0000 { 61*4882a593Smuzhiyun compatible = "rockchip,px30-dsi-dphy"; 62*4882a593Smuzhiyun reg = <0xff2e0000 0x10000>; 63*4882a593Smuzhiyun clocks = <&pmucru 13>, <&cru 12>; 64*4882a593Smuzhiyun clock-names = "ref", "pclk"; 65*4882a593Smuzhiyun resets = <&cru 12>; 66*4882a593Smuzhiyun reset-names = "apb"; 67*4882a593Smuzhiyun #phy-cells = <0>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun... 71