1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3562-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/power/rk3562-power.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/soc/rockchip-system-status.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 compatible = "rockchip,rk3562"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 csi2dphy0 = &csi2_dphy0; 25 csi2dphy1 = &csi2_dphy1; 26 csi2dphy2 = &csi2_dphy2; 27 csi2dphy3 = &csi2_dphy3; 28 csi2dphy4 = &csi2_dphy4; 29 csi2dphy5 = &csi2_dphy5; 30 ethernet0 = &gmac0; 31 ethernet1 = &gmac1; 32 gpio0 = &gpio0; 33 gpio1 = &gpio1; 34 gpio2 = &gpio2; 35 gpio3 = &gpio3; 36 gpio4 = &gpio4; 37 i2c0 = &i2c0; 38 i2c1 = &i2c1; 39 i2c2 = &i2c2; 40 i2c3 = &i2c3; 41 i2c4 = &i2c4; 42 i2c5 = &i2c5; 43 rkcif_mipi_lvds0= &rkcif_mipi_lvds; 44 rkcif_mipi_lvds1= &rkcif_mipi_lvds1; 45 rkcif_mipi_lvds2= &rkcif_mipi_lvds2; 46 rkcif_mipi_lvds3= &rkcif_mipi_lvds3; 47 serial0 = &uart0; 48 serial1 = &uart1; 49 serial2 = &uart2; 50 serial3 = &uart3; 51 serial4 = &uart4; 52 serial5 = &uart5; 53 serial6 = &uart6; 54 serial7 = &uart7; 55 serial8 = &uart8; 56 serial9 = &uart9; 57 spi0 = &spi0; 58 spi1 = &spi1; 59 spi2 = &spi2; 60 spi3 = &sfc; 61 }; 62 63 clocks { 64 compatible = "simple-bus"; 65 #address-cells = <2>; 66 #size-cells = <2>; 67 ranges; 68 69 xin32k: xin32k { 70 compatible = "fixed-clock"; 71 #clock-cells = <0>; 72 clock-frequency = <32768>; 73 clock-output-names = "xin32k"; 74 }; 75 76 xin24m: xin24m { 77 compatible = "fixed-clock"; 78 #clock-cells = <0>; 79 clock-frequency = <24000000>; 80 clock-output-names = "xin24m"; 81 }; 82 83 aclk_vepu: aclk_vepu@ff100324 { 84 compatible = "rockchip,rk3562-clock-gate-link"; 85 reg = <0 0xff100324 0 0x10>; 86 clock-names = "link"; 87 clocks = <&cru ACLK_ISP>; 88 #power-domain-cells = <1>; 89 #clock-cells = <0>; 90 }; 91 92 aclk_vdpu: aclk_vdpu@ff100328 { 93 compatible = "rockchip,rk3562-clock-gate-link"; 94 reg = <0 0xff100328 0 0x10>; 95 clock-names = "link"; 96 clocks = <&cru ACLK_TOP_VIO>; 97 #power-domain-cells = <1>; 98 #clock-cells = <0>; 99 }; 100 101 aclk_vi_isp: aclk_vi_isp@ff10032c { 102 compatible = "rockchip,rk3562-clock-gate-link"; 103 reg = <0 0xff10032c 0 0x10>; 104 clock-names = "link"; 105 clocks = <&cru ACLK_TOP_VIO>; 106 #power-domain-cells = <1>; 107 #clock-cells = <0>; 108 }; 109 110 aclk_vo: aclk_vo@ff100334 { 111 compatible = "rockchip,rk3562-clock-gate-link"; 112 reg = <0 0xff100334 0 0x10>; 113 clock-names = "link"; 114 clocks = <&cru ACLK_TOP_VIO>; 115 #power-domain-cells = <1>; 116 #clock-cells = <0>; 117 }; 118 119 aclk_rga_jdec: aclk_rga_jdec@ff100338 { 120 compatible = "rockchip,rk3562-clock-gate-link"; 121 reg = <0 0xff100338 0 0x10>; 122 clock-names = "link"; 123 clocks = <&cru ACLK_VOP>; 124 #power-domain-cells = <1>; 125 #clock-cells = <0>; 126 }; 127 }; 128 129 cpus { 130 #address-cells = <2>; 131 #size-cells = <0>; 132 133 cpu0: cpu@0 { 134 device_type = "cpu"; 135 compatible = "arm,cortex-a53"; 136 reg = <0x0 0x0>; 137 enable-method = "psci"; 138 clocks = <&cru ARMCLK>; 139 operating-points-v2 = <&cpu0_opp_table>; 140 }; 141 cpu1: cpu@1 { 142 device_type = "cpu"; 143 compatible = "arm,cortex-a53"; 144 reg = <0x0 0x1>; 145 enable-method = "psci"; 146 clocks = <&cru ARMCLK>; 147 operating-points-v2 = <&cpu0_opp_table>; 148 }; 149 cpu2: cpu@2 { 150 device_type = "cpu"; 151 compatible = "arm,cortex-a53"; 152 reg = <0x0 0x2>; 153 enable-method = "psci"; 154 clocks = <&cru ARMCLK>; 155 operating-points-v2 = <&cpu0_opp_table>; 156 }; 157 cpu3: cpu@3 { 158 device_type = "cpu"; 159 compatible = "arm,cortex-a53"; 160 reg = <0x0 0x3>; 161 enable-method = "psci"; 162 clocks = <&cru ARMCLK>; 163 operating-points-v2 = <&cpu0_opp_table>; 164 }; 165 }; 166 167 cpu0_opp_table: cpu0-opp-table { 168 compatible = "operating-points-v2"; 169 opp-shared; 170 171 nvmem-cells = <&cpu_leakage>; 172 nvmem-cell-names = "leakage"; 173 174 opp-408000000 { 175 opp-hz = /bits/ 64 <408000000>; 176 opp-microvolt = <900000 900000 1100000>; 177 clock-latency-ns = <40000>; 178 opp-suspend; 179 }; 180 opp-600000000 { 181 opp-hz = /bits/ 64 <600000000>; 182 opp-microvolt = <900000 900000 1100000>; 183 clock-latency-ns = <40000>; 184 }; 185 opp-816000000 { 186 opp-hz = /bits/ 64 <816000000>; 187 opp-microvolt = <900000 900000 1100000>; 188 clock-latency-ns = <40000>; 189 }; 190 opp-1008000000 { 191 opp-hz = /bits/ 64 <1008000000>; 192 opp-microvolt = <900000 900000 1100000>; 193 clock-latency-ns = <40000>; 194 }; 195 opp-1200000000 { 196 opp-hz = /bits/ 64 <1200000000>; 197 opp-microvolt = <900000 900000 1100000>; 198 clock-latency-ns = <40000>; 199 }; 200 }; 201 202 arm-pmu { 203 compatible = "arm,cortex-a53-pmu"; 204 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 208 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 209 }; 210 211 cpuinfo { 212 compatible = "rockchip,cpuinfo"; 213 nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>; 214 nvmem-cell-names = "id", "cpu-version", "cpu-code"; 215 }; 216 217 /* dphy0 full mode */ 218 csi2_dphy0: csi2-dphy0 { 219 compatible = "rockchip,rk3562-csi2-dphy"; 220 rockchip,hw = <&csi2_dphy0_hw>; 221 status = "disabled"; 222 }; 223 224 /* dphy0 split mode 01 */ 225 csi2_dphy1: csi2-dphy1 { 226 compatible = "rockchip,rk3562-csi2-dphy"; 227 rockchip,hw = <&csi2_dphy0_hw>; 228 status = "disabled"; 229 }; 230 231 /* dphy0 split mode 23 */ 232 csi2_dphy2: csi2-dphy2 { 233 compatible = "rockchip,rk3562-csi2-dphy"; 234 rockchip,hw = <&csi2_dphy0_hw>; 235 status = "disabled"; 236 }; 237 238 /* dphy1 full mode */ 239 csi2_dphy3: csi2-dphy3 { 240 compatible = "rockchip,rk3562-csi2-dphy"; 241 rockchip,hw = <&csi2_dphy1_hw>; 242 status = "disabled"; 243 }; 244 245 /* dphy1 split mode 01 */ 246 csi2_dphy4: csi2-dphy4 { 247 compatible = "rockchip,rk3562-csi2-dphy"; 248 rockchip,hw = <&csi2_dphy1_hw>; 249 status = "disabled"; 250 }; 251 252 /* dphy1 split mode 23 */ 253 csi2_dphy5: csi2-dphy5 { 254 compatible = "rockchip,rk3562-csi2-dphy"; 255 rockchip,hw = <&csi2_dphy1_hw>; 256 status = "disabled"; 257 }; 258 259 display_subsystem: display-subsystem { 260 compatible = "rockchip,display-subsystem"; 261 ports = <&vop_out>; 262 status = "disabled"; 263 }; 264 265 firmware: firmware { 266 scmi: scmi { 267 compatible = "arm,scmi-smc"; 268 shmem = <&scmi_shmem>; 269 arm,smc-id = <0x82000010>; 270 #address-cells = <1>; 271 #size-cells = <0>; 272 273 scmi_clk: protocol@14 { 274 reg = <0x14>; 275 #clock-cells = <1>; 276 }; 277 }; 278 }; 279 280 mpp_srv: mpp-srv { 281 compatible = "rockchip,mpp-service"; 282 rockchip,taskqueue-count = <3>; 283 rockchip,resetgroup-count = <3>; 284 status = "disabled"; 285 }; 286 287 psci: psci { 288 compatible = "arm,psci-1.0"; 289 method = "smc"; 290 }; 291 292 rkcif_mipi_lvds: rkcif-mipi-lvds { 293 compatible = "rockchip,rkcif-mipi-lvds"; 294 rockchip,hw = <&rkcif>; 295 iommus = <&rkcif_mmu>; 296 status = "disabled"; 297 }; 298 299 rkcif_mipi_lvds_sditf: rkcif-mipi-lvds-sditf { 300 compatible = "rockchip,rkcif-sditf"; 301 rockchip,cif = <&rkcif_mipi_lvds>; 302 status = "disabled"; 303 }; 304 305 rkcif_mipi_lvds_sditf_vir1: rkcif-mipi-lvds-sditf-vir1 { 306 compatible = "rockchip,rkcif-sditf"; 307 rockchip,cif = <&rkcif_mipi_lvds>; 308 status = "disabled"; 309 }; 310 311 rkcif_mipi_lvds_sditf_vir2: rkcif-mipi-lvds-sditf-vir2 { 312 compatible = "rockchip,rkcif-sditf"; 313 rockchip,cif = <&rkcif_mipi_lvds>; 314 status = "disabled"; 315 }; 316 317 rkcif_mipi_lvds_sditf_vir3: rkcif-mipi-lvds-sditf-vir3 { 318 compatible = "rockchip,rkcif-sditf"; 319 rockchip,cif = <&rkcif_mipi_lvds>; 320 status = "disabled"; 321 }; 322 323 rkcif_mipi_lvds1: rkcif-mipi-lvds1 { 324 compatible = "rockchip,rkcif-mipi-lvds"; 325 rockchip,hw = <&rkcif>; 326 iommus = <&rkcif_mmu>; 327 status = "disabled"; 328 }; 329 330 rkcif_mipi_lvds1_sditf: rkcif-mipi-lvds1-sditf { 331 compatible = "rockchip,rkcif-sditf"; 332 rockchip,cif = <&rkcif_mipi_lvds1>; 333 status = "disabled"; 334 }; 335 336 rkcif_mipi_lvds1_sditf_vir1: rkcif-mipi-lvds1-sditf-vir1 { 337 compatible = "rockchip,rkcif-sditf"; 338 rockchip,cif = <&rkcif_mipi_lvds1>; 339 status = "disabled"; 340 }; 341 342 rkcif_mipi_lvds1_sditf_vir2: rkcif-mipi-lvds1-sditf-vir2 { 343 compatible = "rockchip,rkcif-sditf"; 344 rockchip,cif = <&rkcif_mipi_lvds1>; 345 status = "disabled"; 346 }; 347 348 rkcif_mipi_lvds1_sditf_vir3: rkcif-mipi-lvds1-sditf-vir3 { 349 compatible = "rockchip,rkcif-sditf"; 350 rockchip,cif = <&rkcif_mipi_lvds1>; 351 status = "disabled"; 352 }; 353 354 rkcif_mipi_lvds2: rkcif-mipi-lvds2 { 355 compatible = "rockchip,rkcif-mipi-lvds"; 356 rockchip,hw = <&rkcif>; 357 iommus = <&rkcif_mmu>; 358 status = "disabled"; 359 }; 360 361 rkcif_mipi_lvds2_sditf: rkcif-mipi-lvds2-sditf { 362 compatible = "rockchip,rkcif-sditf"; 363 rockchip,cif = <&rkcif_mipi_lvds2>; 364 status = "disabled"; 365 }; 366 367 rkcif_mipi_lvds2_sditf_vir1: rkcif-mipi-lvds2-sditf-vir1 { 368 compatible = "rockchip,rkcif-sditf"; 369 rockchip,cif = <&rkcif_mipi_lvds2>; 370 status = "disabled"; 371 }; 372 373 rkcif_mipi_lvds2_sditf_vir2: rkcif-mipi-lvds2-sditf-vir2 { 374 compatible = "rockchip,rkcif-sditf"; 375 rockchip,cif = <&rkcif_mipi_lvds2>; 376 status = "disabled"; 377 }; 378 379 rkcif_mipi_lvds2_sditf_vir3: rkcif-mipi-lvds2-sditf-vir3 { 380 compatible = "rockchip,rkcif-sditf"; 381 rockchip,cif = <&rkcif_mipi_lvds2>; 382 status = "disabled"; 383 }; 384 385 rkcif_mipi_lvds3: rkcif-mipi-lvds3 { 386 compatible = "rockchip,rkcif-mipi-lvds"; 387 rockchip,hw = <&rkcif>; 388 iommus = <&rkcif_mmu>; 389 status = "disabled"; 390 }; 391 392 rkcif_mipi_lvds3_sditf: rkcif-mipi-lvds3-sditf { 393 compatible = "rockchip,rkcif-sditf"; 394 rockchip,cif = <&rkcif_mipi_lvds3>; 395 status = "disabled"; 396 }; 397 398 rkcif_mipi_lvds3_sditf_vir1: rkcif-mipi-lvds3-sditf-vir1 { 399 compatible = "rockchip,rkcif-sditf"; 400 rockchip,cif = <&rkcif_mipi_lvds3>; 401 status = "disabled"; 402 }; 403 404 rkcif_mipi_lvds3_sditf_vir2: rkcif-mipi-lvds3-sditf-vir2 { 405 compatible = "rockchip,rkcif-sditf"; 406 rockchip,cif = <&rkcif_mipi_lvds3>; 407 status = "disabled"; 408 }; 409 410 rkcif_mipi_lvds3_sditf_vir3: rkcif-mipi-lvds3-sditf-vir3 { 411 compatible = "rockchip,rkcif-sditf"; 412 rockchip,cif = <&rkcif_mipi_lvds3>; 413 status = "disabled"; 414 }; 415 416 rkisp_vir0: rkisp-vir0 { 417 compatible = "rockchip,rkisp-vir"; 418 rockchip,hw = <&rkisp>; 419 status = "disabled"; 420 }; 421 422 rkisp_vir1: rkisp-vir1 { 423 compatible = "rockchip,rkisp-vir"; 424 rockchip,hw = <&rkisp>; 425 status = "disabled"; 426 }; 427 428 rkisp_vir2: rkisp-vir2 { 429 compatible = "rockchip,rkisp-vir"; 430 rockchip,hw = <&rkisp>; 431 status = "disabled"; 432 }; 433 434 rkisp_vir3: rkisp-vir3 { 435 compatible = "rockchip,rkisp-vir"; 436 rockchip,hw = <&rkisp>; 437 status = "disabled"; 438 }; 439 440 thermal_zones: thermal-zones { 441 soc_thermal: soc-thermal { 442 polling-delay-passive = <20>; /* milliseconds */ 443 polling-delay = <1000>; /* milliseconds */ 444 445 thermal-sensors = <&tsadc 0>; 446 trips { 447 soc_crit: soc-crit { 448 /* millicelsius */ 449 temperature = <115000>; 450 /* millicelsius */ 451 hysteresis = <2000>; 452 type = "critical"; 453 }; 454 }; 455 }; 456 }; 457 458 timer { 459 compatible = "arm,armv8-timer"; 460 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 461 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 462 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 463 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 464 }; 465 466 scmi_shmem: scmi-shmem@10f000 { 467 compatible = "arm,scmi-shmem"; 468 reg = <0x0 0x0010f000 0x0 0x100>; 469 }; 470 471 usbdrd30: usbdrd { 472 compatible = "rockchip,rk3562-dwc3", "rockchip,rk3399-dwc3"; 473 clocks = <&cru CLK_USB3OTG_REF>, <&cru CLK_USB3OTG_SUSPEND>, 474 <&cru ACLK_USB3OTG>, <&cru PCLK_PHP>; 475 clock-names = "ref", "suspend", "bus", "pipe_clk"; 476 #address-cells = <2>; 477 #size-cells = <2>; 478 ranges; 479 status = "disabled"; 480 481 usbdrd_dwc3: usb@fe500000 { 482 compatible = "snps,dwc3"; 483 reg = <0x0 0xfe500000 0x0 0x400000>; 484 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 485 dr_mode = "otg"; 486 phys = <&u2phy_otg>, <&combphy_pu PHY_TYPE_USB3>; 487 phy-names = "usb2-phy", "usb3-phy"; 488 phy_type = "utmi_wide"; 489 power-domains = <&power RK3562_PD_PHP>; 490 resets = <&cru SRST_USB3OTG>; 491 reset-names = "usb3-otg"; 492 snps,dis_enblslpm_quirk; 493 snps,dis-u1-entry-quirk; 494 snps,dis-u2-entry-quirk; 495 snps,dis-u2-freeclk-exists-quirk; 496 snps,dis-del-phy-power-chg-quirk; 497 snps,dis-tx-ipgap-linecheck-quirk; 498 snps,dis_rxdet_inp3_quirk; 499 quirk-skip-phy-init; 500 status = "disabled"; 501 }; 502 }; 503 504 gic: interrupt-controller@fe901000 { 505 compatible = "arm,gic-400"; 506 #interrupt-cells = <3>; 507 #address-cells = <0>; 508 interrupt-controller; 509 reg = <0x0 0xfe901000 0 0x1000>, 510 <0x0 0xfe902000 0 0x2000>, 511 <0x0 0xfe904000 0 0x2000>, 512 <0x0 0xfe906000 0 0x2000>; 513 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 514 }; 515 516 usb_host0_ehci: usb@fed00000 { 517 compatible = "generic-ehci"; 518 reg = <0x0 0xfed00000 0x0 0x40000>; 519 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 520 clocks = <&cru HCLK_USB2HOST>, <&cru HCLK_USB2HOST_ARB>, 521 <&u2phy>; 522 clock-names = "usbhost", "arbiter", "utmi"; 523 phys = <&u2phy_host>; 524 phy-names = "usb2-phy"; 525 status = "disabled"; 526 }; 527 528 usb_host0_ohci: usb@fed40000 { 529 compatible = "generic-ohci"; 530 reg = <0x0 0xfed40000 0x0 0x40000>; 531 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&cru HCLK_USB2HOST>, <&cru HCLK_USB2HOST_ARB>, 533 <&u2phy>; 534 clock-names = "usbhost", "arbiter", "utmi"; 535 phys = <&u2phy_host>; 536 phy-names = "usb2-phy"; 537 status = "disabled"; 538 }; 539 540 qos_dma2ddr: qos@fee03800 { 541 compatible = "syscon"; 542 reg = <0x0 0xfee03800 0x0 0x20>; 543 }; 544 545 qos_mcu: qos@fee10000 { 546 compatible = "syscon"; 547 reg = <0x0 0xfee10000 0x0 0x20>; 548 }; 549 550 qos_dft_apb: qos@fee10100 { 551 compatible = "syscon"; 552 reg = <0x0 0xfee10100 0x0 0x20>; 553 }; 554 555 qos_gmac: qos@fee10200 { 556 compatible = "syscon"; 557 reg = <0x0 0xfee10200 0x0 0x20>; 558 }; 559 560 qos_mac100: qos@fee10300 { 561 compatible = "syscon"; 562 reg = <0x0 0xfee10300 0x0 0x20>; 563 }; 564 565 qos_dcf: qos@fee10400 { 566 compatible = "syscon"; 567 reg = <0x0 0xfee10400 0x0 0x20>; 568 }; 569 570 qos_cpu: qos@fee20000 { 571 compatible = "syscon"; 572 reg = <0x0 0xfee20000 0x0 0x20>; 573 }; 574 575 qos_daplite_apb: qos@fee20100 { 576 compatible = "syscon"; 577 reg = <0x0 0xfee20100 0x0 0x20>; 578 }; 579 580 qos_gpu: qos@fee30000 { 581 compatible = "syscon"; 582 reg = <0x0 0xfee30000 0x0 0x20>; 583 }; 584 585 qos_npu: qos@fee40000 { 586 compatible = "syscon"; 587 reg = <0x0 0xfee40000 0x0 0x20>; 588 }; 589 590 qos_rkvdec: qos@fee50000 { 591 compatible = "syscon"; 592 reg = <0x0 0xfee50000 0x0 0x20>; 593 }; 594 595 qos_vepu: qos@fee60000 { 596 compatible = "syscon"; 597 reg = <0x0 0xfee60000 0x0 0x20>; 598 }; 599 600 qos_isp: qos@fee70000 { 601 compatible = "syscon"; 602 reg = <0x0 0xfee70000 0x0 0x20>; 603 }; 604 605 qos_vicap: qos@fee70100 { 606 compatible = "syscon"; 607 reg = <0x0 0xfee70100 0x0 0x20>; 608 }; 609 610 qos_vop: qos@fee80000 { 611 compatible = "syscon"; 612 reg = <0x0 0xfee80000 0x0 0x20>; 613 }; 614 615 qos_jpeg: qos@fee90000 { 616 compatible = "syscon"; 617 reg = <0x0 0xfee90000 0x0 0x20>; 618 }; 619 620 qos_rga_rd: qos@fee90100 { 621 compatible = "syscon"; 622 reg = <0x0 0xfee90100 0x0 0x20>; 623 }; 624 625 qos_rga_wr: qos@fee90200 { 626 compatible = "syscon"; 627 reg = <0x0 0xfee90200 0x0 0x20>; 628 }; 629 630 qos_pcie: qos@feea0000 { 631 compatible = "syscon"; 632 reg = <0x0 0xfeea0000 0x0 0x20>; 633 }; 634 635 qos_usb3: qos@feea0100 { 636 compatible = "syscon"; 637 reg = <0x0 0xfeea0100 0x0 0x20>; 638 }; 639 640 qos_crypto_apb: qos@feeb0000 { 641 compatible = "syscon"; 642 reg = <0x0 0xfeeb0000 0x0 0x20>; 643 }; 644 645 qos_crypto: qos@feeb0100 { 646 compatible = "syscon"; 647 reg = <0x0 0xfeeb0100 0x0 0x20>; 648 }; 649 650 qos_dmac: qos@feeb0200 { 651 compatible = "syscon"; 652 reg = <0x0 0xfeeb0200 0x0 0x20>; 653 }; 654 655 qos_emmc: qos@feeb0300 { 656 compatible = "syscon"; 657 reg = <0x0 0xfeeb0300 0x0 0x20>; 658 }; 659 660 qos_fspi: qos@feeb0400 { 661 compatible = "syscon"; 662 reg = <0x0 0xfeeb0400 0x0 0x20>; 663 }; 664 665 qos_rkdma: qos@feeb0500 { 666 compatible = "syscon"; 667 reg = <0x0 0xfeeb0500 0x0 0x20>; 668 }; 669 670 qos_sdmmc0: qos@feeb0600 { 671 compatible = "syscon"; 672 reg = <0x0 0xfeeb0600 0x0 0x20>; 673 }; 674 675 qos_sdmmc1: qos@feeb0700 { 676 compatible = "syscon"; 677 reg = <0x0 0xfeeb0700 0x0 0x20>; 678 }; 679 680 qos_usb2: qos@feeb0800 { 681 compatible = "syscon"; 682 reg = <0x0 0xfeeb0800 0x0 0x20>; 683 }; 684 685 pmu_grf: syscon@ff010000 { 686 compatible = "rockchip,rk3562-pmu-grf", "syscon", "simple-mfd"; 687 reg = <0x0 0xff010000 0x0 0x10000>; 688 689 reboot_mode: reboot-mode { 690 compatible = "syscon-reboot-mode"; 691 offset = <0x200>; 692 mode-bootloader = <BOOT_BL_DOWNLOAD>; 693 mode-charge = <BOOT_CHARGING>; 694 mode-fastboot = <BOOT_FASTBOOT>; 695 mode-loader = <BOOT_BL_DOWNLOAD>; 696 mode-normal = <BOOT_NORMAL>; 697 mode-recovery = <BOOT_RECOVERY>; 698 mode-ums = <BOOT_UMS>; 699 mode-panic = <BOOT_PANIC>; 700 mode-watchdog = <BOOT_WATCHDOG>; 701 }; 702 }; 703 704 sys_grf: syscon@ff030000 { 705 compatible = "rockchip,rk3562-sys-grf", "syscon", "simple-mfd"; 706 reg = <0x0 0xff030000 0x0 0x10000>; 707 708 lvds: lvds { 709 compatible = "rockchip,rk3562-lvds"; 710 phys = <&video_phy>; 711 phy-names = "phy"; 712 status = "disabled"; 713 714 ports { 715 #address-cells = <1>; 716 #size-cells = <0>; 717 718 port@0 { 719 reg = <0>; 720 #address-cells = <1>; 721 #size-cells = <0>; 722 723 lvds_in_vp0: endpoint@0 { 724 reg = <0>; 725 remote-endpoint = <&vp0_out_lvds>; 726 status = "disabled"; 727 }; 728 729 lvds_in_vp1: endpoint@1 { 730 reg = <1>; 731 remote-endpoint = <&vp1_out_lvds>; 732 status = "disabled"; 733 }; 734 }; 735 }; 736 }; 737 738 rgb: rgb { 739 compatible = "rockchip,rk3562-rgb"; 740 pinctrl-names = "default"; 741 pinctrl-0 = <&vo_pins>; 742 status = "disabled"; 743 744 ports { 745 #address-cells = <1>; 746 #size-cells = <0>; 747 748 port@0 { 749 reg = <0>; 750 #address-cells = <1>; 751 #size-cells = <0>; 752 753 rgb_in_vp0: endpoint@0 { 754 reg = <0>; 755 remote-endpoint = <&vp0_out_rgb>; 756 status = "disabled"; 757 }; 758 759 rgb_in_vp1: endpoint@1 { 760 reg = <1>; 761 remote-endpoint = <&vp1_out_rgb>; 762 status = "disabled"; 763 }; 764 }; 765 }; 766 }; 767 }; 768 769 peri_grf: syscon@ff040000 { 770 compatible = "rockchip,rk3562-peri-grf", "syscon"; 771 reg = <0x0 0xff040000 0x0 0x10000>; 772 }; 773 774 ioc_grf: syscon@ff060000 { 775 compatible = "rockchip,rk3562-ioc-grf", "syscon"; 776 reg = <0x0 0xff060000 0x0 0x30000>; 777 }; 778 779 usbphy_grf: syscon@ff090000 { 780 compatible = "rockchip,rk3562-usbphy-grf", "syscon"; 781 reg = <0x0 0xff090000 0x0 0x8000>; 782 }; 783 784 pipephy_grf: syscon@ff098000 { 785 compatible = "rockchip,rk3562-pipephy-grf", "syscon"; 786 reg = <0x0 0xff098000 0x0 0x8000>; 787 }; 788 789 cru: clock-controller@ff100000 { 790 compatible = "rockchip,rk3562-cru"; 791 reg = <0x0 0xff100000 0x0 0x40000>; 792 rockchip,grf = <&sys_grf>; 793 #clock-cells = <1>; 794 #reset-cells = <1>; 795 796 assigned-clocks = 797 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 798 <&cru ARMCLK>; 799 assigned-clock-rates = 800 <1188000000>, <1000000000>, 801 <600000000>; 802 }; 803 804 i2c0: i2c@ff200000 { 805 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; 806 reg = <0x0 0xff200000 0x0 0x1000>; 807 clocks = <&cru CLK_PMU0_I2C0>, <&cru PCLK_PMU0_I2C0>; 808 clock-names = "i2c", "pclk"; 809 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 810 pinctrl-names = "default"; 811 pinctrl-0 = <&i2c0_xfer>; 812 #address-cells = <1>; 813 #size-cells = <0>; 814 status = "disabled"; 815 }; 816 817 uart0: serial@ff210000 { 818 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 819 reg = <0x0 0xff210000 0x0 0x100>; 820 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 821 clocks = <&cru SCLK_PMU1_UART0>, <&cru PCLK_PMU1_UART0>; 822 clock-names = "baudclk", "apb_pclk"; 823 reg-shift = <2>; 824 reg-io-width = <4>; 825 dmas = <&dmac 0>; 826 status = "disabled"; 827 }; 828 829 spi0: spi@ff220000 { 830 compatible = "rockchip,rk3066-spi"; 831 reg = <0x0 0xff220000 0x0 0x1000>; 832 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 833 #address-cells = <1>; 834 #size-cells = <0>; 835 clocks = <&cru CLK_PMU1_SPI0>, <&cru PCLK_PMU1_SPI0>, <&cru PCLK_PMU1_SPI0>; 836 clock-names = "spiclk", "apb_pclk", "sclk_in"; 837 dmas = <&dmac 13>, <&dmac 12>; 838 dma-names = "tx", "rx"; 839 pinctrl-names = "default"; 840 pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>; 841 num-cs = <2>; 842 status = "disabled"; 843 }; 844 845 pwm0: pwm@ff230000 { 846 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 847 reg = <0x0 0xff230000 0x0 0x10>; 848 #pwm-cells = <3>; 849 pinctrl-names = "active"; 850 pinctrl-0 = <&pwm0m0_pins>; 851 clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; 852 clock-names = "pwm", "pclk"; 853 status = "disabled"; 854 }; 855 856 pwm1: pwm@ff230010 { 857 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 858 reg = <0x0 0xff230010 0x0 0x10>; 859 #pwm-cells = <3>; 860 pinctrl-names = "active"; 861 pinctrl-0 = <&pwm1m0_pins>; 862 clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; 863 clock-names = "pwm", "pclk"; 864 status = "disabled"; 865 }; 866 867 pwm2: pwm@ff230020 { 868 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 869 reg = <0x0 0xff230020 0x0 0x10>; 870 #pwm-cells = <3>; 871 pinctrl-names = "active"; 872 pinctrl-0 = <&pwm2m0_pins>; 873 clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; 874 clock-names = "pwm", "pclk"; 875 status = "disabled"; 876 }; 877 878 pwm3: pwm@ff230030 { 879 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 880 reg = <0x0 0xff230030 0x0 0x10>; 881 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 883 #pwm-cells = <3>; 884 pinctrl-names = "active"; 885 pinctrl-0 = <&pwm3m0_pins>; 886 clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; 887 clock-names = "pwm", "pclk"; 888 status = "disabled"; 889 }; 890 891 pmu: power-management@ff258000 { 892 compatible = "rockchip,rk3562-pmu", "syscon", "simple-mfd"; 893 reg = <0x0 0xff258000 0x0 0x1000>; 894 895 power: power-controller { 896 compatible = "rockchip,rk3562-power-controller"; 897 #power-domain-cells = <1>; 898 #address-cells = <1>; 899 #size-cells = <0>; 900 status = "okay"; 901 902 /* These power domains are grouped by VD_GPU */ 903 pd_gpu@RK3562_PD_GPU { 904 reg = <RK3562_PD_GPU>; 905 pm_qos = <&qos_gpu>; 906 }; 907 /* These power domains are grouped by VD_NPU */ 908 pd_npu@RK3562_PD_NPU { 909 reg = <RK3562_PD_NPU>; 910 pm_qos = <&qos_npu>; 911 }; 912 /* These power domains are grouped by VD_LOGIC */ 913 pd_vdpu@RK3562_PD_VDPU { 914 reg = <RK3562_PD_VDPU>; 915 pm_qos = <&qos_rkvdec>; 916 }; 917 pd_vi@RK3562_PD_VI { 918 reg = <RK3562_PD_VI>; 919 #address-cells = <1>; 920 #size-cells = <0>; 921 pm_qos = <&qos_isp>, 922 <&qos_vicap>; 923 924 pd_vepu@RK3562_PD_VEPU { 925 reg = <RK3562_PD_VEPU>; 926 pm_qos = <&qos_vepu>; 927 }; 928 }; 929 pd_vo@RK3562_PD_VO { 930 reg = <RK3562_PD_VO>; 931 #address-cells = <1>; 932 #size-cells = <0>; 933 pm_qos = <&qos_vop>; 934 935 pd_rga@RK3562_PD_RGA { 936 reg = <RK3562_PD_RGA>; 937 pm_qos = <&qos_rga_rd>, 938 <&qos_rga_wr>, 939 <&qos_jpeg>; 940 }; 941 }; 942 pd_php@RK3562_PD_PHP { 943 reg = <RK3562_PD_PHP>; 944 pm_qos = <&qos_pcie>, 945 <&qos_usb3>; 946 }; 947 }; 948 }; 949 950 pmu_mailbox: mailbox@ff290000 { 951 compatible = "rockchip,rk3562-mailbox", 952 "rockchip,rk3368-mailbox"; 953 reg = <0x0 0xff290000 0x0 0x200>; 954 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 955 clocks = <&cru PCLK_PMU1_MAILBOX>; 956 clock-names = "pclk_mailbox"; 957 #mbox-cells = <1>; 958 status = "disabled"; 959 }; 960 961 rknpu: npu@ff300000 { 962 compatible = "rockchip,rk3562-rknpu"; 963 reg = <0x0 0xff300000 0x0 0x10000>; 964 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 965 clocks = <&cru ACLK_RKNN>, <&cru HCLK_RKNN>; 966 clock-names = "aclk", "hclk"; 967 assigned-clocks = <&cru ACLK_RKNN>; 968 assigned-clock-rates = <600000000>; 969 resets = <&cru SRST_A_RKNN>, <&cru SRST_H_RKNN>; 970 reset-names = "srst_a", "srst_h"; 971 power-domains = <&power RK3562_PD_NPU>; 972 iommus = <&rknpu_mmu>; 973 status = "disabled"; 974 }; 975 976 rknpu_mmu: iommu@ff30b000 { 977 compatible = "rockchip,iommu-v2"; 978 reg = <0x0 0xff30b000 0x0 0x40>; 979 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 980 interrupt-names = "rknpu_mmu"; 981 clocks = <&cru ACLK_RKNN>, <&cru HCLK_RKNN>; 982 clock-names = "aclk", "iface"; 983 power-domains = <&power RK3562_PD_NPU>; 984 #iommu-cells = <0>; 985 status = "disabled"; 986 }; 987 988 gpu: gpu@ff320000 { 989 compatible = "arm,mali-bifrost"; 990 reg = <0x0 0xff320000 0x0 0x4000>; 991 992 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 995 interrupt-names = "GPU", "MMU", "JOB"; 996 997 upthreshold = <40>; 998 downdifferential = <10>; 999 1000 clocks = <&cru CLK_GPU>, <&cru CLK_GPU_BRG>; 1001 clock-names = "clk_gpu", "clk_gpu_brg"; 1002 power-domains = <&power RK3562_PD_GPU>; 1003 operating-points-v2 = <&gpu_opp_table>; 1004 #cooling-cells = <2>; 1005 1006 status = "disabled"; 1007 }; 1008 1009 gpu_opp_table: gpu-opp-table { 1010 compatible = "operating-points-v2"; 1011 1012 nvmem-cells = <&gpu_leakage>; 1013 nvmem-cell-names = "leakage"; 1014 1015 opp-300000000 { 1016 opp-hz = /bits/ 64 <300000000>; 1017 opp-microvolt = <900000 900000 1000000>; 1018 }; 1019 opp-400000000 { 1020 opp-hz = /bits/ 64 <400000000>; 1021 opp-microvolt = <900000 900000 1000000>; 1022 }; 1023 }; 1024 1025 rkvdec: rkvdec@ff340100 { 1026 compatible = "rockchip,rkv-decoder-vdpu382", "rockchip,rkv-decoder-v2"; 1027 reg = <0x0 0xff340100 0x0 0x400>, <0x0 0xff340000 0x0 0x100>; 1028 reg-names = "regs", "link"; 1029 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1030 interrupt-names = "irq_dec"; 1031 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_RKVDEC_HEVC_CA>; 1032 clock-names = "aclk_vcodec", "hclk_vcodec","clk_hevc_cabac"; 1033 rockchip,normal-rates = <198000000>, <0>, <396000000>; 1034 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_RKVDEC_HEVC_CA>; 1035 assigned-clock-rates = <198000000>, <396000000>; 1036 resets = <&cru SRST_A_RKVDEC>, <&cru SRST_H_RKVDEC>, 1037 <&cru SRST_RKVDEC_HEVC_CA>; 1038 reset-names = "video_a", "video_h", "video_hevc_cabac"; 1039 power-domains = <&power RK3562_PD_VDPU>; 1040 iommus = <&rkvdec_mmu>; 1041 rockchip,srv = <&mpp_srv>; 1042 rockchip,taskqueue-node = <0>; 1043 rockchip,resetgroup-node = <0>; 1044 rockchip,task-capacity = <16>; 1045 status = "disabled"; 1046 }; 1047 1048 rkvdec_mmu: iommu@ff340800 { 1049 compatible = "rockchip,iommu-v2"; 1050 reg = <0x0 0xff340800 0x0 0x40>, <0x0 0xff340900 0x0 0x40>; 1051 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1052 interrupt-names = "rkvdec_mmu"; 1053 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 1054 clock-names = "aclk", "iface"; 1055 power-domains = <&power RK3562_PD_VDPU>; 1056 #iommu-cells = <0>; 1057 status = "disabled"; 1058 }; 1059 1060 rkvenc: rkvenc@ff360000 { 1061 compatible = "rockchip,rkv-encoder-vepu540c", "rockchip,rkv-encoder-v2"; 1062 reg = <0x0 0xff360000 0x0 0x6000>; 1063 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1064 interrupt-names = "irq_rkvenc"; 1065 clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>, <&cru CLK_RKVENC_CORE>; 1066 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 1067 rockchip,normal-rates = <297000000>, <0>, <297000000>; 1068 resets = <&cru SRST_A_RKVENC>, <&cru SRST_H_RKVENC>, 1069 <&cru SRST_RKVENC_CORE>; 1070 reset-names = "video_a", "video_h", "video_core"; 1071 assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_RKVENC_CORE>; 1072 assigned-clock-rates = <297000000>, <297000000>; 1073 power-domains = <&power RK3562_PD_VEPU>; 1074 iommus = <&rkvenc_mmu>; 1075 rockchip,srv = <&mpp_srv>; 1076 rockchip,taskqueue-node = <1>; 1077 rockchip,resetgroup-node = <1>; 1078 status = "disabled"; 1079 }; 1080 1081 rkvenc_mmu: iommu@ff36f000 { 1082 compatible = "rockchip,iommu-v2"; 1083 reg = <0x0 0xff36f000 0x0 0x40>; 1084 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1085 interrupt-names = "rkvenc_mmu"; 1086 clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>; 1087 clock-names = "aclk", "iface"; 1088 power-domains = <&power RK3562_PD_VEPU>; 1089 #iommu-cells = <0>; 1090 status = "disabled"; 1091 }; 1092 1093 mipi0_csi2: mipi0-csi2@ff380000 { 1094 compatible = "rockchip,rk3562-mipi-csi2"; 1095 reg = <0x0 0xff380000 0x0 0x10000>; 1096 reg-names = "csihost_regs"; 1097 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1099 interrupt-names = "csi-intr1", "csi-intr2"; 1100 clocks = <&cru PCLK_CSIHOST0>; 1101 clock-names = "pclk_csi2host"; 1102 resets = <&cru SRST_P_CSIHOST0>; 1103 reset-names = "srst_csihost_p"; 1104 status = "disabled"; 1105 }; 1106 1107 mipi1_csi2: mipi1-csi2@ff390000 { 1108 compatible = "rockchip,rk3562-mipi-csi2"; 1109 reg = <0x0 0xff390000 0x0 0x10000>; 1110 reg-names = "csihost_regs"; 1111 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1113 interrupt-names = "csi-intr1", "csi-intr2"; 1114 clocks = <&cru PCLK_CSIHOST1>; 1115 clock-names = "pclk_csi2host"; 1116 resets = <&cru SRST_P_CSIHOST1>; 1117 reset-names = "srst_csihost_p"; 1118 status = "disabled"; 1119 }; 1120 1121 mipi2_csi2: mipi2-csi2@ff3a0000 { 1122 compatible = "rockchip,rk3562-mipi-csi2"; 1123 reg = <0x0 0xff3a0000 0x0 0x10000>; 1124 reg-names = "csihost_regs"; 1125 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1127 interrupt-names = "csi-intr1", "csi-intr2"; 1128 clocks = <&cru PCLK_CSIHOST2>; 1129 clock-names = "pclk_csi2host"; 1130 resets = <&cru SRST_P_CSIHOST2>; 1131 reset-names = "srst_csihost_p"; 1132 status = "disabled"; 1133 }; 1134 1135 mipi3_csi2: mipi3-csi2@ff3b0000 { 1136 compatible = "rockchip,rk3562-mipi-csi2"; 1137 reg = <0x0 0xff3b0000 0x0 0x10000>; 1138 reg-names = "csihost_regs"; 1139 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1140 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1141 interrupt-names = "csi-intr1", "csi-intr2"; 1142 clocks = <&cru PCLK_CSIHOST3>; 1143 clock-names = "pclk_csi2host"; 1144 resets = <&cru SRST_P_CSIHOST3>; 1145 reset-names = "srst_csihost_p"; 1146 status = "disabled"; 1147 }; 1148 1149 csi2_dphy0_hw: csi2-dphy0-hw@ff3c0000 { 1150 compatible = "rockchip,rk3562-csi2-dphy-hw"; 1151 reg = <0x0 0xff3c0000 0x0 0x10000>; 1152 clocks = <&cru PCLK_CSIPHY0>; 1153 clock-names = "pclk"; 1154 resets = <&cru SRST_P_CSIPHY0>; 1155 reset-names = "srst_p_csiphy0"; 1156 rockchip,grf = <&sys_grf>; 1157 status = "disabled"; 1158 }; 1159 1160 csi2_dphy1_hw: csi2-dphy1-hw@ff3d0000 { 1161 compatible = "rockchip,rk3562-csi2-dphy-hw"; 1162 reg = <0x0 0xff3d0000 0x0 0x10000>; 1163 clocks = <&cru PCLK_CSIPHY1>; 1164 clock-names = "pclk"; 1165 resets = <&cru SRST_P_CSIPHY1>; 1166 reset-names = "srst_p_csiphy1"; 1167 rockchip,grf = <&sys_grf>; 1168 status = "disabled"; 1169 }; 1170 1171 rkcif: rkcif@ff3e0000 { 1172 compatible = "rockchip,rk3562-cif"; 1173 reg = <0x0 0xff3e0000 0x0 0x800>; 1174 reg-names = "cif_regs"; 1175 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1176 interrupt-names = "cif-intr"; 1177 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, <&cru DCLK_VICAP>; 1178 clock-names = "aclk_cif", "hclk_cif", "dclk_cif"; 1179 resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, <&cru SRST_D_VICAP>, 1180 <&cru SRST_I0_VICAP>, <&cru SRST_I1_VICAP>, <&cru SRST_I2_VICAP>, 1181 <&cru SRST_I3_VICAP>; 1182 reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_d", 1183 "rst_cif_i0", "rst_cif_i1", "rst_cif_i2", 1184 "rst_cif_i3"; 1185 power-domains = <&power RK3562_PD_VI>; 1186 rockchip,grf = <&sys_grf>; 1187 iommus = <&rkcif_mmu>; 1188 status = "disabled"; 1189 }; 1190 1191 rkcif_mmu: iommu@ff3e0800 { 1192 compatible = "rockchip,iommu-v2"; 1193 reg = <0x0 0xff3e0800 0x0 0x100>; 1194 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1195 interrupt-names = "cif_mmu"; 1196 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>; 1197 clock-names = "aclk", "iface"; 1198 power-domains = <&power RK3562_PD_VI>; 1199 rockchip,disable-mmu-reset; 1200 #iommu-cells = <0>; 1201 status = "disabled"; 1202 }; 1203 1204 rkisp: isp@ff3f0000 { 1205 compatible = "rockchip,rk3562-rkisp"; 1206 reg = <0x0 0xff3f0000 0x0 0x7f00>; 1207 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1210 interrupt-names = "mipi_irq", "mi_irq", "isp_irq"; 1211 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru CLK_ISP>; 1212 clock-names = "aclk_isp", "hclk_isp", "clk_isp_core"; 1213 power-domains = <&power RK3562_PD_VI>; 1214 iommus = <&rkisp_mmu>; 1215 status = "disabled"; 1216 }; 1217 1218 rkisp_mmu: iommu@ff3f7f00 { 1219 compatible = "rockchip,iommu-v2"; 1220 reg = <0x0 0xff3f7f00 0x0 0x100>; 1221 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1222 interrupt-names = "isp_mmu"; 1223 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>; 1224 clock-names = "aclk", "iface"; 1225 rockchip,disable-mmu-reset; 1226 #iommu-cells = <0>; 1227 power-domains = <&power RK3562_PD_VI>; 1228 status = "disabled"; 1229 }; 1230 1231 vop: vop@ff400000 { 1232 compatible = "rockchip,rk3562-vop"; 1233 reg = <0x0 0xff400000 0x0 0x2000>, <0x0 0xff405000 0x0 0x1000>; 1234 reg-names = "regs", "gamma_lut"; 1235 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 1236 clocks = <&cru ACLK_VOP>, 1237 <&cru HCLK_VOP>, 1238 <&cru DCLK_VOP>, 1239 <&cru DCLK_VOP1>; 1240 clock-names = "aclk_vop", 1241 "hclk_vop", 1242 "dclk_vp0", 1243 "dclk_vp1"; 1244 resets = <&cru SRST_A_VOP>, 1245 <&cru SRST_H_VOP>, 1246 <&cru SRST_D_VOP>, 1247 <&cru SRST_D_VOP1>; 1248 reset-names = "axi", 1249 "ahb", 1250 "dclk_vp0", 1251 "dclk_vp1"; 1252 iommus = <&vop_mmu>; 1253 power-domains = <&power RK3562_PD_VO>; 1254 rockchip,grf = <&sys_grf>; 1255 status = "disabled"; 1256 1257 vop_out: ports { 1258 #address-cells = <1>; 1259 #size-cells = <0>; 1260 1261 port@0 { 1262 #address-cells = <1>; 1263 #size-cells = <0>; 1264 reg = <0>; 1265 1266 vp0_out_rgb: endpoint@0 { 1267 reg = <0>; 1268 remote-endpoint = <&rgb_in_vp0>; 1269 }; 1270 1271 vp0_out_dsi: endpoint@1 { 1272 reg = <1>; 1273 remote-endpoint = <&dsi_in_vp0>; 1274 }; 1275 1276 vp0_out_lvds: endpoint@2 { 1277 reg = <2>; 1278 remote-endpoint = <&lvds_in_vp0>; 1279 }; 1280 }; 1281 1282 port@1 { 1283 #address-cells = <1>; 1284 #size-cells = <0>; 1285 reg = <1>; 1286 1287 vp1_out_rgb: endpoint@0 { 1288 reg = <0>; 1289 remote-endpoint = <&rgb_in_vp1>; 1290 }; 1291 1292 vp1_out_dsi: endpoint@1 { 1293 reg = <1>; 1294 remote-endpoint = <&dsi_in_vp1>; 1295 }; 1296 1297 vp1_out_lvds: endpoint@2 { 1298 reg = <2>; 1299 remote-endpoint = <&lvds_in_vp1>; 1300 }; 1301 }; 1302 }; 1303 }; 1304 1305 vop_mmu: iommu@ff407e00 { 1306 compatible = "rockchip,iommu-v2"; 1307 reg = <0x0 0xff407e00 0x0 0x100>; 1308 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 1309 interrupt-names = "vop_mmu"; 1310 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 1311 clock-names = "aclk", "iface"; 1312 #iommu-cells = <0>; 1313 rockchip,disable-device-link-resume; 1314 rockchip,shootdown-entire; 1315 status = "disabled"; 1316 }; 1317 1318 rga2: rga@ff440000 { 1319 compatible = "rockchip,rga2_core0"; 1320 reg = <0x0 0xff440000 0x0 0x1000>; 1321 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1322 interrupt-names = "rga2_irq"; 1323 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>; 1324 clock-names = "aclk_rga2", "hclk_rga2", "clk_rga2"; 1325 iommus = <&rga2_mmu>; 1326 power-domains = <&power RK3562_PD_RGA>; 1327 status = "disabled"; 1328 }; 1329 1330 rga2_mmu: iommu@ff440f00 { 1331 compatible = "rockchip,iommu-v2"; 1332 reg = <0x0 0xff440f00 0x0 0x100>; 1333 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1334 interrupt-names = "rga2_mmu"; 1335 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>; 1336 clock-names = "aclk", "iface"; 1337 #iommu-cells = <0>; 1338 power-domains = <&power RK3562_PD_RGA>; 1339 status = "disabled"; 1340 }; 1341 1342 jpegd: jpegd@ff450000 { 1343 compatible = "rockchip,rkv-jpeg-decoder-v1"; 1344 reg = <0x0 0xff450000 0x0 0x400>; 1345 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1346 clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>; 1347 clock-names = "aclk_vcodec", "hclk_vcodec"; 1348 rockchip,disable-auto-freq; 1349 resets = <&cru SRST_A_JDEC>, <&cru SRST_H_JDEC>; 1350 reset-names = "video_a", "video_h"; 1351 power-domains = <&power RK3562_PD_RGA>; 1352 iommus = <&jpegd_mmu>; 1353 rockchip,srv = <&mpp_srv>; 1354 rockchip,taskqueue-node = <2>; 1355 rockchip,resetgroup-node = <2>; 1356 status = "disabled"; 1357 }; 1358 1359 jpegd_mmu: iommu@ff450480 { 1360 compatible = "rockchip,iommu-v2"; 1361 reg = <0x0 0xff450480 0x0 0x40>; 1362 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1363 interrupt-names = "jpegd_mmu"; 1364 clock-names = "aclk", "iface"; 1365 clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>; 1366 power-domains = <&power RK3562_PD_RGA>; 1367 #iommu-cells = <0>; 1368 status = "disabled"; 1369 }; 1370 1371 pcie2x1: pcie@ff500000 { 1372 compatible = "rockchip,rk3562-pcie", "snps,dw-pcie"; 1373 #address-cells = <3>; 1374 #size-cells = <2>; 1375 bus-range = <0x0 0xff>; 1376 clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, 1377 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, 1378 <&cru CLK_PCIE20_AUX>; 1379 clock-names = "aclk_mst", "aclk_slv", 1380 "aclk_dbi", "pclk", "aux"; 1381 device_type = "pci"; 1382 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1384 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1385 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1386 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1387 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1388 interrupt-names = "msi", "pmc", "sys", "legacy", "msg", "err"; 1389 #interrupt-cells = <1>; 1390 interrupt-map-mask = <0 0 0 7>; 1391 interrupt-map = <0 0 0 1 &pcie2x1_intc 0>, 1392 <0 0 0 2 &pcie2x1_intc 1>, 1393 <0 0 0 3 &pcie2x1_intc 2>, 1394 <0 0 0 4 &pcie2x1_intc 3>; 1395 linux,pci-domain = <0>; 1396 num-ib-windows = <8>; 1397 num-viewport = <8>; 1398 num-ob-windows = <2>; 1399 max-link-speed = <2>; 1400 num-lanes = <1>; 1401 phys = <&combphy_pu PHY_TYPE_PCIE>; 1402 phy-names = "pcie-phy"; 1403 ranges = <0x00000800 0x0 0xfc000000 0x0 0xfc000000 0x0 0x100000 1404 0x81000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000 1405 0x82000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000 1406 0xc3000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>; 1407 reg = <0x0 0xfe000000 0x0 0x400000>, 1408 <0x0 0xff500000 0x0 0x10000>; 1409 reg-names = "pcie-dbi", "pcie-apb"; 1410 resets = <&cru SRST_PCIE20_POWERUP>; 1411 reset-names = "pipe"; 1412 status = "disabled"; 1413 1414 pcie2x1_intc: legacy-interrupt-controller { 1415 interrupt-controller; 1416 #address-cells = <0>; 1417 #interrupt-cells = <1>; 1418 interrupt-parent = <&gic>; 1419 }; 1420 }; 1421 1422 spi1: spi@ff640000 { 1423 compatible = "rockchip,rk3066-spi"; 1424 reg = <0x0 0xff640000 0x0 0x1000>; 1425 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1426 #address-cells = <1>; 1427 #size-cells = <0>; 1428 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 1429 clock-names = "spiclk", "apb_pclk"; 1430 dmas = <&dmac 15>, <&dmac 14>; 1431 dma-names = "tx", "rx"; 1432 pinctrl-names = "default"; 1433 pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>; 1434 num-cs = <2>; 1435 status = "disabled"; 1436 }; 1437 1438 spi2: spi@ff650000 { 1439 compatible = "rockchip,rk3066-spi"; 1440 reg = <0x0 0xff650000 0x0 0x1000>; 1441 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1442 #address-cells = <1>; 1443 #size-cells = <0>; 1444 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 1445 clock-names = "spiclk", "apb_pclk"; 1446 dmas = <&dmac 17>, <&dmac 16>; 1447 dma-names = "tx", "rx"; 1448 pinctrl-names = "default"; 1449 pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>; 1450 num-cs = <2>; 1451 status = "disabled"; 1452 }; 1453 1454 uart1: serial@ff670000 { 1455 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 1456 reg = <0x0 0xff670000 0x0 0x100>; 1457 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1458 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1459 clock-names = "baudclk", "apb_pclk"; 1460 reg-shift = <2>; 1461 reg-io-width = <4>; 1462 dmas = <&dmac 1>, <&dmac 10>; 1463 status = "disabled"; 1464 }; 1465 1466 uart2: serial@ff680000 { 1467 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 1468 reg = <0x0 0xff680000 0x0 0x100>; 1469 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1470 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1471 clock-names = "baudclk", "apb_pclk"; 1472 reg-shift = <2>; 1473 reg-io-width = <4>; 1474 dmas = <&dmac 2>; 1475 status = "disabled"; 1476 }; 1477 1478 uart3: serial@ff690000 { 1479 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 1480 reg = <0x0 0xff690000 0x0 0x100>; 1481 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1482 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1483 clock-names = "baudclk", "apb_pclk"; 1484 reg-shift = <2>; 1485 reg-io-width = <4>; 1486 dmas = <&dmac 3>; 1487 status = "disabled"; 1488 }; 1489 1490 uart4: serial@ff6a0000 { 1491 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 1492 reg = <0x0 0xff6a0000 0x0 0x100>; 1493 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1494 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1495 clock-names = "baudclk", "apb_pclk"; 1496 reg-shift = <2>; 1497 reg-io-width = <4>; 1498 dmas = <&dmac 4>; 1499 status = "disabled"; 1500 }; 1501 1502 uart5: serial@ff6b0000 { 1503 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 1504 reg = <0x0 0xff6b0000 0x0 0x100>; 1505 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1506 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1507 clock-names = "baudclk", "apb_pclk"; 1508 reg-shift = <2>; 1509 reg-io-width = <4>; 1510 dmas = <&dmac 5>, <&dmac 11>; 1511 status = "disabled"; 1512 }; 1513 1514 uart6: serial@ff6c0000 { 1515 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 1516 reg = <0x0 0xff6c0000 0x0 0x100>; 1517 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1518 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 1519 clock-names = "baudclk", "apb_pclk"; 1520 reg-shift = <2>; 1521 reg-io-width = <4>; 1522 dmas = <&dmac 6>; 1523 status = "disabled"; 1524 }; 1525 1526 uart7: serial@ff6d0000 { 1527 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 1528 reg = <0x0 0xff6d0000 0x0 0x100>; 1529 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1530 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 1531 clock-names = "baudclk", "apb_pclk"; 1532 reg-shift = <2>; 1533 reg-io-width = <4>; 1534 dmas = <&dmac 7>; 1535 status = "disabled"; 1536 }; 1537 1538 uart8: serial@ff6e0000 { 1539 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 1540 reg = <0x0 0xff6e0000 0x0 0x100>; 1541 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1542 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 1543 clock-names = "baudclk", "apb_pclk"; 1544 reg-shift = <2>; 1545 reg-io-width = <4>; 1546 dmas = <&dmac 8>; 1547 status = "disabled"; 1548 }; 1549 1550 uart9: serial@ff6f0000 { 1551 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 1552 reg = <0x0 0xff6f0000 0x0 0x100>; 1553 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1554 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 1555 clock-names = "baudclk", "apb_pclk"; 1556 reg-shift = <2>; 1557 reg-io-width = <4>; 1558 dmas = <&dmac 9>; 1559 status = "disabled"; 1560 }; 1561 1562 pwm4: pwm@ff700000 { 1563 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 1564 reg = <0x0 0xff700000 0x0 0x10>; 1565 #pwm-cells = <3>; 1566 pinctrl-names = "active"; 1567 pinctrl-0 = <&pwm4m0_pins>; 1568 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; 1569 clock-names = "pwm", "pclk"; 1570 status = "disabled"; 1571 }; 1572 1573 pwm5: pwm@ff700010 { 1574 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 1575 reg = <0x0 0xff700010 0x0 0x10>; 1576 #pwm-cells = <3>; 1577 pinctrl-names = "active"; 1578 pinctrl-0 = <&pwm5m0_pins>; 1579 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; 1580 clock-names = "pwm", "pclk"; 1581 status = "disabled"; 1582 }; 1583 1584 pwm6: pwm@ff700020 { 1585 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 1586 reg = <0x0 0xff700020 0x0 0x10>; 1587 #pwm-cells = <3>; 1588 pinctrl-names = "active"; 1589 pinctrl-0 = <&pwm6m0_pins>; 1590 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; 1591 clock-names = "pwm", "pclk"; 1592 status = "disabled"; 1593 }; 1594 1595 pwm7: pwm@ff700030 { 1596 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 1597 reg = <0x0 0xff700030 0x0 0x10>; 1598 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1600 #pwm-cells = <3>; 1601 pinctrl-names = "active"; 1602 pinctrl-0 = <&pwm7m0_pins>; 1603 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; 1604 clock-names = "pwm", "pclk"; 1605 status = "disabled"; 1606 }; 1607 1608 pwm8: pwm@ff710000 { 1609 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 1610 reg = <0x0 0xff710000 0x0 0x10>; 1611 #pwm-cells = <3>; 1612 pinctrl-names = "active"; 1613 pinctrl-0 = <&pwm8m0_pins>; 1614 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; 1615 clock-names = "pwm", "pclk"; 1616 status = "disabled"; 1617 }; 1618 1619 pwm9: pwm@ff710010 { 1620 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 1621 reg = <0x0 0xff710010 0x0 0x10>; 1622 #pwm-cells = <3>; 1623 pinctrl-names = "active"; 1624 pinctrl-0 = <&pwm9m0_pins>; 1625 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; 1626 clock-names = "pwm", "pclk"; 1627 status = "disabled"; 1628 }; 1629 1630 pwm10: pwm@ff710020 { 1631 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 1632 reg = <0x0 0xff710020 0x0 0x10>; 1633 #pwm-cells = <3>; 1634 pinctrl-names = "active"; 1635 pinctrl-0 = <&pwm10m0_pins>; 1636 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; 1637 clock-names = "pwm", "pclk"; 1638 status = "disabled"; 1639 }; 1640 1641 pwm11: pwm@ff710030 { 1642 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 1643 reg = <0x0 0xff710030 0x0 0x10>; 1644 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1646 #pwm-cells = <3>; 1647 pinctrl-names = "active"; 1648 pinctrl-0 = <&pwm11m0_pins>; 1649 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; 1650 clock-names = "pwm", "pclk"; 1651 status = "disabled"; 1652 }; 1653 1654 pwm12: pwm@ff720000 { 1655 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 1656 reg = <0x0 0xff720000 0x0 0x10>; 1657 #pwm-cells = <3>; 1658 pinctrl-names = "active"; 1659 pinctrl-0 = <&pwm12m0_pins>; 1660 clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; 1661 clock-names = "pwm", "pclk"; 1662 status = "disabled"; 1663 }; 1664 1665 pwm13: pwm@ff720010 { 1666 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 1667 reg = <0x0 0xff720010 0x0 0x10>; 1668 #pwm-cells = <3>; 1669 pinctrl-names = "active"; 1670 pinctrl-0 = <&pwm13m0_pins>; 1671 clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; 1672 clock-names = "pwm", "pclk"; 1673 status = "disabled"; 1674 }; 1675 1676 pwm14: pwm@ff720020 { 1677 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 1678 reg = <0x0 0xff720020 0x0 0x10>; 1679 #pwm-cells = <3>; 1680 pinctrl-names = "active"; 1681 pinctrl-0 = <&pwm14m0_pins>; 1682 clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; 1683 clock-names = "pwm", "pclk"; 1684 status = "disabled"; 1685 }; 1686 1687 pwm15: pwm@ff720030 { 1688 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 1689 reg = <0x0 0xff720030 0x0 0x10>; 1690 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1691 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1692 #pwm-cells = <3>; 1693 pinctrl-names = "active"; 1694 pinctrl-0 = <&pwm15m0_pins>; 1695 clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; 1696 clock-names = "pwm", "pclk"; 1697 status = "disabled"; 1698 }; 1699 1700 saradc0: saradc@ff730000 { 1701 compatible = "rockchip,rk3562-saradc"; 1702 reg = <0x0 0xff730000 0x0 0x100>; 1703 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1704 #io-channel-cells = <1>; 1705 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 1706 clock-names = "saradc", "apb_pclk"; 1707 resets = <&cru SRST_P_SARADC>; 1708 reset-names = "saradc-apb"; 1709 status = "disabled"; 1710 }; 1711 1712 u2phy: usb2-phy@ff740000 { 1713 compatible = "rockchip,rk3562-usb2phy"; 1714 reg = <0x0 0xff740000 0x0 0x10000>; 1715 clocks = <&cru CLK_USB2PHY_REF>, <&cru PCLK_USB2PHY>; 1716 clock-names = "phyclk", "pclk"; 1717 #clock-cells = <0>; 1718 clock-output-names = "usb480m_phy"; 1719 rockchip,usbgrf = <&usbphy_grf>; 1720 status = "disabled"; 1721 1722 u2phy_otg: otg-port { 1723 #phy-cells = <0>; 1724 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 1725 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 1726 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1727 interrupt-names = "otg-bvalid", "otg-id", "linestate"; 1728 status = "disabled"; 1729 }; 1730 1731 u2phy_host: host-port { 1732 #phy-cells = <0>; 1733 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1734 interrupt-names = "linestate"; 1735 status = "disabled"; 1736 }; 1737 }; 1738 1739 combphy_pu: phy@ff750000 { 1740 compatible = "rockchip,rk3562-naneng-combphy"; 1741 reg = <0x0 0xff750000 0x0 0x100>; 1742 #phy-cells = <1>; 1743 clocks = <&cru CLK_PIPEPHY_REF>, <&cru PCLK_PIPEPHY>, 1744 <&cru PCLK_PHP>; 1745 clock-names = "refclk", "apbclk", "pipe_clk"; 1746 assigned-clocks = <&cru CLK_PIPEPHY_REF>; 1747 assigned-clock-rates = <100000000>; 1748 resets = <&cru SRST_P_PIPEPHY>, <&cru SRST_PIPEPHY>; 1749 reset-names = "combphy-apb", "combphy"; 1750 rockchip,pipe-grf = <&peri_grf>; 1751 rockchip,pipe-phy-grf = <&pipephy_grf>; 1752 status = "disabled"; 1753 }; 1754 1755 sai0: sai@ff800000 { 1756 compatible = "rockchip,rk3562-sai", "rockchip,sai-v1"; 1757 reg = <0x0 0xff800000 0x0 0x1000>; 1758 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1759 clocks = <&cru MCLK_SAI0>, <&cru HCLK_SAI0>; 1760 clock-names = "mclk", "hclk"; 1761 dmas = <&dmac 19>, <&dmac 18>; 1762 dma-names = "tx", "rx"; 1763 resets = <&cru SRST_M_SAI0_8CH>, <&cru SRST_H_SAI0_8CH>; 1764 reset-names = "m", "h"; 1765 pinctrl-names = "default"; 1766 pinctrl-0 = <&i2s0m0_lrck 1767 &i2s0m0_sclk 1768 &i2s0m0_sdi0 1769 &i2s0m0_sdo0 1770 &i2s0m0_sdo1 1771 &i2s0m0_sdo2 1772 &i2s0m0_sdo3>; 1773 #sound-dai-cells = <0>; 1774 status = "disabled"; 1775 }; 1776 1777 sai1: sai@ff810000 { 1778 compatible = "rockchip,rk3562-sai", "rockchip,sai-v1"; 1779 reg = <0x0 0xff810000 0x0 0x1000>; 1780 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1781 clocks = <&cru MCLK_SAI1>, <&cru HCLK_SAI1>; 1782 clock-names = "mclk", "hclk"; 1783 dmas = <&dmac 21>, <&dmac 20>; 1784 dma-names = "tx", "rx"; 1785 resets = <&cru SRST_M_SAI1_8CH>, <&cru SRST_H_SAI1_8CH>; 1786 reset-names = "m", "h"; 1787 pinctrl-names = "default"; 1788 pinctrl-0 = <&i2s1m0_lrck 1789 &i2s1m0_sclk 1790 &i2s1m0_sdi0 1791 &i2s1m0_sdi1 1792 &i2s1m0_sdi2 1793 &i2s1m0_sdi3 1794 &i2s1m0_sdo0 1795 &i2s1m0_sdo1 1796 &i2s1m0_sdo2 1797 &i2s1m0_sdo3>; 1798 #sound-dai-cells = <0>; 1799 status = "disabled"; 1800 }; 1801 1802 sai2: sai@ff820000 { 1803 compatible = "rockchip,rk3562-sai", "rockchip,sai-v1"; 1804 reg = <0x0 0xff820000 0x0 0x1000>; 1805 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1806 clocks = <&cru MCLK_SAI2>, <&cru HCLK_SAI2>; 1807 clock-names = "mclk", "hclk"; 1808 dmas = <&dmac 23>, <&dmac 22>; 1809 dma-names = "tx", "rx"; 1810 resets = <&cru SRST_M_SAI2_2CH>, <&cru SRST_H_SAI2_2CH>; 1811 reset-names = "m", "h"; 1812 pinctrl-names = "default"; 1813 pinctrl-0 = <&i2s2m0_lrck 1814 &i2s2m0_sclk 1815 &i2s2m0_sdi 1816 &i2s2m0_sdo>; 1817 #sound-dai-cells = <0>; 1818 status = "disabled"; 1819 }; 1820 1821 pdm: pdm@ff830000 { 1822 compatible = "rockchip,rk3562-pdm", "rockchip,pdm"; 1823 reg = <0x0 0xff830000 0x0 0x1000>; 1824 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; 1825 clock-names = "pdm_clk", "pdm_hclk"; 1826 dmas = <&dmac 31>; 1827 dma-names = "rx"; 1828 pinctrl-names = "default"; 1829 pinctrl-0 = <&pdmm0_clk0 1830 &pdmm0_clk1 1831 &pdmm0_sdi0 1832 &pdmm0_sdi1 1833 &pdmm0_sdi2 1834 &pdmm0_sdi3>; 1835 #sound-dai-cells = <0>; 1836 status = "disabled"; 1837 }; 1838 1839 spdif_8ch: spdif@ff840000 { 1840 compatible = "rockchip,rk3562-spdif", "rockchip,rk3568-spdif"; 1841 reg = <0x0 0xff840000 0x0 0x1000>; 1842 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1843 dmas = <&dmac 30>; 1844 dma-names = "tx"; 1845 clock-names = "mclk", "hclk"; 1846 clocks = <&cru MCLK_SPDIF>, <&cru HCLK_SPDIF>; 1847 #sound-dai-cells = <0>; 1848 pinctrl-names = "default"; 1849 pinctrl-0 = <&spdifm0_pins>; 1850 status = "disabled"; 1851 }; 1852 1853 acdcdig_dsm: codec-digital@ff850000 { 1854 compatible = "rockchip,rk3562-codec-digital", "rockchip,codec-digital-v1"; 1855 reg = <0x0 0xff850000 0x0 0x1000>; 1856 clocks = <&cru CLK_DSM>, <&cru HCLK_DSM>; 1857 clock-names = "dac", "pclk"; 1858 resets = <&cru SRST_DSM>; 1859 reset-names = "reset" ; 1860 rockchip,grf = <&sys_grf>; 1861 rockchip,pwm-output-mode; 1862 pinctrl-names = "default"; 1863 pinctrl-0 = <&dsm_pins>; 1864 #sound-dai-cells = <0>; 1865 status = "disabled"; 1866 }; 1867 1868 sfc: spi@ff860000 { 1869 compatible = "rockchip,sfc"; 1870 reg = <0x0 0xff860000 0x0 0x10000>; 1871 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 1872 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1873 clock-names = "clk_sfc", "hclk_sfc"; 1874 assigned-clocks = <&cru SCLK_SFC>; 1875 assigned-clock-rates = <100000000>; 1876 #address-cells = <1>; 1877 #size-cells = <0>; 1878 status = "disabled"; 1879 }; 1880 1881 sdhci: mmc@ff870000 { 1882 compatible = "rockchip,rk3562-dwcmshc", "rockchip,rk3528-dwcmshc"; 1883 reg = <0x0 0xff870000 0x0 0x10000>; 1884 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1885 assigned-clocks = <&cru BCLK_EMMC>, <&cru CCLK_EMMC>; 1886 assigned-clock-rates = <200000000>, <200000000>; 1887 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 1888 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1889 <&cru TMCLK_EMMC>; 1890 clock-names = "core", "bus", "axi", "block", "timer"; 1891 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 1892 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 1893 <&cru SRST_T_EMMC>; 1894 reset-names = "core", "bus", "axi", "block", "timer"; 1895 max-frequency = <200000000>; 1896 status = "disabled"; 1897 }; 1898 1899 sdmmc0: mmc@ff880000 { 1900 compatible = "rockchip,rk3562-dw-mshc", 1901 "rockchip,rk3288-dw-mshc"; 1902 reg = <0x0 0xff880000 0x0 0x10000>; 1903 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1904 max-frequency = <150000000>; 1905 clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SDMMC0>, 1906 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; 1907 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1908 resets = <&cru SRST_H_SDMMC0>; 1909 reset-names = "reset"; 1910 fifo-depth = <0x100>; 1911 status = "disabled"; 1912 }; 1913 1914 sdmmc1: mmc@ff890000 { 1915 compatible = "rockchip,rk3562-dw-mshc", 1916 "rockchip,rk3288-dw-mshc"; 1917 reg = <0x0 0xff890000 0x0 0x10000>; 1918 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1919 max-frequency = <150000000>; 1920 clocks = <&cru HCLK_SDMMC1>, <&cru CCLK_SDMMC1>, 1921 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; 1922 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1923 resets = <&cru SRST_H_SDMMC1>; 1924 reset-names = "reset"; 1925 fifo-depth = <0x100>; 1926 status = "disabled"; 1927 }; 1928 1929 crypto: crypto@ff8a0000 { 1930 compatible = "rockchip,crypto-v4"; 1931 reg = <0x0 0xff8a0000 0x0 0x2000>; 1932 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1933 clocks = <&scmi_clk CLK_CORE_CRYPTO>, <&scmi_clk CLK_PKA_CRYPTO>, 1934 <&scmi_clk ACLK_CRYPTO>, <&scmi_clk HCLK_CRYPTO>, 1935 <&scmi_clk PCLK_CRYPTO>; 1936 clock-names = "sclk", "pka", "aclk", "pclk", "pclk"; 1937 assigned-clocks = <&scmi_clk CLK_CORE_CRYPTO>, <&scmi_clk CLK_PKA_CRYPTO>; 1938 assigned-clock-rates = <200000000>, <300000000>; 1939 resets = <&cru SRST_CORE_CRYPTO>; 1940 reset-names = "crypto-rst"; 1941 status = "disabled"; 1942 }; 1943 1944 rng: rng@ff8e0000 { 1945 compatible = "rockchip,rkrng"; 1946 reg = <0x0 0xff8e0000 0x0 0x200>; 1947 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1948 clocks = <&scmi_clk HCLK_RK_RNG_NS>; 1949 clock-names = "hclk_trng"; 1950 resets = <&cru SRST_H_RK_RNG_NS>; 1951 reset-names = "reset"; 1952 status = "disabled"; 1953 }; 1954 1955 otp: otp@ff930000 { 1956 compatible = "rockchip,rk3562-otp"; 1957 reg = <0x0 0xff930000 0x0 0x4000>; 1958 #address-cells = <1>; 1959 #size-cells = <1>; 1960 clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>, 1961 <&cru PCLK_OTPC_NS>, <&cru CLK_OTPC_ARB>, 1962 <&cru PCLK_OTPPHY>; 1963 clock-names = "usr", "sbpi", "apb", "arb", "phy"; 1964 resets = <&cru SRST_USER_OTPC_NS>, <&cru SRST_SBPI_OTPC_NS>, 1965 <&cru SRST_P_OTPC_NS>, <&cru SRST_OTPC_ARB>, 1966 <&cru SRST_P_OTPPHY>; 1967 reset-names = "usr", "sbpi", "apb", "arb", "phy"; 1968 1969 /* Data cells */ 1970 cpu_code: cpu-code@2 { 1971 reg = <0x02 0x2>; 1972 }; 1973 otp_cpu_version: cpu-version@8 { 1974 reg = <0x08 0x1>; 1975 bits = <3 3>; 1976 }; 1977 otp_id: id@a { 1978 reg = <0x0a 0x10>; 1979 }; 1980 cpu_leakage: cpu-leakage@1a { 1981 reg = <0x1a 0x1>; 1982 }; 1983 log_leakage: log-leakage@1b { 1984 reg = <0x1b 0x1>; 1985 }; 1986 npu_leakage: npu-leakage@1c { 1987 reg = <0x1c 0x1>; 1988 }; 1989 gpu_leakage: gpu-leakage@1d { 1990 reg = <0x1d 0x1>; 1991 }; 1992 }; 1993 1994 dmac: dma-controller@ff990000 { 1995 compatible = "arm,pl330", "arm,primecell"; 1996 reg = <0x0 0xff990000 0x0 0x4000>; 1997 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1998 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 1999 clocks = <&cru ACLK_DMAC>; 2000 clock-names = "apb_pclk"; 2001 #dma-cells = <1>; 2002 arm,pl330-periph-burst; 2003 }; 2004 2005 hwlock: hwspinlock@ff9e0000 { 2006 compatible = "rockchip,hwspinlock"; 2007 reg = <0x0 0xff9e0000 0x0 0x100>; 2008 #hwlock-cells = <1>; 2009 status = "disabled"; 2010 }; 2011 2012 i2c1: i2c@ffa00000 { 2013 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; 2014 reg = <0x0 0xffa00000 0x0 0x1000>; 2015 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 2016 clock-names = "i2c", "pclk"; 2017 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2018 pinctrl-names = "default"; 2019 pinctrl-0 = <&i2c1m0_xfer>; 2020 #address-cells = <1>; 2021 #size-cells = <0>; 2022 status = "disabled"; 2023 }; 2024 2025 i2c2: i2c@ffa10000 { 2026 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; 2027 reg = <0x0 0xffa10000 0x0 0x1000>; 2028 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 2029 clock-names = "i2c", "pclk"; 2030 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2031 pinctrl-names = "default"; 2032 pinctrl-0 = <&i2c2m0_xfer>; 2033 #address-cells = <1>; 2034 #size-cells = <0>; 2035 status = "disabled"; 2036 }; 2037 2038 i2c3: i2c@ffa20000 { 2039 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; 2040 reg = <0x0 0xffa20000 0x0 0x1000>; 2041 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 2042 clock-names = "i2c", "pclk"; 2043 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 2044 pinctrl-names = "default"; 2045 pinctrl-0 = <&i2c3m0_xfer>; 2046 #address-cells = <1>; 2047 #size-cells = <0>; 2048 status = "disabled"; 2049 }; 2050 2051 i2c4: i2c@ffa30000 { 2052 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; 2053 reg = <0x0 0xffa30000 0x0 0x1000>; 2054 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 2055 clock-names = "i2c", "pclk"; 2056 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 2057 pinctrl-names = "default"; 2058 pinctrl-0 = <&i2c4m0_xfer>; 2059 #address-cells = <1>; 2060 #size-cells = <0>; 2061 status = "disabled"; 2062 }; 2063 2064 i2c5: i2c@ffa40000 { 2065 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; 2066 reg = <0x0 0xffa40000 0x0 0x1000>; 2067 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 2068 clock-names = "i2c", "pclk"; 2069 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 2070 pinctrl-names = "default"; 2071 pinctrl-0 = <&i2c5m0_xfer>; 2072 #address-cells = <1>; 2073 #size-cells = <0>; 2074 status = "disabled"; 2075 }; 2076 2077 wdt: watchdog@ffa60000 { 2078 compatible = "snps,dw-wdt"; 2079 reg = <0x0 0xffa60000 0x0 0x100>; 2080 clocks = <&cru CLK_WDTNS>, <&cru PCLK_WDTNS>; 2081 clock-names = "tclk", "pclk"; 2082 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2083 status = "disabled"; 2084 }; 2085 2086 tsadc: tsadc@ffa70000 { 2087 compatible = "rockchip,rk3562-tsadc"; 2088 reg = <0x0 0xffa70000 0x0 0x400>; 2089 rockchip,grf = <&sys_grf>; 2090 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2091 clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>, <&cru PCLK_TSADC>; 2092 clock-names = "tsadc", "tsadc_tsen", "apb_pclk"; 2093 assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>; 2094 assigned-clock-rates = <1200000>, <12000000>; 2095 resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>, <&cru SRST_TSADCPHY>; 2096 reset-names = "tsadc", "tsadc-apb", "tsadc-phy"; 2097 #thermal-sensor-cells = <1>; 2098 rockchip,hw-tshut-temp = <120000>; 2099 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 2100 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 2101 status = "disabled"; 2102 }; 2103 2104 gmac0: ethernet@ffa80000 { 2105 compatible = "rockchip,rk3562-gmac", "snps,dwmac-4.20a"; 2106 reg = <0x0 0xffa80000 0x0 0x10000>; 2107 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 2108 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 2109 interrupt-names = "macirq", "eth_wake_irq"; 2110 rockchip,grf = <&sys_grf>; 2111 rockchip,php_grf = <&ioc_grf>; 2112 clocks = <&cru CLK_GMAC_125M_CRU_I>, <&cru CLK_GMAC_50M_CRU_I>, 2113 <&cru PCLK_GMAC>, <&cru ACLK_GMAC>; 2114 clock-names = "stmmaceth", "clk_mac_ref", 2115 "pclk_mac", "aclk_mac"; 2116 resets = <&cru SRST_A_GMAC>; 2117 reset-names = "stmmaceth"; 2118 2119 snps,mixed-burst; 2120 snps,tso; 2121 2122 snps,axi-config = <&gmac0_stmmac_axi_setup>; 2123 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 2124 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 2125 status = "disabled"; 2126 2127 mdio0: mdio { 2128 compatible = "snps,dwmac-mdio"; 2129 #address-cells = <0x1>; 2130 #size-cells = <0x0>; 2131 }; 2132 2133 gmac0_stmmac_axi_setup: stmmac-axi-config { 2134 snps,wr_osr_lmt = <4>; 2135 snps,rd_osr_lmt = <8>; 2136 snps,blen = <0 0 0 0 16 8 4>; 2137 }; 2138 2139 gmac0_mtl_rx_setup: rx-queues-config { 2140 snps,rx-queues-to-use = <1>; 2141 queue0 {}; 2142 }; 2143 2144 gmac0_mtl_tx_setup: tx-queues-config { 2145 snps,tx-queues-to-use = <1>; 2146 queue0 {}; 2147 }; 2148 }; 2149 2150 saradc1: saradc@ffaa0000 { 2151 compatible = "rockchip,rk3562-saradc"; 2152 reg = <0x0 0xffaa0000 0x0 0x100>; 2153 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 2154 #io-channel-cells = <1>; 2155 clocks = <&cru CLK_SARADC_VCCIO156>, <&cru PCLK_SARADC_VCCIO156>; 2156 clock-names = "saradc", "apb_pclk"; 2157 resets = <&cru SRST_P_SARADC_VCCIO156>; 2158 reset-names = "saradc-apb"; 2159 status = "disabled"; 2160 }; 2161 2162 mailbox: mailbox@ffae0000 { 2163 compatible = "rockchip,rk3562-mailbox", 2164 "rockchip,rk3368-mailbox"; 2165 reg = <0x0 0xffae0000 0x0 0x200>; 2166 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 2167 clocks = <&cru PCLK_MAILBOX>; 2168 clock-names = "pclk_mailbox"; 2169 #mbox-cells = <1>; 2170 status = "disabled"; 2171 }; 2172 2173 dsi: dsi@ffb10000 { 2174 compatible = "rockchip,rk3562-mipi-dsi"; 2175 reg = <0x0 0xffb10000 0x0 0x10000>; 2176 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 2177 clocks = <&cru PCLK_DSITX>; 2178 clock-names = "pclk"; 2179 resets = <&cru SRST_P_DSITX>; 2180 reset-names = "apb"; 2181 phys = <&video_phy>; 2182 phy-names = "dphy"; 2183 rockchip,grf = <&sys_grf>; 2184 #address-cells = <1>; 2185 #size-cells = <0>; 2186 status = "disabled"; 2187 2188 ports { 2189 #address-cells = <1>; 2190 #size-cells = <0>; 2191 2192 dsi_in: port@0 { 2193 reg = <0>; 2194 #address-cells = <1>; 2195 #size-cells = <0>; 2196 2197 dsi_in_vp0: endpoint@0 { 2198 reg = <0>; 2199 remote-endpoint = <&vp0_out_dsi>; 2200 status = "disabled"; 2201 }; 2202 2203 dsi_in_vp1: endpoint@1 { 2204 reg = <1>; 2205 remote-endpoint = <&vp1_out_dsi>; 2206 status = "disabled"; 2207 }; 2208 }; 2209 }; 2210 }; 2211 2212 video_phy: phy@ffb20000 { 2213 compatible = "rockchip,rk3562-dsi-dphy", "rockchip,rk3562-video-phy", 2214 "rockchip,rk3568-dsi-dphy", "rockchip,rk3568-video-phy"; 2215 reg = <0x0 0xffb20000 0x0 0x10000>, 2216 <0x0 0xffb10000 0x0 0x10000>; 2217 reg-names = "phy", "host"; 2218 clocks = <&cru CLK_MIPIDSIPHY_REF>, 2219 <&cru PCLK_DSIPHY>, <&cru PCLK_DSITX>; 2220 clock-names = "ref", "pclk", "pclk_host"; 2221 #clock-cells = <0>; 2222 resets = <&cru SRST_P_DSIPHY>; 2223 reset-names = "apb"; 2224 #phy-cells = <0>; 2225 status = "disabled"; 2226 }; 2227 2228 gmac1: ethernet@ffb30000 { 2229 compatible = "rockchip,rk3562-gmac"; 2230 reg = <0x0 0xffb30000 0x0 0x10000>; 2231 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 2232 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 2233 interrupt-names = "macirq", "eth_wake_irq"; 2234 rockchip,grf = <&sys_grf>; 2235 rockchip,php_grf = <&ioc_grf>; 2236 clocks = <&cru CLK_GMAC_50M_CRU_I>, <&cru CLK_GMAC_50M_CRU_I>, 2237 <&cru PCLK_GMAC>, <&cru ACLK_GMAC>; 2238 clock-names = "stmmaceth", "clk_mac_ref", 2239 "pclk_mac", "aclk_mac"; 2240 resets = <&cru SRST_A_MAC100>; 2241 reset-names = "stmmaceth"; 2242 status = "disabled"; 2243 2244 mdio1: mdio { 2245 compatible = "snps,dwmac-mdio"; 2246 #address-cells = <0x1>; 2247 #size-cells = <0x0>; 2248 }; 2249 }; 2250 2251 pinctrl: pinctrl { 2252 compatible = "rockchip,rk3562-pinctrl"; 2253 rockchip,grf = <&ioc_grf>; 2254 #address-cells = <2>; 2255 #size-cells = <2>; 2256 ranges; 2257 2258 gpio0: gpio@ff260000 { 2259 compatible = "rockchip,gpio-bank"; 2260 reg = <0x0 0xff260000 0x0 0x100>; 2261 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 2262 clocks = <&cru PCLK_PMU0_GPIO0>, <&cru DBCLK_PMU0_GPIO0>; 2263 2264 gpio-controller; 2265 #gpio-cells = <2>; 2266 gpio-ranges = <&pinctrl 0 0 32>; 2267 interrupt-controller; 2268 #interrupt-cells = <2>; 2269 }; 2270 2271 gpio1: gpio@ff620000 { 2272 compatible = "rockchip,gpio-bank"; 2273 reg = <0x0 0xff620000 0x0 0x100>; 2274 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 2275 clocks = <&cru PCLK_PERI_GPIO1>, <&cru DCLK_PERI_GPIO1>; 2276 2277 gpio-controller; 2278 #gpio-cells = <2>; 2279 gpio-ranges = <&pinctrl 0 32 32>; 2280 interrupt-controller; 2281 #interrupt-cells = <2>; 2282 }; 2283 2284 gpio2: gpio@ff630000 { 2285 compatible = "rockchip,gpio-bank"; 2286 reg = <0x0 0xff630000 0x0 0x100>; 2287 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 2288 clocks = <&cru PCLK_PERI_GPIO2>, <&cru DCLK_PERI_GPIO2>; 2289 2290 gpio-controller; 2291 #gpio-cells = <2>; 2292 gpio-ranges = <&pinctrl 0 64 32>; 2293 interrupt-controller; 2294 #interrupt-cells = <2>; 2295 }; 2296 2297 gpio3: gpio@ffac0000 { 2298 compatible = "rockchip,gpio-bank"; 2299 reg = <0x0 0xffac0000 0x0 0x100>; 2300 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 2301 clocks = <&cru PCLK_GPIO3_VCCIO156>, <&cru DCLK_BUS_GPIO3>; 2302 2303 gpio-controller; 2304 #gpio-cells = <2>; 2305 gpio-ranges = <&pinctrl 0 96 32>; 2306 interrupt-controller; 2307 #interrupt-cells = <2>; 2308 }; 2309 2310 gpio4: gpio@ffad0000 { 2311 compatible = "rockchip,gpio-bank"; 2312 reg = <0x0 0xffad0000 0x0 0x100>; 2313 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 2314 clocks = <&cru PCLK_GPIO4_VCCIO156>, <&cru DCLK_BUS_GPIO4>; 2315 2316 gpio-controller; 2317 #gpio-cells = <2>; 2318 gpio-ranges = <&pinctrl 0 128 32>; 2319 interrupt-controller; 2320 #interrupt-cells = <2>; 2321 }; 2322 }; 2323}; 2324 2325#include "rk3562-pinctrl.dtsi" 2326