1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3562-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/power/rk3562-power.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/soc/rockchip-system-status.h> 14#include <dt-bindings/suspend/rockchip-rk3562.h> 15#include <dt-bindings/thermal/thermal.h> 16 17/ { 18 compatible = "rockchip,rk3562"; 19 20 interrupt-parent = <&gic>; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 aliases { 25 csi2dphy0 = &csi2_dphy0; 26 csi2dphy1 = &csi2_dphy1; 27 csi2dphy2 = &csi2_dphy2; 28 csi2dphy3 = &csi2_dphy3; 29 csi2dphy4 = &csi2_dphy4; 30 csi2dphy5 = &csi2_dphy5; 31 ethernet0 = &gmac0; 32 ethernet1 = &gmac1; 33 gpio0 = &gpio0; 34 gpio1 = &gpio1; 35 gpio2 = &gpio2; 36 gpio3 = &gpio3; 37 gpio4 = &gpio4; 38 i2c0 = &i2c0; 39 i2c1 = &i2c1; 40 i2c2 = &i2c2; 41 i2c3 = &i2c3; 42 i2c4 = &i2c4; 43 i2c5 = &i2c5; 44 rkcif_mipi_lvds0= &rkcif_mipi_lvds; 45 rkcif_mipi_lvds1= &rkcif_mipi_lvds1; 46 rkcif_mipi_lvds2= &rkcif_mipi_lvds2; 47 rkcif_mipi_lvds3= &rkcif_mipi_lvds3; 48 serial0 = &uart0; 49 serial1 = &uart1; 50 serial2 = &uart2; 51 serial3 = &uart3; 52 serial4 = &uart4; 53 serial5 = &uart5; 54 serial6 = &uart6; 55 serial7 = &uart7; 56 serial8 = &uart8; 57 serial9 = &uart9; 58 spi0 = &spi0; 59 spi1 = &spi1; 60 spi2 = &spi2; 61 spi3 = &sfc; 62 }; 63 64 clocks { 65 compatible = "simple-bus"; 66 #address-cells = <2>; 67 #size-cells = <2>; 68 ranges; 69 70 xin32k: xin32k { 71 compatible = "fixed-clock"; 72 #clock-cells = <0>; 73 clock-frequency = <32768>; 74 clock-output-names = "xin32k"; 75 }; 76 77 xin24m: xin24m { 78 compatible = "fixed-clock"; 79 #clock-cells = <0>; 80 clock-frequency = <24000000>; 81 clock-output-names = "xin24m"; 82 }; 83 84 hclk_vepu: hclk_vepu@ff100324 { 85 compatible = "rockchip,rk3562-clock-gate-link"; 86 reg = <0 0xff100324 0 0x10>; 87 clock-names = "link"; 88 clocks = <&cru HCLK_VI>; 89 #power-domain-cells = <1>; 90 #clock-cells = <0>; 91 }; 92 93 aclk_vdpu: aclk_vdpu@ff100328 { 94 compatible = "rockchip,rk3562-clock-gate-link"; 95 reg = <0 0xff100328 0 0x10>; 96 clock-names = "link"; 97 clocks = <&cru ACLK_TOP_VIO>; 98 #power-domain-cells = <1>; 99 #clock-cells = <0>; 100 }; 101 102 aclk_vi_isp: aclk_vi_isp@ff10032c { 103 compatible = "rockchip,rk3562-clock-gate-link"; 104 reg = <0 0xff10032c 0 0x10>; 105 clock-names = "link"; 106 clocks = <&cru ACLK_TOP_VIO>; 107 #power-domain-cells = <1>; 108 #clock-cells = <0>; 109 }; 110 111 aclk_vo: aclk_vo@ff100334 { 112 compatible = "rockchip,rk3562-clock-gate-link"; 113 reg = <0 0xff100334 0 0x10>; 114 clock-names = "link"; 115 clocks = <&cru ACLK_TOP_VIO>; 116 #power-domain-cells = <1>; 117 #clock-cells = <0>; 118 }; 119 120 aclk_vepu: aclk_vepu@ff100324 { 121 compatible = "rockchip,rk3562-clock-gate-link"; 122 reg = <0 0xff100324 0 0x10>; 123 clock-names = "link"; 124 clocks = <&aclk_vi_isp>; 125 #power-domain-cells = <1>; 126 #clock-cells = <0>; 127 }; 128 129 aclk_rga_jdec: aclk_rga_jdec@ff100338 { 130 compatible = "rockchip,rk3562-clock-gate-link"; 131 reg = <0 0xff100338 0 0x10>; 132 clock-names = "link"; 133 clocks = <&aclk_vo>; 134 #power-domain-cells = <1>; 135 #clock-cells = <0>; 136 }; 137 138 mclkin_sai0: mclkin-sai0 { 139 compatible = "fixed-clock"; 140 #clock-cells = <0>; 141 clock-frequency = <0>; 142 clock-output-names = "mclk_sai0_from_io"; 143 }; 144 145 mclkin_sai1: mclkin-sai1 { 146 compatible = "fixed-clock"; 147 #clock-cells = <0>; 148 clock-frequency = <0>; 149 clock-output-names = "mclk_sai1_from_io"; 150 }; 151 152 mclkin_sai2: mclkin-sai2 { 153 compatible = "fixed-clock"; 154 #clock-cells = <0>; 155 clock-frequency = <0>; 156 clock-output-names = "mclk_sai2_from_io"; 157 }; 158 159 mclkout_sai0: mclkout-sai0@ff040070 { 160 compatible = "rockchip,clk-out"; 161 reg = <0 0xff040070 0 0x4>; 162 clocks = <&cru MCLK_SAI0_OUT2IO>; 163 #clock-cells = <0>; 164 clock-output-names = "mclk_sai0_to_io"; 165 rockchip,bit-shift = <4>; 166 }; 167 168 mclkout_sai1: mclkout-sai1@ff040070 { 169 compatible = "rockchip,clk-out"; 170 reg = <0 0xff040070 0 0x4>; 171 clocks = <&cru MCLK_SAI1_OUT2IO>; 172 #clock-cells = <0>; 173 clock-output-names = "mclk_sai1_to_io"; 174 rockchip,bit-shift = <9>; 175 }; 176 177 mclkout_sai2: mclkout-sai2@ff040070 { 178 compatible = "rockchip,clk-out"; 179 reg = <0 0xff040070 0 0x4>; 180 clocks = <&cru MCLK_SAI2_OUT2IO>; 181 #clock-cells = <0>; 182 clock-output-names = "mclk_sai2_to_io"; 183 rockchip,bit-shift = <11>; 184 }; 185 }; 186 187 cpus { 188 #address-cells = <2>; 189 #size-cells = <0>; 190 191 cpu0: cpu@0 { 192 device_type = "cpu"; 193 compatible = "arm,cortex-a53"; 194 reg = <0x0 0x0>; 195 enable-method = "psci"; 196 clocks = <&scmi_clk ARMCLK>; 197 cpu-idle-states = <&CPU_SLEEP>; 198 operating-points-v2 = <&cpu0_opp_table>; 199 #cooling-cells = <2>; 200 dynamic-power-coefficient = <138>; 201 }; 202 cpu1: cpu@1 { 203 device_type = "cpu"; 204 compatible = "arm,cortex-a53"; 205 reg = <0x0 0x1>; 206 enable-method = "psci"; 207 clocks = <&scmi_clk ARMCLK>; 208 cpu-idle-states = <&CPU_SLEEP>; 209 operating-points-v2 = <&cpu0_opp_table>; 210 #cooling-cells = <2>; 211 dynamic-power-coefficient = <138>; 212 }; 213 cpu2: cpu@2 { 214 device_type = "cpu"; 215 compatible = "arm,cortex-a53"; 216 reg = <0x0 0x2>; 217 enable-method = "psci"; 218 clocks = <&scmi_clk ARMCLK>; 219 cpu-idle-states = <&CPU_SLEEP>; 220 operating-points-v2 = <&cpu0_opp_table>; 221 #cooling-cells = <2>; 222 dynamic-power-coefficient = <138>; 223 }; 224 cpu3: cpu@3 { 225 device_type = "cpu"; 226 compatible = "arm,cortex-a53"; 227 reg = <0x0 0x3>; 228 enable-method = "psci"; 229 clocks = <&scmi_clk ARMCLK>; 230 cpu-idle-states = <&CPU_SLEEP>; 231 operating-points-v2 = <&cpu0_opp_table>; 232 #cooling-cells = <2>; 233 dynamic-power-coefficient = <138>; 234 }; 235 236 idle-states { 237 entry-method = "psci"; 238 CPU_SLEEP: cpu-sleep { 239 compatible = "arm,idle-state"; 240 local-timer-stop; 241 arm,psci-suspend-param = <0x0010000>; 242 entry-latency-us = <120>; 243 exit-latency-us = <250>; 244 min-residency-us = <900>; 245 }; 246 }; 247 }; 248 249 cpu0_opp_table: cpu0-opp-table { 250 compatible = "operating-points-v2"; 251 opp-shared; 252 253 mbist-vmin = <825000 900000 975000>; 254 nvmem-cells = <&cpu_leakage>, <&cpu_opp_info>, <&mbist_vmin>, <&cpu_pvtpll>; 255 nvmem-cell-names = "leakage", "opp-info", "mbist-vmin", "pvtm"; 256 257 rockchip,pvtm-voltage-sel = < 258 0 1280 0 259 1281 1350 1 260 1351 1420 2 261 1421 1490 3 262 1491 9999 4 263 >; 264 rockchip,pvtm-pvtpll; 265 rockchip,pvtm-offset = <0x634>; 266 rockchip,pvtm-sample-time = <1100>; 267 rockchip,pvtm-freq = <1608000>; 268 rockchip,pvtm-volt = <900000>; 269 rockchip,pvtm-ref-temp = <40>; 270 rockchip,pvtm-temp-prop = <0 0>; 271 rockchip,pvtm-thermal-zone = "soc-thermal"; 272 rockchip,grf = <&sys_grf>; 273 rockchip,temp-hysteresis = <5000>; 274 rockchip,low-temp = <10000>; 275 rockchip,low-temp-min-volt = <925000>; 276 277 opp-408000000 { 278 opp-hz = /bits/ 64 <408000000>; 279 opp-microvolt = <825000 825000 1150000>; 280 clock-latency-ns = <40000>; 281 opp-suspend; 282 }; 283 opp-600000000 { 284 opp-hz = /bits/ 64 <600000000>; 285 opp-microvolt = <825000 825000 1150000>; 286 clock-latency-ns = <40000>; 287 }; 288 opp-816000000 { 289 opp-hz = /bits/ 64 <816000000>; 290 opp-microvolt = <825000 825000 1150000>; 291 clock-latency-ns = <40000>; 292 }; 293 opp-1008000000 { 294 opp-hz = /bits/ 64 <1008000000>; 295 opp-microvolt = <850000 850000 1150000>; 296 opp-microvolt-L0 = <850000 850000 1150000>; 297 opp-microvolt-L1 = <825000 825000 1150000>; 298 opp-microvolt-L2 = <825000 825000 1150000>; 299 opp-microvolt-L3 = <825000 825000 1150000>; 300 opp-microvolt-L4 = <825000 825000 1150000>; 301 clock-latency-ns = <40000>; 302 }; 303 opp-1200000000 { 304 opp-hz = /bits/ 64 <1200000000>; 305 opp-microvolt = <925000 925000 1150000>; 306 opp-microvolt-L0 = <925000 925000 1150000>; 307 opp-microvolt-L1 = <900000 900000 1150000>; 308 opp-microvolt-L2 = <875000 875000 1150000>; 309 opp-microvolt-L3 = <850000 850000 1150000>; 310 opp-microvolt-L4 = <825000 825000 1150000>; 311 clock-latency-ns = <40000>; 312 }; 313 opp-1416000000 { 314 opp-hz = /bits/ 64 <1416000000>; 315 opp-microvolt = <1000000 1000000 1150000>; 316 opp-microvolt-L0 = <1000000 1000000 1150000>; 317 opp-microvolt-L1 = <975000 975000 1150000>; 318 opp-microvolt-L2 = <950000 950000 1150000>; 319 opp-microvolt-L3 = <925000 925000 1150000>; 320 opp-microvolt-L4 = <900000 900000 1150000>; 321 clock-latency-ns = <40000>; 322 }; 323 opp-1608000000 { 324 opp-hz = /bits/ 64 <1608000000>; 325 opp-microvolt = <1037500 1037500 1150000>; 326 opp-microvolt-L0 = <1037500 1037500 1150000>; 327 opp-microvolt-L1 = <1012500 1012500 1150000>; 328 opp-microvolt-L2 = <987500 987500 1150000>; 329 opp-microvolt-L3 = <962500 962500 1150000>; 330 opp-microvolt-L4 = <937500 937500 1150000>; 331 clock-latency-ns = <40000>; 332 }; 333 opp-1800000000 { 334 opp-hz = /bits/ 64 <1800000000>; 335 opp-microvolt = <1125000 1125000 1150000>; 336 opp-microvolt-L0 = <1125000 1125000 1150000>; 337 opp-microvolt-L1 = <1100000 1100000 1150000>; 338 opp-microvolt-L2 = <1075000 1075000 1150000>; 339 opp-microvolt-L3 = <1050000 1050000 1150000>; 340 opp-microvolt-L4 = <1025000 1025000 1150000>; 341 clock-latency-ns = <40000>; 342 }; 343 opp-2016000000 { 344 opp-hz = /bits/ 64 <2016000000>; 345 opp-microvolt = <1150000 1150000 1150000>; 346 opp-microvolt-L0 = <1150000 1150000 1150000>; 347 opp-microvolt-L1 = <1150000 1150000 1150000>; 348 opp-microvolt-L2 = <1125000 1125000 1150000>; 349 opp-microvolt-L3 = <1100000 1100000 1150000>; 350 opp-microvolt-L4 = <1075000 1075000 1150000>; 351 clock-latency-ns = <40000>; 352 }; 353 }; 354 355 arm-pmu { 356 compatible = "arm,cortex-a53-pmu"; 357 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 361 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 362 }; 363 364 bus_soc: bus-soc { 365 compatible = "rockchip,rk3562-bus"; 366 rockchip,busfreq-policy = "smc"; 367 rockchip,soc-bus-table = <0 0x00a000a8 0x7001>, 368 <1 0x00a000a8 0x7c39>, 369 <2 0x00a000a8 0x7c39>, 370 <3 0x00a000a8 0x7c39>, 371 <4 0x00a000a5 0xb007>, 372 <5 0x00a000a8 0x7034>, 373 <6 0x00a000a8 0x7034>, 374 <7 0x00a000a8 0x7034>, 375 <8 0x00a000a8 0x7001>; 376 }; 377 378 cpuinfo { 379 compatible = "rockchip,cpuinfo"; 380 nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>; 381 nvmem-cell-names = "id", "cpu-version", "cpu-code"; 382 }; 383 384 /* dphy0 full mode */ 385 csi2_dphy0: csi2-dphy0 { 386 compatible = "rockchip,rk3562-csi2-dphy"; 387 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 388 status = "disabled"; 389 }; 390 391 /* dphy0 split mode 01 */ 392 csi2_dphy1: csi2-dphy1 { 393 compatible = "rockchip,rk3562-csi2-dphy"; 394 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 395 status = "disabled"; 396 }; 397 398 /* dphy0 split mode 23 */ 399 csi2_dphy2: csi2-dphy2 { 400 compatible = "rockchip,rk3562-csi2-dphy"; 401 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 402 status = "disabled"; 403 }; 404 405 /* dphy1 full mode */ 406 csi2_dphy3: csi2-dphy3 { 407 compatible = "rockchip,rk3562-csi2-dphy"; 408 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 409 status = "disabled"; 410 }; 411 412 /* dphy1 split mode 01 */ 413 csi2_dphy4: csi2-dphy4 { 414 compatible = "rockchip,rk3562-csi2-dphy"; 415 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 416 status = "disabled"; 417 }; 418 419 /* dphy1 split mode 23 */ 420 csi2_dphy5: csi2-dphy5 { 421 compatible = "rockchip,rk3562-csi2-dphy"; 422 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 423 status = "disabled"; 424 }; 425 426 display_subsystem: display-subsystem { 427 compatible = "rockchip,display-subsystem"; 428 ports = <&vop_out>; 429 status = "disabled"; 430 431 memory-region = <&drm_logo>, <&drm_cubic_lut>; 432 memory-region-names = "drm-logo", "drm-cubic-lut"; 433 /* devfreq = <&dmc>; */ 434 435 route { 436 route_dsi: route-dsi { 437 status = "disabled"; 438 logo,uboot = "logo.bmp"; 439 logo,kernel = "logo_kernel.bmp"; 440 logo,mode = "center"; 441 charge_logo,mode = "center"; 442 connect = <&vp0_out_dsi>; 443 }; 444 route_lvds: route-lvds { 445 status = "disabled"; 446 logo,uboot = "logo.bmp"; 447 logo,kernel = "logo_kernel.bmp"; 448 logo,mode = "center"; 449 charge_logo,mode = "center"; 450 connect = <&vp0_out_lvds>; 451 }; 452 route_rgb: route-rgb { 453 status = "disabled"; 454 logo,uboot = "logo.bmp"; 455 logo,kernel = "logo_kernel.bmp"; 456 logo,mode = "center"; 457 charge_logo,mode = "center"; 458 connect = <&vp0_out_rgb>; 459 }; 460 }; 461 }; 462 463 dmc: dmc { 464 compatible = "rockchip,rk3562-dmc"; 465 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 466 interrupt-names = "complete"; 467 devfreq-events = <&dfi>; 468 clocks = <&scmi_clk CLK_DDR>; 469 clock-names = "dmc_clk"; 470 operating-points-v2 = <&dmc_opp_table>; 471 upthreshold = <40>; 472 downdifferential = <20>; 473 system-status-level = < 474 /*system status freq level*/ 475 SYS_STATUS_NORMAL DMC_FREQ_LEVEL_MID_HIGH 476 SYS_STATUS_REBOOT DMC_FREQ_LEVEL_HIGH 477 SYS_STATUS_SUSPEND DMC_FREQ_LEVEL_LOW 478 SYS_STATUS_VIDEO_4K DMC_FREQ_LEVEL_MID_HIGH 479 SYS_STATUS_VIDEO_4K_10B DMC_FREQ_LEVEL_MID_HIGH 480 SYS_STATUS_BOOST DMC_FREQ_LEVEL_HIGH 481 SYS_STATUS_ISP DMC_FREQ_LEVEL_HIGH 482 SYS_STATUS_PERFORMANCE DMC_FREQ_LEVEL_HIGH 483 SYS_STATUS_DUALVIEW DMC_FREQ_LEVEL_HIGH 484 >; 485 auto-min-freq = <324000>; 486 auto-freq-en = <1>; 487 #cooling-cells = <2>; 488 status = "disabled"; 489 }; 490 491 dmc_opp_table: dmc-opp-table { 492 compatible = "operating-points-v2"; 493 494 mbist-vmin = <850000 900000 925000>; 495 nvmem-cells = <&log_leakage>, <&dmc_opp_info>, <&log_mbist_vmin>; 496 nvmem-cell-names = "leakage", "opp-info", "mbist-vmin"; 497 498 rockchip,temp-hysteresis = <5000>; 499 rockchip,low-temp = <10000>; 500 rockchip,low-temp-min-volt = <900000>; 501 502 rockchip,leakage-voltage-sel = < 503 1 15 0 504 16 20 1 505 21 254 2 506 >; 507 508 opp-1560000000 { 509 opp-hz = /bits/ 64 <1560000000>; 510 opp-microvolt = <900000 900000 950000>; 511 opp-microvolt-L0 = <900000 900000 950000>; 512 opp-microvolt-L1 = <875000 875000 950000>; 513 opp-microvolt-L2 = <850000 850000 950000>; 514 }; 515 }; 516 517 firmware { 518 scmi: scmi { 519 compatible = "arm,scmi-smc"; 520 shmem = <&scmi_shmem>; 521 arm,smc-id = <0x82000010>; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 525 scmi_clk: protocol@14 { 526 reg = <0x14>; 527 #clock-cells = <1>; 528 }; 529 }; 530 }; 531 532 mpp_srv: mpp-srv { 533 compatible = "rockchip,mpp-service"; 534 rockchip,taskqueue-count = <3>; 535 rockchip,resetgroup-count = <3>; 536 status = "disabled"; 537 }; 538 539 mipi0_csi2: mipi0-csi2 { 540 compatible = "rockchip,rk3562-mipi-csi2"; 541 rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, 542 <&mipi2_csi2_hw>, <&mipi3_csi2_hw>; 543 status = "disabled"; 544 }; 545 546 mipi1_csi2: mipi1-csi2 { 547 compatible = "rockchip,rk3562-mipi-csi2"; 548 rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, 549 <&mipi2_csi2_hw>, <&mipi3_csi2_hw>; 550 status = "disabled"; 551 }; 552 553 mipi2_csi2: mipi2-csi2 { 554 compatible = "rockchip,rk3562-mipi-csi2"; 555 rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, 556 <&mipi2_csi2_hw>, <&mipi3_csi2_hw>; 557 status = "disabled"; 558 }; 559 560 mipi3_csi2: mipi3-csi2 { 561 compatible = "rockchip,rk3562-mipi-csi2"; 562 rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, 563 <&mipi2_csi2_hw>, <&mipi3_csi2_hw>; 564 status = "disabled"; 565 }; 566 567 psci { 568 compatible = "arm,psci-1.0"; 569 method = "smc"; 570 }; 571 572 reserved_memory: reserved-memory { 573 #address-cells = <2>; 574 #size-cells = <2>; 575 ranges; 576 577 drm_logo: drm-logo@00000000 { 578 compatible = "rockchip,drm-logo"; 579 reg = <0x0 0x0 0x0 0x0>; 580 }; 581 582 vendor_storage_rm: vendor-storage-rm@00000000 { 583 compatible = "rockchip,vendor-storage-rm"; 584 reg = <0x0 0x0 0x0 0x0>; 585 }; 586 587 drm_cubic_lut: drm-cubic-lut@00000000 { 588 compatible = "rockchip,drm-cubic-lut"; 589 reg = <0x0 0x0 0x0 0x0>; 590 }; 591 592 ramoops: ramoops@110000 { 593 compatible = "ramoops"; 594 /* 0x110000 to 0x1f0000 is for ramoops */ 595 reg = <0x0 0x110000 0x0 0xe0000>; 596 boot-log-size = <0x8000>; /* do not change */ 597 boot-log-count = <0x1>; /* do not change */ 598 console-size = <0x80000>; 599 pmsg-size = <0x30000>; 600 ftrace-size = <0x00000>; 601 record-size = <0x14000>; 602 }; 603 }; 604 605 rkcif_mipi_lvds: rkcif-mipi-lvds { 606 compatible = "rockchip,rkcif-mipi-lvds"; 607 rockchip,hw = <&rkcif>; 608 iommus = <&rkcif_mmu>; 609 status = "disabled"; 610 }; 611 612 rkcif_mipi_lvds_sditf: rkcif-mipi-lvds-sditf { 613 compatible = "rockchip,rkcif-sditf"; 614 rockchip,cif = <&rkcif_mipi_lvds>; 615 status = "disabled"; 616 }; 617 618 rkcif_mipi_lvds_sditf_vir1: rkcif-mipi-lvds-sditf-vir1 { 619 compatible = "rockchip,rkcif-sditf"; 620 rockchip,cif = <&rkcif_mipi_lvds>; 621 status = "disabled"; 622 }; 623 624 rkcif_mipi_lvds_sditf_vir2: rkcif-mipi-lvds-sditf-vir2 { 625 compatible = "rockchip,rkcif-sditf"; 626 rockchip,cif = <&rkcif_mipi_lvds>; 627 status = "disabled"; 628 }; 629 630 rkcif_mipi_lvds_sditf_vir3: rkcif-mipi-lvds-sditf-vir3 { 631 compatible = "rockchip,rkcif-sditf"; 632 rockchip,cif = <&rkcif_mipi_lvds>; 633 status = "disabled"; 634 }; 635 636 rkcif_mipi_lvds1: rkcif-mipi-lvds1 { 637 compatible = "rockchip,rkcif-mipi-lvds"; 638 rockchip,hw = <&rkcif>; 639 iommus = <&rkcif_mmu>; 640 status = "disabled"; 641 }; 642 643 rkcif_mipi_lvds1_sditf: rkcif-mipi-lvds1-sditf { 644 compatible = "rockchip,rkcif-sditf"; 645 rockchip,cif = <&rkcif_mipi_lvds1>; 646 status = "disabled"; 647 }; 648 649 rkcif_mipi_lvds1_sditf_vir1: rkcif-mipi-lvds1-sditf-vir1 { 650 compatible = "rockchip,rkcif-sditf"; 651 rockchip,cif = <&rkcif_mipi_lvds1>; 652 status = "disabled"; 653 }; 654 655 rkcif_mipi_lvds1_sditf_vir2: rkcif-mipi-lvds1-sditf-vir2 { 656 compatible = "rockchip,rkcif-sditf"; 657 rockchip,cif = <&rkcif_mipi_lvds1>; 658 status = "disabled"; 659 }; 660 661 rkcif_mipi_lvds1_sditf_vir3: rkcif-mipi-lvds1-sditf-vir3 { 662 compatible = "rockchip,rkcif-sditf"; 663 rockchip,cif = <&rkcif_mipi_lvds1>; 664 status = "disabled"; 665 }; 666 667 rkcif_mipi_lvds2: rkcif-mipi-lvds2 { 668 compatible = "rockchip,rkcif-mipi-lvds"; 669 rockchip,hw = <&rkcif>; 670 iommus = <&rkcif_mmu>; 671 status = "disabled"; 672 }; 673 674 rkcif_mipi_lvds2_sditf: rkcif-mipi-lvds2-sditf { 675 compatible = "rockchip,rkcif-sditf"; 676 rockchip,cif = <&rkcif_mipi_lvds2>; 677 status = "disabled"; 678 }; 679 680 rkcif_mipi_lvds2_sditf_vir1: rkcif-mipi-lvds2-sditf-vir1 { 681 compatible = "rockchip,rkcif-sditf"; 682 rockchip,cif = <&rkcif_mipi_lvds2>; 683 status = "disabled"; 684 }; 685 686 rkcif_mipi_lvds2_sditf_vir2: rkcif-mipi-lvds2-sditf-vir2 { 687 compatible = "rockchip,rkcif-sditf"; 688 rockchip,cif = <&rkcif_mipi_lvds2>; 689 status = "disabled"; 690 }; 691 692 rkcif_mipi_lvds2_sditf_vir3: rkcif-mipi-lvds2-sditf-vir3 { 693 compatible = "rockchip,rkcif-sditf"; 694 rockchip,cif = <&rkcif_mipi_lvds2>; 695 status = "disabled"; 696 }; 697 698 rkcif_mipi_lvds3: rkcif-mipi-lvds3 { 699 compatible = "rockchip,rkcif-mipi-lvds"; 700 rockchip,hw = <&rkcif>; 701 iommus = <&rkcif_mmu>; 702 status = "disabled"; 703 }; 704 705 rkcif_mipi_lvds3_sditf: rkcif-mipi-lvds3-sditf { 706 compatible = "rockchip,rkcif-sditf"; 707 rockchip,cif = <&rkcif_mipi_lvds3>; 708 status = "disabled"; 709 }; 710 711 rkcif_mipi_lvds3_sditf_vir1: rkcif-mipi-lvds3-sditf-vir1 { 712 compatible = "rockchip,rkcif-sditf"; 713 rockchip,cif = <&rkcif_mipi_lvds3>; 714 status = "disabled"; 715 }; 716 717 rkcif_mipi_lvds3_sditf_vir2: rkcif-mipi-lvds3-sditf-vir2 { 718 compatible = "rockchip,rkcif-sditf"; 719 rockchip,cif = <&rkcif_mipi_lvds3>; 720 status = "disabled"; 721 }; 722 723 rkcif_mipi_lvds3_sditf_vir3: rkcif-mipi-lvds3-sditf-vir3 { 724 compatible = "rockchip,rkcif-sditf"; 725 rockchip,cif = <&rkcif_mipi_lvds3>; 726 status = "disabled"; 727 }; 728 729 rkisp_vir0: rkisp-vir0 { 730 compatible = "rockchip,rkisp-vir"; 731 rockchip,hw = <&rkisp>; 732 status = "disabled"; 733 }; 734 735 rkisp_vir1: rkisp-vir1 { 736 compatible = "rockchip,rkisp-vir"; 737 rockchip,hw = <&rkisp>; 738 status = "disabled"; 739 }; 740 741 rkisp_vir2: rkisp-vir2 { 742 compatible = "rockchip,rkisp-vir"; 743 rockchip,hw = <&rkisp>; 744 status = "disabled"; 745 }; 746 747 rkisp_vir3: rkisp-vir3 { 748 compatible = "rockchip,rkisp-vir"; 749 rockchip,hw = <&rkisp>; 750 status = "disabled"; 751 }; 752 753 rockchip_system_monitor: rockchip-system-monitor { 754 compatible = "rockchip,system-monitor"; 755 rockchip,thermal-zone = "soc-thermal"; 756 }; 757 758 thermal_zones: thermal-zones { 759 soc_thermal: soc-thermal { 760 polling-delay-passive = <20>; /* milliseconds */ 761 polling-delay = <1000>; /* milliseconds */ 762 sustainable-power = <685>; /* milliwatts */ 763 764 thermal-sensors = <&tsadc 0>; 765 trips { 766 threshold: trip-point-0 { 767 temperature = <75000>; 768 hysteresis = <2000>; 769 type = "passive"; 770 }; 771 target: trip-point-1 { 772 temperature = <85000>; 773 hysteresis = <2000>; 774 type = "passive"; 775 }; 776 soc_crit: soc-crit { 777 /* millicelsius */ 778 temperature = <115000>; 779 /* millicelsius */ 780 hysteresis = <2000>; 781 type = "critical"; 782 }; 783 }; 784 cooling-maps { 785 map0 { 786 trip = <&target>; 787 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 788 contribution = <1024>; 789 }; 790 map1 { 791 trip = <&target>; 792 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 793 contribution = <1024>; 794 }; 795 }; 796 }; 797 }; 798 799 timer { 800 compatible = "arm,armv8-timer"; 801 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 802 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 803 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 804 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 805 }; 806 807 vendor_storage: vendor-storage { 808 compatible = "rockchip,ram-vendor-storage"; 809 memory-region = <&vendor_storage_rm>; 810 status = "okay"; 811 }; 812 813 scmi_shmem: scmi-shmem@10f000 { 814 compatible = "arm,scmi-shmem"; 815 reg = <0x0 0x0010f000 0x0 0x100>; 816 }; 817 818 usbdrd30: usbdrd { 819 compatible = "rockchip,rk3562-dwc3", "rockchip,rk3399-dwc3"; 820 clocks = <&cru CLK_USB3OTG_REF>, <&cru CLK_USB3OTG_SUSPEND>, 821 <&cru ACLK_USB3OTG>, <&cru PCLK_PHP>; 822 clock-names = "ref", "suspend", "bus", "pipe_clk"; 823 #address-cells = <2>; 824 #size-cells = <2>; 825 ranges; 826 status = "disabled"; 827 828 usbdrd_dwc3: usb@fe500000 { 829 compatible = "snps,dwc3"; 830 reg = <0x0 0xfe500000 0x0 0x400000>; 831 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 832 dr_mode = "otg"; 833 phys = <&u2phy_otg>, <&combphy_pu PHY_TYPE_USB3>; 834 phy-names = "usb2-phy", "usb3-phy"; 835 phy_type = "utmi_wide"; 836 power-domains = <&power RK3562_PD_PHP>; 837 resets = <&cru SRST_USB3OTG>; 838 reset-names = "usb3-otg"; 839 snps,dis_enblslpm_quirk; 840 snps,dis-u1-entry-quirk; 841 snps,dis-u2-entry-quirk; 842 snps,dis-u2-freeclk-exists-quirk; 843 snps,dis-del-phy-power-chg-quirk; 844 snps,dis-tx-ipgap-linecheck-quirk; 845 snps,dis_rxdet_inp3_quirk; 846 quirk-skip-phy-init; 847 status = "disabled"; 848 }; 849 }; 850 851 gic: interrupt-controller@fe901000 { 852 compatible = "arm,gic-400"; 853 #interrupt-cells = <3>; 854 #address-cells = <0>; 855 interrupt-controller; 856 reg = <0x0 0xfe901000 0 0x1000>, 857 <0x0 0xfe902000 0 0x2000>, 858 <0x0 0xfe904000 0 0x2000>, 859 <0x0 0xfe906000 0 0x2000>; 860 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 861 }; 862 863 usb_host0_ehci: usb@fed00000 { 864 compatible = "generic-ehci"; 865 reg = <0x0 0xfed00000 0x0 0x40000>; 866 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 867 clocks = <&cru HCLK_USB2HOST>, <&cru HCLK_USB2HOST_ARB>, 868 <&u2phy>; 869 clock-names = "usbhost", "arbiter", "utmi"; 870 phys = <&u2phy_host>; 871 phy-names = "usb2-phy"; 872 status = "disabled"; 873 }; 874 875 usb_host0_ohci: usb@fed40000 { 876 compatible = "generic-ohci"; 877 reg = <0x0 0xfed40000 0x0 0x40000>; 878 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 879 clocks = <&cru HCLK_USB2HOST>, <&cru HCLK_USB2HOST_ARB>, 880 <&u2phy>; 881 clock-names = "usbhost", "arbiter", "utmi"; 882 phys = <&u2phy_host>; 883 phy-names = "usb2-phy"; 884 status = "disabled"; 885 }; 886 887 debug: debug@fed90000 { 888 compatible = "rockchip,debug"; 889 reg = <0x0 0xfed90000 0x0 0x2000>, 890 <0x0 0xfed92000 0x0 0x2000>, 891 <0x0 0xfed94000 0x0 0x2000>, 892 <0x0 0xfed96000 0x0 0x2000>; 893 }; 894 895 qos_dma2ddr: qos@fee03800 { 896 compatible = "syscon"; 897 reg = <0x0 0xfee03800 0x0 0x20>; 898 }; 899 900 qos_mcu: qos@fee10000 { 901 compatible = "syscon"; 902 reg = <0x0 0xfee10000 0x0 0x20>; 903 }; 904 905 qos_dft_apb: qos@fee10100 { 906 compatible = "syscon"; 907 reg = <0x0 0xfee10100 0x0 0x20>; 908 }; 909 910 qos_gmac: qos@fee10200 { 911 compatible = "syscon"; 912 reg = <0x0 0xfee10200 0x0 0x20>; 913 }; 914 915 qos_mac100: qos@fee10300 { 916 compatible = "syscon"; 917 reg = <0x0 0xfee10300 0x0 0x20>; 918 }; 919 920 qos_dcf: qos@fee10400 { 921 compatible = "syscon"; 922 reg = <0x0 0xfee10400 0x0 0x20>; 923 }; 924 925 qos_cpu: qos@fee20000 { 926 compatible = "syscon"; 927 reg = <0x0 0xfee20000 0x0 0x20>; 928 }; 929 930 qos_daplite_apb: qos@fee20100 { 931 compatible = "syscon"; 932 reg = <0x0 0xfee20100 0x0 0x20>; 933 }; 934 935 qos_gpu: qos@fee30000 { 936 compatible = "syscon"; 937 reg = <0x0 0xfee30000 0x0 0x20>; 938 priority-init = <0x202>; 939 }; 940 941 qos_npu: qos@fee40000 { 942 compatible = "syscon"; 943 reg = <0x0 0xfee40000 0x0 0x20>; 944 }; 945 946 qos_rkvdec: qos@fee50000 { 947 compatible = "syscon"; 948 reg = <0x0 0xfee50000 0x0 0x20>; 949 }; 950 951 qos_vepu: qos@fee60000 { 952 compatible = "syscon"; 953 reg = <0x0 0xfee60000 0x0 0x20>; 954 }; 955 956 qos_isp: qos@fee70000 { 957 compatible = "syscon"; 958 reg = <0x0 0xfee70000 0x0 0x20>; 959 }; 960 961 qos_vicap: qos@fee70100 { 962 compatible = "syscon"; 963 reg = <0x0 0xfee70100 0x0 0x20>; 964 }; 965 966 qos_vop: qos@fee80000 { 967 compatible = "syscon"; 968 reg = <0x0 0xfee80000 0x0 0x20>; 969 }; 970 971 qos_jpeg: qos@fee90000 { 972 compatible = "syscon"; 973 reg = <0x0 0xfee90000 0x0 0x20>; 974 }; 975 976 qos_rga_rd: qos@fee90100 { 977 compatible = "syscon"; 978 reg = <0x0 0xfee90100 0x0 0x20>; 979 }; 980 981 qos_rga_wr: qos@fee90200 { 982 compatible = "syscon"; 983 reg = <0x0 0xfee90200 0x0 0x20>; 984 }; 985 986 qos_pcie: qos@feea0000 { 987 compatible = "syscon"; 988 reg = <0x0 0xfeea0000 0x0 0x20>; 989 }; 990 991 qos_usb3: qos@feea0100 { 992 compatible = "syscon"; 993 reg = <0x0 0xfeea0100 0x0 0x20>; 994 }; 995 996 qos_crypto_apb: qos@feeb0000 { 997 compatible = "syscon"; 998 reg = <0x0 0xfeeb0000 0x0 0x20>; 999 }; 1000 1001 qos_crypto: qos@feeb0100 { 1002 compatible = "syscon"; 1003 reg = <0x0 0xfeeb0100 0x0 0x20>; 1004 }; 1005 1006 qos_dmac: qos@feeb0200 { 1007 compatible = "syscon"; 1008 reg = <0x0 0xfeeb0200 0x0 0x20>; 1009 }; 1010 1011 qos_emmc: qos@feeb0300 { 1012 compatible = "syscon"; 1013 reg = <0x0 0xfeeb0300 0x0 0x20>; 1014 }; 1015 1016 qos_fspi: qos@feeb0400 { 1017 compatible = "syscon"; 1018 reg = <0x0 0xfeeb0400 0x0 0x20>; 1019 }; 1020 1021 qos_rkdma: qos@feeb0500 { 1022 compatible = "syscon"; 1023 reg = <0x0 0xfeeb0500 0x0 0x20>; 1024 }; 1025 1026 qos_sdmmc0: qos@feeb0600 { 1027 compatible = "syscon"; 1028 reg = <0x0 0xfeeb0600 0x0 0x20>; 1029 }; 1030 1031 qos_sdmmc1: qos@feeb0700 { 1032 compatible = "syscon"; 1033 reg = <0x0 0xfeeb0700 0x0 0x20>; 1034 }; 1035 1036 qos_usb2: qos@feeb0800 { 1037 compatible = "syscon"; 1038 reg = <0x0 0xfeeb0800 0x0 0x20>; 1039 }; 1040 1041 pmu_grf: syscon@ff010000 { 1042 compatible = "rockchip,rk3562-pmu-grf", "syscon", "simple-mfd"; 1043 reg = <0x0 0xff010000 0x0 0x10000>; 1044 1045 reboot_mode: reboot-mode { 1046 compatible = "syscon-reboot-mode"; 1047 offset = <0x220>; 1048 mode-bootloader = <BOOT_BL_DOWNLOAD>; 1049 mode-charge = <BOOT_CHARGING>; 1050 mode-fastboot = <BOOT_FASTBOOT>; 1051 mode-loader = <BOOT_BL_DOWNLOAD>; 1052 mode-normal = <BOOT_NORMAL>; 1053 mode-recovery = <BOOT_RECOVERY>; 1054 mode-ums = <BOOT_UMS>; 1055 mode-panic = <BOOT_PANIC>; 1056 mode-watchdog = <BOOT_WATCHDOG>; 1057 }; 1058 }; 1059 1060 sys_grf: syscon@ff030000 { 1061 compatible = "rockchip,rk3562-sys-grf", "syscon", "simple-mfd"; 1062 reg = <0x0 0xff030000 0x0 0x10000>; 1063 1064 lvds: lvds { 1065 compatible = "rockchip,rk3562-lvds"; 1066 phys = <&video_phy>; 1067 phy-names = "phy"; 1068 status = "disabled"; 1069 1070 ports { 1071 #address-cells = <1>; 1072 #size-cells = <0>; 1073 1074 port@0 { 1075 reg = <0>; 1076 #address-cells = <1>; 1077 #size-cells = <0>; 1078 1079 lvds_in_vp0: endpoint@0 { 1080 reg = <0>; 1081 remote-endpoint = <&vp0_out_lvds>; 1082 status = "disabled"; 1083 }; 1084 }; 1085 }; 1086 }; 1087 }; 1088 1089 peri_grf: syscon@ff040000 { 1090 compatible = "rockchip,rk3562-peri-grf", "syscon"; 1091 reg = <0x0 0xff040000 0x0 0x10000>; 1092 }; 1093 1094 ioc_grf: syscon@ff060000 { 1095 compatible = "rockchip,rk3562-ioc-grf", "syscon", "simple-mfd"; 1096 reg = <0x0 0xff060000 0x0 0x30000>; 1097 1098 rgb: rgb { 1099 compatible = "rockchip,rk3562-rgb"; 1100 pinctrl-names = "default"; 1101 pinctrl-0 = <&vo_pins>; 1102 status = "disabled"; 1103 1104 ports { 1105 #address-cells = <1>; 1106 #size-cells = <0>; 1107 1108 port@0 { 1109 reg = <0>; 1110 #address-cells = <1>; 1111 #size-cells = <0>; 1112 1113 rgb_in_vp0: endpoint@0 { 1114 reg = <0>; 1115 remote-endpoint = <&vp0_out_rgb>; 1116 status = "disabled"; 1117 }; 1118 }; 1119 }; 1120 }; 1121 }; 1122 1123 usbphy_grf: syscon@ff090000 { 1124 compatible = "rockchip,rk3562-usbphy-grf", "syscon"; 1125 reg = <0x0 0xff090000 0x0 0x8000>; 1126 }; 1127 1128 pipephy_grf: syscon@ff098000 { 1129 compatible = "rockchip,rk3562-pipephy-grf", "syscon"; 1130 reg = <0x0 0xff098000 0x0 0x8000>; 1131 }; 1132 1133 cru: clock-controller@ff100000 { 1134 compatible = "rockchip,rk3562-cru"; 1135 reg = <0x0 0xff100000 0x0 0x40000>; 1136 rockchip,grf = <&sys_grf>; 1137 #clock-cells = <1>; 1138 #reset-cells = <1>; 1139 1140 assigned-clocks = 1141 <&cru PLL_GPLL>, <&cru PLL_CPLL>, <&cru PLL_HPLL>; 1142 assigned-clock-rates = 1143 <1188000000>, <1000000000>, <983040000>; 1144 }; 1145 1146 i2c0: i2c@ff200000 { 1147 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; 1148 reg = <0x0 0xff200000 0x0 0x1000>; 1149 clocks = <&cru CLK_PMU0_I2C0>, <&cru PCLK_PMU0_I2C0>; 1150 clock-names = "i2c", "pclk"; 1151 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1152 pinctrl-names = "default"; 1153 pinctrl-0 = <&i2c0_xfer>; 1154 #address-cells = <1>; 1155 #size-cells = <0>; 1156 status = "disabled"; 1157 }; 1158 1159 uart0: serial@ff210000 { 1160 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 1161 reg = <0x0 0xff210000 0x0 0x100>; 1162 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1163 clocks = <&cru SCLK_PMU1_UART0>, <&cru PCLK_PMU1_UART0>; 1164 clock-names = "baudclk", "apb_pclk"; 1165 reg-shift = <2>; 1166 reg-io-width = <4>; 1167 dmas = <&dmac 0>; 1168 status = "disabled"; 1169 }; 1170 1171 spi0: spi@ff220000 { 1172 compatible = "rockchip,rk3066-spi"; 1173 reg = <0x0 0xff220000 0x0 0x1000>; 1174 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 clocks = <&cru CLK_PMU1_SPI0>, <&cru PCLK_PMU1_SPI0>, <&cru SCLK_IN_PMU1_SPI0>; 1178 clock-names = "spiclk", "apb_pclk", "sclk_in"; 1179 dmas = <&dmac 13>, <&dmac 12>; 1180 dma-names = "tx", "rx"; 1181 pinctrl-names = "default"; 1182 pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>; 1183 num-cs = <2>; 1184 status = "disabled"; 1185 }; 1186 1187 pwm0: pwm@ff230000 { 1188 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 1189 reg = <0x0 0xff230000 0x0 0x10>; 1190 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1191 #pwm-cells = <3>; 1192 pinctrl-names = "active"; 1193 pinctrl-0 = <&pwm0m0_pins>; 1194 clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; 1195 clock-names = "pwm", "pclk"; 1196 status = "disabled"; 1197 }; 1198 1199 pwm1: pwm@ff230010 { 1200 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 1201 reg = <0x0 0xff230010 0x0 0x10>; 1202 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1203 #pwm-cells = <3>; 1204 pinctrl-names = "active"; 1205 pinctrl-0 = <&pwm1m0_pins>; 1206 clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; 1207 clock-names = "pwm", "pclk"; 1208 status = "disabled"; 1209 }; 1210 1211 pwm2: pwm@ff230020 { 1212 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 1213 reg = <0x0 0xff230020 0x0 0x10>; 1214 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1215 #pwm-cells = <3>; 1216 pinctrl-names = "active"; 1217 pinctrl-0 = <&pwm2m0_pins>; 1218 clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; 1219 clock-names = "pwm", "pclk"; 1220 status = "disabled"; 1221 }; 1222 1223 pwm3: pwm@ff230030 { 1224 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 1225 reg = <0x0 0xff230030 0x0 0x10>; 1226 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1228 #pwm-cells = <3>; 1229 pinctrl-names = "active"; 1230 pinctrl-0 = <&pwm3m0_pins>; 1231 clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; 1232 clock-names = "pwm", "pclk"; 1233 status = "disabled"; 1234 }; 1235 1236 pmu: power-management@ff258000 { 1237 compatible = "rockchip,rk3562-pmu", "syscon", "simple-mfd"; 1238 reg = <0x0 0xff258000 0x0 0x1000>; 1239 1240 power: power-controller { 1241 compatible = "rockchip,rk3562-power-controller"; 1242 #power-domain-cells = <1>; 1243 #address-cells = <1>; 1244 #size-cells = <0>; 1245 status = "okay"; 1246 1247 /* These power domains are grouped by VD_GPU */ 1248 pd_gpu@RK3562_PD_GPU { 1249 reg = <RK3562_PD_GPU>; 1250 pm_qos = <&qos_gpu>; 1251 }; 1252 /* These power domains are grouped by VD_NPU */ 1253 pd_npu@RK3562_PD_NPU { 1254 reg = <RK3562_PD_NPU>; 1255 pm_qos = <&qos_npu>; 1256 }; 1257 /* These power domains are grouped by VD_LOGIC */ 1258 pd_vdpu@RK3562_PD_VDPU { 1259 reg = <RK3562_PD_VDPU>; 1260 pm_qos = <&qos_rkvdec>; 1261 }; 1262 pd_vi@RK3562_PD_VI { 1263 reg = <RK3562_PD_VI>; 1264 #address-cells = <1>; 1265 #size-cells = <0>; 1266 pm_qos = <&qos_isp>, 1267 <&qos_vicap>; 1268 1269 pd_vepu@RK3562_PD_VEPU { 1270 reg = <RK3562_PD_VEPU>; 1271 pm_qos = <&qos_vepu>; 1272 }; 1273 }; 1274 pd_vo@RK3562_PD_VO { 1275 reg = <RK3562_PD_VO>; 1276 #address-cells = <1>; 1277 #size-cells = <0>; 1278 pm_qos = <&qos_vop>; 1279 1280 pd_rga@RK3562_PD_RGA { 1281 reg = <RK3562_PD_RGA>; 1282 pm_qos = <&qos_rga_rd>, 1283 <&qos_rga_wr>, 1284 <&qos_jpeg>; 1285 }; 1286 }; 1287 pd_php@RK3562_PD_PHP { 1288 reg = <RK3562_PD_PHP>; 1289 pm_qos = <&qos_pcie>, 1290 <&qos_usb3>; 1291 }; 1292 }; 1293 }; 1294 1295 pmu_mailbox: mailbox@ff290000 { 1296 compatible = "rockchip,rk3562-mailbox", 1297 "rockchip,rk3368-mailbox"; 1298 reg = <0x0 0xff290000 0x0 0x200>; 1299 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1300 clocks = <&cru PCLK_PMU1_MAILBOX>; 1301 clock-names = "pclk_mailbox"; 1302 #mbox-cells = <1>; 1303 status = "disabled"; 1304 }; 1305 1306 rknpu: npu@ff300000 { 1307 compatible = "rockchip,rk3562-rknpu"; 1308 reg = <0x0 0xff300000 0x0 0x10000>; 1309 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1310 clocks = <&scmi_clk ACLK_RKNN>, <&cru ACLK_RKNN>, <&cru HCLK_RKNN>; 1311 clock-names = "scmi_clk", "aclk", "hclk"; 1312 assigned-clocks = <&cru ACLK_RKNN>; 1313 assigned-clock-rates = <600000000>; 1314 resets = <&cru SRST_A_RKNN>, <&cru SRST_H_RKNN>; 1315 reset-names = "srst_a", "srst_h"; 1316 power-domains = <&power RK3562_PD_NPU>; 1317 operating-points-v2 = <&npu_opp_table>; 1318 iommus = <&rknpu_mmu>; 1319 status = "disabled"; 1320 }; 1321 1322 npu_opp_table: npu-opp-table { 1323 compatible = "operating-points-v2"; 1324 1325 mbist-vmin = <825000 900000 975000>; 1326 nvmem-cells = <&npu_leakage>, <&npu_opp_info>, <&mbist_vmin>, <&npu_pvtpll>; 1327 nvmem-cell-names = "leakage", "opp-info", "mbist-vmin", "pvtm"; 1328 1329 rockchip,pvtm-voltage-sel = < 1330 0 760 0 1331 761 800 1 1332 801 840 2 1333 841 880 3 1334 881 9999 4 1335 >; 1336 rockchip,pvtm-pvtpll; 1337 rockchip,pvtm-offset = <0x674>; 1338 rockchip,pvtm-sample-time = <1100>; 1339 rockchip,pvtm-freq = <900000>; 1340 rockchip,pvtm-volt = <900000>; 1341 rockchip,pvtm-ref-temp = <40>; 1342 rockchip,pvtm-temp-prop = <0 0>; 1343 rockchip,pvtm-thermal-zone = "soc-thermal"; 1344 rockchip,grf = <&sys_grf>; 1345 rockchip,temp-hysteresis = <5000>; 1346 rockchip,low-temp = <10000>; 1347 rockchip,low-temp-min-volt = <925000>; 1348 1349 opp-300000000 { 1350 opp-hz = /bits/ 64 <300000000>; 1351 opp-microvolt = <825000 825000 1000000>; 1352 }; 1353 opp-400000000 { 1354 opp-hz = /bits/ 64 <400000000>; 1355 opp-microvolt = <825000 825000 1000000>; 1356 }; 1357 opp-500000000 { 1358 opp-hz = /bits/ 64 <500000000>; 1359 opp-microvolt = <825000 825000 1000000>; 1360 }; 1361 opp-600000000 { 1362 opp-hz = /bits/ 64 <600000000>; 1363 opp-microvolt = <875000 875000 1000000>; 1364 opp-microvolt-L0 = <875000 875000 1000000>; 1365 opp-microvolt-L1 = <850000 850000 1000000>; 1366 opp-microvolt-L2 = <825000 825000 1000000>; 1367 opp-microvolt-L3 = <825000 825000 1000000>; 1368 opp-microvolt-L4 = <825000 825000 1000000>; 1369 }; 1370 opp-700000000 { 1371 opp-hz = /bits/ 64 <700000000>; 1372 opp-microvolt = <925000 925000 1000000>; 1373 opp-microvolt-L0 = <925000 925000 1000000>; 1374 opp-microvolt-L1 = <900000 900000 1000000>; 1375 opp-microvolt-L2 = <875000 875000 1000000>; 1376 opp-microvolt-L3 = <850000 850000 1000000>; 1377 opp-microvolt-L4 = <825000 825000 1000000>; 1378 }; 1379 opp-800000000 { 1380 opp-hz = /bits/ 64 <800000000>; 1381 opp-microvolt = <975000 975000 1000000>; 1382 opp-microvolt-L0 = <975000 975000 1000000>; 1383 opp-microvolt-L1 = <950000 950000 1000000>; 1384 opp-microvolt-L2 = <925000 925000 1000000>; 1385 opp-microvolt-L3 = <900000 900000 1000000>; 1386 opp-microvolt-L4 = <875000 875000 1000000>; 1387 }; 1388 opp-900000000 { 1389 opp-hz = /bits/ 64 <900000000>; 1390 opp-microvolt = <1000000 1000000 1000000>; 1391 opp-microvolt-L0 = <1000000 1000000 1000000>; 1392 opp-microvolt-L1 = <1000000 1000000 1000000>; 1393 opp-microvolt-L2 = <975000 975000 1000000>; 1394 opp-microvolt-L3 = <950000 950000 1000000>; 1395 opp-microvolt-L4 = <925000 925000 1000000>; 1396 }; 1397 opp-1000000000 { 1398 opp-hz = /bits/ 64 <1000000000>; 1399 opp-microvolt = <1000000 1000000 1000000>; 1400 opp-microvolt-L0 = <1000000 1000000 1000000>; 1401 opp-microvolt-L1 = <1000000 1000000 1000000>; 1402 opp-microvolt-L2 = <1000000 1000000 1000000>; 1403 opp-microvolt-L3 = <975000 975000 1000000>; 1404 opp-microvolt-L4 = <950000 950000 1000000>; 1405 }; 1406 }; 1407 1408 rknpu_mmu: iommu@ff30a000 { 1409 compatible = "rockchip,iommu-v2"; 1410 reg = <0x0 0xff30a000 0x0 0x40>; 1411 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1412 interrupt-names = "rknpu_mmu"; 1413 clocks = <&cru ACLK_RKNN>, <&cru HCLK_RKNN>; 1414 clock-names = "aclk", "iface"; 1415 power-domains = <&power RK3562_PD_NPU>; 1416 #iommu-cells = <0>; 1417 status = "disabled"; 1418 }; 1419 1420 gpu: gpu@ff320000 { 1421 compatible = "arm,mali-bifrost"; 1422 reg = <0x0 0xff320000 0x0 0x4000>; 1423 1424 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 1426 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1427 interrupt-names = "GPU", "MMU", "JOB"; 1428 1429 upthreshold = <40>; 1430 downdifferential = <10>; 1431 1432 clocks = <&scmi_clk CLK_GPU>, <&cru CLK_GPU>, 1433 <&cru CLK_GPU_BRG>, <&cru ACLK_GPU_PRE>; 1434 clock-names = "clk_mali", "clk_gpu", "clk_gpu_brg", "aclk_gpu"; 1435 power-domains = <&power RK3562_PD_GPU>; 1436 operating-points-v2 = <&gpu_opp_table>; 1437 #cooling-cells = <2>; 1438 dynamic-power-coefficient = <820>; 1439 1440 status = "disabled"; 1441 }; 1442 1443 gpu_opp_table: gpu-opp-table { 1444 compatible = "operating-points-v2"; 1445 1446 mbist-vmin = <825000 900000 975000>; 1447 nvmem-cells = <&gpu_leakage>, <&gpu_opp_info>, <&mbist_vmin>, <&gpu_pvtpll>; 1448 nvmem-cell-names = "leakage", "opp-info", "mbist-vmin", "pvtm"; 1449 1450 rockchip,pvtm-voltage-sel = < 1451 0 780 0 1452 781 820 1 1453 821 860 2 1454 861 900 3 1455 901 9999 4 1456 >; 1457 rockchip,pvtm-pvtpll; 1458 rockchip,pvtm-offset = <0x654>; 1459 rockchip,pvtm-sample-time = <1100>; 1460 rockchip,pvtm-freq = <900000>; 1461 rockchip,pvtm-volt = <900000>; 1462 rockchip,pvtm-ref-temp = <40>; 1463 rockchip,pvtm-temp-prop = <0 0>; 1464 rockchip,pvtm-thermal-zone = "soc-thermal"; 1465 rockchip,grf = <&sys_grf>; 1466 rockchip,temp-hysteresis = <5000>; 1467 rockchip,low-temp = <10000>; 1468 rockchip,low-temp-min-volt = <925000>; 1469 1470 opp-300000000 { 1471 opp-hz = /bits/ 64 <300000000>; 1472 opp-microvolt = <825000 825000 1000000>; 1473 }; 1474 opp-400000000 { 1475 opp-hz = /bits/ 64 <400000000>; 1476 opp-microvolt = <825000 825000 1000000>; 1477 }; 1478 opp-500000000 { 1479 opp-hz = /bits/ 64 <500000000>; 1480 opp-microvolt = <825000 825000 1000000>; 1481 }; 1482 opp-600000000 { 1483 opp-hz = /bits/ 64 <600000000>; 1484 opp-microvolt = <825000 825000 1000000>; 1485 }; 1486 opp-700000000 { 1487 opp-hz = /bits/ 64 <700000000>; 1488 opp-microvolt = <900000 900000 1000000>; 1489 opp-microvolt-L0 = <900000 900000 1000000>; 1490 opp-microvolt-L1 = <875000 875000 1000000>; 1491 opp-microvolt-L2 = <850000 850000 1000000>; 1492 opp-microvolt-L3 = <825000 825000 1000000>; 1493 opp-microvolt-L4 = <825000 825000 1000000>; 1494 }; 1495 opp-800000000 { 1496 opp-hz = /bits/ 64 <800000000>; 1497 opp-microvolt = <950000 950000 1000000>; 1498 opp-microvolt-L0 = <950000 950000 1000000>; 1499 opp-microvolt-L1 = <925000 925000 1000000>; 1500 opp-microvolt-L2 = <900000 900000 1000000>; 1501 opp-microvolt-L3 = <875000 875000 1000000>; 1502 opp-microvolt-L4 = <850000 850000 1000000>; 1503 }; 1504 opp-900000000 { 1505 opp-hz = /bits/ 64 <900000000>; 1506 opp-microvolt = <1000000 1000000 1000000>; 1507 opp-microvolt-L0 = <1000000 1000000 1000000>; 1508 opp-microvolt-L1 = <975000 975000 1000000>; 1509 opp-microvolt-L2 = <950000 950000 1000000>; 1510 opp-microvolt-L3 = <925000 925000 1000000>; 1511 opp-microvolt-L4 = <900000 900000 1000000>; 1512 }; 1513 }; 1514 1515 rkvdec: rkvdec@ff340100 { 1516 compatible = "rockchip,rkv-decoder-rk3562", "rockchip,rkv-decoder-v2"; 1517 reg = <0x0 0xff340100 0x0 0x400>, <0x0 0xff340000 0x0 0x100>; 1518 reg-names = "regs", "link"; 1519 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1520 interrupt-names = "irq_dec"; 1521 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_RKVDEC_HEVC_CA>; 1522 clock-names = "aclk_vcodec", "hclk_vcodec","clk_hevc_cabac"; 1523 rockchip,normal-rates = <198000000>, <0>, <396000000>; 1524 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_RKVDEC_HEVC_CA>; 1525 assigned-clock-rates = <198000000>, <396000000>; 1526 resets = <&cru SRST_A_RKVDEC>, <&cru SRST_H_RKVDEC>, 1527 <&cru SRST_RKVDEC_HEVC_CA>; 1528 reset-names = "video_a", "video_h", "video_hevc_cabac"; 1529 power-domains = <&power RK3562_PD_VDPU>; 1530 iommus = <&rkvdec_mmu>; 1531 rockchip,srv = <&mpp_srv>; 1532 rockchip,taskqueue-node = <0>; 1533 rockchip,resetgroup-node = <0>; 1534 rockchip,task-capacity = <16>; 1535 status = "disabled"; 1536 }; 1537 1538 rkvdec_mmu: iommu@ff340800 { 1539 compatible = "rockchip,iommu-v2"; 1540 reg = <0x0 0xff340800 0x0 0x40>, <0x0 0xff340900 0x0 0x40>; 1541 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1542 interrupt-names = "rkvdec_mmu"; 1543 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_RKVDEC_HEVC_CA>; 1544 clock-names = "aclk", "iface", "clk_hevc_cabac"; 1545 power-domains = <&power RK3562_PD_VDPU>; 1546 rockchip,shootdown-entire; 1547 #iommu-cells = <0>; 1548 status = "disabled"; 1549 }; 1550 1551 rkvenc: rkvenc@ff360000 { 1552 compatible = "rockchip,rkv-encoder-rk3562", "rockchip,rkv-encoder-v2"; 1553 reg = <0x0 0xff360000 0x0 0x6000>; 1554 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1555 interrupt-names = "irq_rkvenc"; 1556 clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>, <&cru CLK_RKVENC_CORE>; 1557 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 1558 rockchip,normal-rates = <297000000>, <0>, <297000000>; 1559 resets = <&cru SRST_A_RKVENC>, <&cru SRST_H_RKVENC>, 1560 <&cru SRST_RKVENC_CORE>; 1561 reset-names = "video_a", "video_h", "video_core"; 1562 assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_RKVENC_CORE>; 1563 assigned-clock-rates = <297000000>, <297000000>; 1564 power-domains = <&power RK3562_PD_VEPU>; 1565 iommus = <&rkvenc_mmu>; 1566 rockchip,srv = <&mpp_srv>; 1567 rockchip,taskqueue-node = <1>; 1568 rockchip,resetgroup-node = <1>; 1569 status = "disabled"; 1570 }; 1571 1572 rkvenc_mmu: iommu@ff36f000 { 1573 compatible = "rockchip,iommu-v2"; 1574 reg = <0x0 0xff36f000 0x0 0x40>; 1575 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1576 interrupt-names = "rkvenc_mmu"; 1577 clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>; 1578 clock-names = "aclk", "iface"; 1579 power-domains = <&power RK3562_PD_VEPU>; 1580 rockchip,shootdown-entire; 1581 #iommu-cells = <0>; 1582 status = "disabled"; 1583 }; 1584 1585 mipi0_csi2_hw: mipi0-csi2-hw@ff380000 { 1586 compatible = "rockchip,rk3562-mipi-csi2-hw"; 1587 reg = <0x0 0xff380000 0x0 0x10000>; 1588 reg-names = "csihost_regs"; 1589 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 1590 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1591 interrupt-names = "csi-intr1", "csi-intr2"; 1592 clocks = <&cru PCLK_CSIHOST0>; 1593 clock-names = "pclk_csi2host"; 1594 resets = <&cru SRST_P_CSIHOST0>; 1595 reset-names = "srst_csihost_p"; 1596 status = "okay"; 1597 }; 1598 1599 mipi1_csi2_hw: mipi1-csi2-hw@ff390000 { 1600 compatible = "rockchip,rk3562-mipi-csi2-hw"; 1601 reg = <0x0 0xff390000 0x0 0x10000>; 1602 reg-names = "csihost_regs"; 1603 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 1604 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1605 interrupt-names = "csi-intr1", "csi-intr2"; 1606 clocks = <&cru PCLK_CSIHOST1>; 1607 clock-names = "pclk_csi2host"; 1608 resets = <&cru SRST_P_CSIHOST1>; 1609 reset-names = "srst_csihost_p"; 1610 status = "okay"; 1611 }; 1612 1613 mipi2_csi2_hw: mipi2-csi2-hw@ff3a0000 { 1614 compatible = "rockchip,rk3562-mipi-csi2-hw"; 1615 reg = <0x0 0xff3a0000 0x0 0x10000>; 1616 reg-names = "csihost_regs"; 1617 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 1618 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1619 interrupt-names = "csi-intr1", "csi-intr2"; 1620 clocks = <&cru PCLK_CSIHOST2>; 1621 clock-names = "pclk_csi2host"; 1622 resets = <&cru SRST_P_CSIHOST2>; 1623 reset-names = "srst_csihost_p"; 1624 status = "okay"; 1625 }; 1626 1627 mipi3_csi2_hw: mipi3-csi2-hw@ff3b0000 { 1628 compatible = "rockchip,rk3562-mipi-csi2-hw"; 1629 reg = <0x0 0xff3b0000 0x0 0x10000>; 1630 reg-names = "csihost_regs"; 1631 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1632 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1633 interrupt-names = "csi-intr1", "csi-intr2"; 1634 clocks = <&cru PCLK_CSIHOST3>; 1635 clock-names = "pclk_csi2host"; 1636 resets = <&cru SRST_P_CSIHOST3>; 1637 reset-names = "srst_csihost_p"; 1638 status = "okay"; 1639 }; 1640 1641 csi2_dphy0_hw: csi2-dphy0-hw@ff3c0000 { 1642 compatible = "rockchip,rk3562-csi2-dphy-hw"; 1643 reg = <0x0 0xff3c0000 0x0 0x10000>; 1644 clocks = <&cru PCLK_CSIPHY0>; 1645 clock-names = "pclk"; 1646 resets = <&cru SRST_P_CSIPHY0>; 1647 reset-names = "srst_p_csiphy0"; 1648 rockchip,grf = <&sys_grf>; 1649 status = "okay"; 1650 }; 1651 1652 csi2_dphy1_hw: csi2-dphy1-hw@ff3d0000 { 1653 compatible = "rockchip,rk3562-csi2-dphy-hw"; 1654 reg = <0x0 0xff3d0000 0x0 0x10000>; 1655 clocks = <&cru PCLK_CSIPHY1>; 1656 clock-names = "pclk"; 1657 resets = <&cru SRST_P_CSIPHY1>; 1658 reset-names = "srst_p_csiphy1"; 1659 rockchip,grf = <&sys_grf>; 1660 status = "okay"; 1661 }; 1662 1663 rkcif: rkcif@ff3e0000 { 1664 compatible = "rockchip,rk3562-cif"; 1665 reg = <0x0 0xff3e0000 0x0 0x800>; 1666 reg-names = "cif_regs"; 1667 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1668 interrupt-names = "cif-intr"; 1669 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, <&cru DCLK_VICAP>, 1670 <&cru CSIRX0_CLK_DATA>, <&cru CSIRX1_CLK_DATA>, 1671 <&cru CSIRX2_CLK_DATA>, <&cru CSIRX3_CLK_DATA>; 1672 clock-names = "aclk_cif", "hclk_cif", "dclk_cif", 1673 "csirx0_data", "csirx1_data", "csirx2_data", 1674 "csirx3_data"; 1675 resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, <&cru SRST_D_VICAP>, 1676 <&cru SRST_I0_VICAP>, <&cru SRST_I1_VICAP>, <&cru SRST_I2_VICAP>, 1677 <&cru SRST_I3_VICAP>; 1678 reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_d", 1679 "rst_cif_i0", "rst_cif_i1", "rst_cif_i2", 1680 "rst_cif_i3"; 1681 power-domains = <&power RK3562_PD_VI>; 1682 rockchip,grf = <&sys_grf>; 1683 iommus = <&rkcif_mmu>; 1684 status = "disabled"; 1685 }; 1686 1687 rkcif_mmu: iommu@ff3e0800 { 1688 compatible = "rockchip,iommu-v2"; 1689 reg = <0x0 0xff3e0800 0x0 0x100>; 1690 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1691 interrupt-names = "cif_mmu"; 1692 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>; 1693 clock-names = "aclk", "iface"; 1694 power-domains = <&power RK3562_PD_VI>; 1695 rockchip,disable-mmu-reset; 1696 #iommu-cells = <0>; 1697 status = "disabled"; 1698 }; 1699 1700 rkisp: isp@ff3f0000 { 1701 compatible = "rockchip,rk3562-rkisp"; 1702 reg = <0x0 0xff3f0000 0x0 0x7f00>; 1703 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1704 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1705 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1706 interrupt-names = "mipi_irq", "mi_irq", "isp_irq"; 1707 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru CLK_ISP>; 1708 clock-names = "aclk_isp", "hclk_isp", "clk_isp_core"; 1709 power-domains = <&power RK3562_PD_VI>; 1710 iommus = <&rkisp_mmu>; 1711 status = "disabled"; 1712 }; 1713 1714 rkisp_mmu: iommu@ff3f7f00 { 1715 compatible = "rockchip,iommu-v2"; 1716 reg = <0x0 0xff3f7f00 0x0 0x100>; 1717 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1718 interrupt-names = "isp_mmu"; 1719 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 1720 clock-names = "aclk", "iface"; 1721 rockchip,disable-mmu-reset; 1722 #iommu-cells = <0>; 1723 power-domains = <&power RK3562_PD_VI>; 1724 status = "disabled"; 1725 }; 1726 1727 vop: vop@ff400000 { 1728 compatible = "rockchip,rk3562-vop"; 1729 reg = <0x0 0xff400000 0x0 0x2000>, <0x0 0xff405000 0x0 0x1000>; 1730 reg-names = "regs", "gamma_lut"; 1731 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 1732 clocks = <&cru ACLK_VOP>, 1733 <&cru HCLK_VOP>, 1734 <&cru DCLK_VOP>; 1735 clock-names = "aclk_vop", 1736 "hclk_vop", 1737 "dclk_vp0"; 1738 resets = <&cru SRST_A_VOP>, 1739 <&cru SRST_H_VOP>, 1740 <&cru SRST_D_VOP>; 1741 reset-names = "axi", 1742 "ahb", 1743 "dclk_vp0"; 1744 iommus = <&vop_mmu>; 1745 power-domains = <&power RK3562_PD_VO>; 1746 rockchip,grf = <&ioc_grf>; 1747 assigned-clocks = <&cru DCLK_VOP>; 1748 assigned-clock-parents = <&cru PLL_VPLL>; 1749 status = "disabled"; 1750 1751 vop_out: ports { 1752 #address-cells = <1>; 1753 #size-cells = <0>; 1754 1755 vp0: port@0 { 1756 #address-cells = <1>; 1757 #size-cells = <0>; 1758 reg = <0>; 1759 1760 vp0_out_rgb: endpoint@0 { 1761 reg = <0>; 1762 remote-endpoint = <&rgb_in_vp0>; 1763 }; 1764 1765 vp0_out_dsi: endpoint@1 { 1766 reg = <1>; 1767 remote-endpoint = <&dsi_in_vp0>; 1768 }; 1769 1770 vp0_out_lvds: endpoint@2 { 1771 reg = <2>; 1772 remote-endpoint = <&lvds_in_vp0>; 1773 }; 1774 }; 1775 }; 1776 }; 1777 1778 vop_mmu: iommu@ff407e00 { 1779 compatible = "rockchip,iommu-v2"; 1780 reg = <0x0 0xff407e00 0x0 0x100>; 1781 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 1782 interrupt-names = "vop_mmu"; 1783 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 1784 clock-names = "aclk", "iface"; 1785 #iommu-cells = <0>; 1786 rockchip,disable-device-link-resume; 1787 rockchip,shootdown-entire; 1788 status = "disabled"; 1789 }; 1790 1791 rga2: rga@ff440000 { 1792 compatible = "rockchip,rga2_core0"; 1793 reg = <0x0 0xff440000 0x0 0x1000>; 1794 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1795 interrupt-names = "rga2_irq"; 1796 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>; 1797 clock-names = "aclk_rga2", "hclk_rga2", "clk_rga2"; 1798 iommus = <&rga2_mmu>; 1799 power-domains = <&power RK3562_PD_RGA>; 1800 status = "disabled"; 1801 }; 1802 1803 rga2_mmu: iommu@ff440f00 { 1804 compatible = "rockchip,iommu-v2"; 1805 reg = <0x0 0xff440f00 0x0 0x100>; 1806 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1807 interrupt-names = "rga2_mmu"; 1808 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>; 1809 clock-names = "aclk", "iface"; 1810 #iommu-cells = <0>; 1811 power-domains = <&power RK3562_PD_RGA>; 1812 status = "disabled"; 1813 }; 1814 1815 jpegd: jpegd@ff450000 { 1816 compatible = "rockchip,rkv-jpeg-decoder-v1"; 1817 reg = <0x0 0xff450000 0x0 0x400>; 1818 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1819 clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>; 1820 clock-names = "aclk_vcodec", "hclk_vcodec"; 1821 rockchip,disable-auto-freq; 1822 resets = <&cru SRST_A_JDEC>, <&cru SRST_H_JDEC>; 1823 reset-names = "video_a", "video_h"; 1824 power-domains = <&power RK3562_PD_RGA>; 1825 iommus = <&jpegd_mmu>; 1826 rockchip,srv = <&mpp_srv>; 1827 rockchip,taskqueue-node = <2>; 1828 rockchip,resetgroup-node = <2>; 1829 status = "disabled"; 1830 }; 1831 1832 jpegd_mmu: iommu@ff450480 { 1833 compatible = "rockchip,iommu-v2"; 1834 reg = <0x0 0xff450480 0x0 0x40>; 1835 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1836 interrupt-names = "jpegd_mmu"; 1837 clock-names = "aclk", "iface"; 1838 clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>; 1839 power-domains = <&power RK3562_PD_RGA>; 1840 rockchip,shootdown-entire; 1841 #iommu-cells = <0>; 1842 status = "disabled"; 1843 }; 1844 1845 dfi: dfi@ff4c0000 { 1846 reg = <0x00 0xff4c0000 0x00 0x400>; 1847 compatible = "rockchip,rk3562-dfi"; 1848 rockchip,pmugrf = <&pmu_grf>; 1849 status = "disabled"; 1850 }; 1851 1852 pcie2x1: pcie@ff500000 { 1853 compatible = "rockchip,rk3562-pcie", "snps,dw-pcie"; 1854 #address-cells = <3>; 1855 #size-cells = <2>; 1856 bus-range = <0x0 0xff>; 1857 clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, 1858 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, 1859 <&cru CLK_PCIE20_AUX>; 1860 clock-names = "aclk_mst", "aclk_slv", 1861 "aclk_dbi", "pclk", "aux"; 1862 device_type = "pci"; 1863 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1869 interrupt-names = "msi", "pmc", "sys", "legacy", "msg", "err"; 1870 #interrupt-cells = <1>; 1871 interrupt-map-mask = <0 0 0 7>; 1872 interrupt-map = <0 0 0 1 &pcie2x1_intc 0>, 1873 <0 0 0 2 &pcie2x1_intc 1>, 1874 <0 0 0 3 &pcie2x1_intc 2>, 1875 <0 0 0 4 &pcie2x1_intc 3>; 1876 linux,pci-domain = <0>; 1877 num-ib-windows = <8>; 1878 num-viewport = <8>; 1879 num-ob-windows = <2>; 1880 max-link-speed = <2>; 1881 num-lanes = <1>; 1882 phys = <&combphy_pu PHY_TYPE_PCIE>; 1883 phy-names = "pcie-phy"; 1884 power-domains = <&power RK3562_PD_PHP>; 1885 ranges = <0x00000800 0x0 0xfc000000 0x0 0xfc000000 0x0 0x100000 1886 0x81000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000 1887 0x82000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000 1888 0xc3000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>; 1889 reg = <0x0 0xfe000000 0x0 0x400000>, 1890 <0x0 0xff500000 0x0 0x10000>; 1891 reg-names = "pcie-dbi", "pcie-apb"; 1892 resets = <&cru SRST_PCIE20_POWERUP>; 1893 reset-names = "pipe"; 1894 status = "disabled"; 1895 1896 pcie2x1_intc: legacy-interrupt-controller { 1897 interrupt-controller; 1898 #address-cells = <0>; 1899 #interrupt-cells = <1>; 1900 interrupt-parent = <&gic>; 1901 }; 1902 }; 1903 1904 spi1: spi@ff640000 { 1905 compatible = "rockchip,rk3066-spi"; 1906 reg = <0x0 0xff640000 0x0 0x1000>; 1907 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1908 #address-cells = <1>; 1909 #size-cells = <0>; 1910 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>, <&cru SCLK_IN_SPI1>; 1911 clock-names = "spiclk", "apb_pclk", "sclk_in"; 1912 dmas = <&dmac 15>, <&dmac 14>; 1913 dma-names = "tx", "rx"; 1914 pinctrl-names = "default"; 1915 pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>; 1916 num-cs = <2>; 1917 status = "disabled"; 1918 }; 1919 1920 spi2: spi@ff650000 { 1921 compatible = "rockchip,rk3066-spi"; 1922 reg = <0x0 0xff650000 0x0 0x1000>; 1923 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1924 #address-cells = <1>; 1925 #size-cells = <0>; 1926 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>, <&cru SCLK_IN_SPI2>; 1927 clock-names = "spiclk", "apb_pclk", "sclk_in"; 1928 dmas = <&dmac 17>, <&dmac 16>; 1929 dma-names = "tx", "rx"; 1930 pinctrl-names = "default"; 1931 pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>; 1932 num-cs = <2>; 1933 status = "disabled"; 1934 }; 1935 1936 uart1: serial@ff670000 { 1937 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 1938 reg = <0x0 0xff670000 0x0 0x100>; 1939 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1940 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1941 clock-names = "baudclk", "apb_pclk"; 1942 reg-shift = <2>; 1943 reg-io-width = <4>; 1944 dmas = <&dmac 10>, <&dmac 1>; /* tx:10 rx:1 */ 1945 status = "disabled"; 1946 }; 1947 1948 uart2: serial@ff680000 { 1949 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 1950 reg = <0x0 0xff680000 0x0 0x100>; 1951 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1952 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1953 clock-names = "baudclk", "apb_pclk"; 1954 reg-shift = <2>; 1955 reg-io-width = <4>; 1956 dmas = <&dmac 2>; /* rx:2 */ 1957 status = "disabled"; 1958 }; 1959 1960 uart3: serial@ff690000 { 1961 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 1962 reg = <0x0 0xff690000 0x0 0x100>; 1963 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1964 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1965 clock-names = "baudclk", "apb_pclk"; 1966 reg-shift = <2>; 1967 reg-io-width = <4>; 1968 dmas = <&dmac 3>; /* rx:3 */ 1969 status = "disabled"; 1970 }; 1971 1972 uart4: serial@ff6a0000 { 1973 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 1974 reg = <0x0 0xff6a0000 0x0 0x100>; 1975 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1976 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1977 clock-names = "baudclk", "apb_pclk"; 1978 reg-shift = <2>; 1979 reg-io-width = <4>; 1980 dmas = <&dmac 4>; /* rx:4 */ 1981 status = "disabled"; 1982 }; 1983 1984 uart5: serial@ff6b0000 { 1985 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 1986 reg = <0x0 0xff6b0000 0x0 0x100>; 1987 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1988 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1989 clock-names = "baudclk", "apb_pclk"; 1990 reg-shift = <2>; 1991 reg-io-width = <4>; 1992 dmas = <&dmac 11>, <&dmac 5>; /* tx:11 rx:5 */ 1993 status = "disabled"; 1994 }; 1995 1996 uart6: serial@ff6c0000 { 1997 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 1998 reg = <0x0 0xff6c0000 0x0 0x100>; 1999 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 2000 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 2001 clock-names = "baudclk", "apb_pclk"; 2002 reg-shift = <2>; 2003 reg-io-width = <4>; 2004 dmas = <&dmac 6>; /* rx:6 */ 2005 status = "disabled"; 2006 }; 2007 2008 uart7: serial@ff6d0000 { 2009 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 2010 reg = <0x0 0xff6d0000 0x0 0x100>; 2011 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 2012 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 2013 clock-names = "baudclk", "apb_pclk"; 2014 reg-shift = <2>; 2015 reg-io-width = <4>; 2016 dmas = <&dmac 7>; /* rx:7 */ 2017 status = "disabled"; 2018 }; 2019 2020 uart8: serial@ff6e0000 { 2021 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 2022 reg = <0x0 0xff6e0000 0x0 0x100>; 2023 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 2024 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 2025 clock-names = "baudclk", "apb_pclk"; 2026 reg-shift = <2>; 2027 reg-io-width = <4>; 2028 dmas = <&dmac 8>; /* rx:8 */ 2029 status = "disabled"; 2030 }; 2031 2032 uart9: serial@ff6f0000 { 2033 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 2034 reg = <0x0 0xff6f0000 0x0 0x100>; 2035 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 2036 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 2037 clock-names = "baudclk", "apb_pclk"; 2038 reg-shift = <2>; 2039 reg-io-width = <4>; 2040 dmas = <&dmac 9>; /* rx:9 */ 2041 status = "disabled"; 2042 }; 2043 2044 pwm4: pwm@ff700000 { 2045 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 2046 reg = <0x0 0xff700000 0x0 0x10>; 2047 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 2048 #pwm-cells = <3>; 2049 pinctrl-names = "active"; 2050 pinctrl-0 = <&pwm4m0_pins>; 2051 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; 2052 clock-names = "pwm", "pclk"; 2053 status = "disabled"; 2054 }; 2055 2056 pwm5: pwm@ff700010 { 2057 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 2058 reg = <0x0 0xff700010 0x0 0x10>; 2059 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 2060 #pwm-cells = <3>; 2061 pinctrl-names = "active"; 2062 pinctrl-0 = <&pwm5m0_pins>; 2063 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; 2064 clock-names = "pwm", "pclk"; 2065 status = "disabled"; 2066 }; 2067 2068 pwm6: pwm@ff700020 { 2069 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 2070 reg = <0x0 0xff700020 0x0 0x10>; 2071 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 2072 #pwm-cells = <3>; 2073 pinctrl-names = "active"; 2074 pinctrl-0 = <&pwm6m0_pins>; 2075 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; 2076 clock-names = "pwm", "pclk"; 2077 status = "disabled"; 2078 }; 2079 2080 pwm7: pwm@ff700030 { 2081 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 2082 reg = <0x0 0xff700030 0x0 0x10>; 2083 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 2084 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 2085 #pwm-cells = <3>; 2086 pinctrl-names = "active"; 2087 pinctrl-0 = <&pwm7m0_pins>; 2088 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; 2089 clock-names = "pwm", "pclk"; 2090 status = "disabled"; 2091 }; 2092 2093 pwm8: pwm@ff710000 { 2094 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 2095 reg = <0x0 0xff710000 0x0 0x10>; 2096 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 2097 #pwm-cells = <3>; 2098 pinctrl-names = "active"; 2099 pinctrl-0 = <&pwm8m0_pins>; 2100 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; 2101 clock-names = "pwm", "pclk"; 2102 status = "disabled"; 2103 }; 2104 2105 pwm9: pwm@ff710010 { 2106 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 2107 reg = <0x0 0xff710010 0x0 0x10>; 2108 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 2109 #pwm-cells = <3>; 2110 pinctrl-names = "active"; 2111 pinctrl-0 = <&pwm9m0_pins>; 2112 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; 2113 clock-names = "pwm", "pclk"; 2114 status = "disabled"; 2115 }; 2116 2117 pwm10: pwm@ff710020 { 2118 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 2119 reg = <0x0 0xff710020 0x0 0x10>; 2120 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 2121 #pwm-cells = <3>; 2122 pinctrl-names = "active"; 2123 pinctrl-0 = <&pwm10m0_pins>; 2124 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; 2125 clock-names = "pwm", "pclk"; 2126 status = "disabled"; 2127 }; 2128 2129 pwm11: pwm@ff710030 { 2130 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 2131 reg = <0x0 0xff710030 0x0 0x10>; 2132 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 2133 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 2134 #pwm-cells = <3>; 2135 pinctrl-names = "active"; 2136 pinctrl-0 = <&pwm11m0_pins>; 2137 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; 2138 clock-names = "pwm", "pclk"; 2139 status = "disabled"; 2140 }; 2141 2142 pwm12: pwm@ff720000 { 2143 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 2144 reg = <0x0 0xff720000 0x0 0x10>; 2145 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 2146 #pwm-cells = <3>; 2147 pinctrl-names = "active"; 2148 pinctrl-0 = <&pwm12m0_pins>; 2149 clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; 2150 clock-names = "pwm", "pclk"; 2151 status = "disabled"; 2152 }; 2153 2154 pwm13: pwm@ff720010 { 2155 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 2156 reg = <0x0 0xff720010 0x0 0x10>; 2157 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 2158 #pwm-cells = <3>; 2159 pinctrl-names = "active"; 2160 pinctrl-0 = <&pwm13m0_pins>; 2161 clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; 2162 clock-names = "pwm", "pclk"; 2163 status = "disabled"; 2164 }; 2165 2166 pwm14: pwm@ff720020 { 2167 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 2168 reg = <0x0 0xff720020 0x0 0x10>; 2169 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 2170 #pwm-cells = <3>; 2171 pinctrl-names = "active"; 2172 pinctrl-0 = <&pwm14m0_pins>; 2173 clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; 2174 clock-names = "pwm", "pclk"; 2175 status = "disabled"; 2176 }; 2177 2178 pwm15: pwm@ff720030 { 2179 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 2180 reg = <0x0 0xff720030 0x0 0x10>; 2181 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 2182 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 2183 #pwm-cells = <3>; 2184 pinctrl-names = "active"; 2185 pinctrl-0 = <&pwm15m0_pins>; 2186 clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; 2187 clock-names = "pwm", "pclk"; 2188 status = "disabled"; 2189 }; 2190 2191 saradc0: saradc@ff730000 { 2192 compatible = "rockchip,rk3562-saradc"; 2193 reg = <0x0 0xff730000 0x0 0x100>; 2194 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 2195 #io-channel-cells = <1>; 2196 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 2197 clock-names = "saradc", "apb_pclk"; 2198 resets = <&cru SRST_P_SARADC>; 2199 reset-names = "saradc-apb"; 2200 status = "disabled"; 2201 }; 2202 2203 u2phy: usb2-phy@ff740000 { 2204 compatible = "rockchip,rk3562-usb2phy"; 2205 reg = <0x0 0xff740000 0x0 0x10000>; 2206 clocks = <&cru CLK_USB2PHY_REF>, <&cru PCLK_USB2PHY>; 2207 clock-names = "phyclk", "pclk"; 2208 #clock-cells = <0>; 2209 clock-output-names = "usb480m_phy"; 2210 rockchip,usbgrf = <&usbphy_grf>; 2211 status = "disabled"; 2212 2213 u2phy_otg: otg-port { 2214 #phy-cells = <0>; 2215 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 2216 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 2217 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2218 interrupt-names = "otg-bvalid", "otg-id", "linestate"; 2219 status = "disabled"; 2220 }; 2221 2222 u2phy_host: host-port { 2223 #phy-cells = <0>; 2224 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 2225 interrupt-names = "linestate"; 2226 status = "disabled"; 2227 }; 2228 }; 2229 2230 combphy_pu: phy@ff750000 { 2231 compatible = "rockchip,rk3562-naneng-combphy"; 2232 reg = <0x0 0xff750000 0x0 0x100>; 2233 #phy-cells = <1>; 2234 clocks = <&cru CLK_PIPEPHY_REF>, <&cru PCLK_PIPEPHY>, 2235 <&cru PCLK_PHP>; 2236 clock-names = "refclk", "apbclk", "pipe_clk"; 2237 assigned-clocks = <&cru CLK_PIPEPHY_REF>; 2238 assigned-clock-rates = <100000000>; 2239 resets = <&cru SRST_P_PIPEPHY>, <&cru SRST_PIPEPHY>; 2240 reset-names = "combphy-apb", "combphy"; 2241 rockchip,pipe-grf = <&peri_grf>; 2242 rockchip,pipe-phy-grf = <&pipephy_grf>; 2243 status = "disabled"; 2244 }; 2245 2246 sai0: sai@ff800000 { 2247 compatible = "rockchip,rk3562-sai", "rockchip,sai-v1"; 2248 reg = <0x0 0xff800000 0x0 0x1000>; 2249 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 2250 clocks = <&cru MCLK_SAI0>, <&cru HCLK_SAI0>; 2251 clock-names = "mclk", "hclk"; 2252 assigned-clocks = <&cru CLK_SAI0_SRC>; 2253 assigned-clock-parents = <&cru PLL_HPLL>; 2254 dmas = <&dmac 19>, <&dmac 18>; 2255 dma-names = "tx", "rx"; 2256 resets = <&cru SRST_M_SAI0_8CH>, <&cru SRST_H_SAI0_8CH>; 2257 reset-names = "m", "h"; 2258 pinctrl-names = "default"; 2259 pinctrl-0 = <&i2s0m0_lrck 2260 &i2s0m0_sclk 2261 &i2s0m0_sdi0 2262 &i2s0m0_sdo0 2263 &i2s0m0_sdo1 2264 &i2s0m0_sdo2 2265 &i2s0m0_sdo3>; 2266 #sound-dai-cells = <0>; 2267 status = "disabled"; 2268 }; 2269 2270 sai1: sai@ff810000 { 2271 compatible = "rockchip,rk3562-sai", "rockchip,sai-v1"; 2272 reg = <0x0 0xff810000 0x0 0x1000>; 2273 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 2274 clocks = <&cru MCLK_SAI1>, <&cru HCLK_SAI1>; 2275 clock-names = "mclk", "hclk"; 2276 assigned-clocks = <&cru CLK_SAI1_SRC>; 2277 assigned-clock-parents = <&cru PLL_HPLL>; 2278 dmas = <&dmac 21>, <&dmac 20>; 2279 dma-names = "tx", "rx"; 2280 resets = <&cru SRST_M_SAI1_8CH>, <&cru SRST_H_SAI1_8CH>; 2281 reset-names = "m", "h"; 2282 pinctrl-names = "default"; 2283 pinctrl-0 = <&i2s1m0_lrck 2284 &i2s1m0_sclk 2285 &i2s1m0_sdi0 2286 &i2s1m0_sdi1 2287 &i2s1m0_sdi2 2288 &i2s1m0_sdi3 2289 &i2s1m0_sdo0 2290 &i2s1m0_sdo1 2291 &i2s1m0_sdo2 2292 &i2s1m0_sdo3>; 2293 #sound-dai-cells = <0>; 2294 status = "disabled"; 2295 }; 2296 2297 sai2: sai@ff820000 { 2298 compatible = "rockchip,rk3562-sai", "rockchip,sai-v1"; 2299 reg = <0x0 0xff820000 0x0 0x1000>; 2300 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 2301 clocks = <&cru MCLK_SAI2>, <&cru HCLK_SAI2>; 2302 clock-names = "mclk", "hclk"; 2303 assigned-clocks = <&cru CLK_SAI2_SRC>; 2304 assigned-clock-parents = <&cru PLL_HPLL>; 2305 dmas = <&dmac 23>, <&dmac 22>; 2306 dma-names = "tx", "rx"; 2307 resets = <&cru SRST_M_SAI2_2CH>, <&cru SRST_H_SAI2_2CH>; 2308 reset-names = "m", "h"; 2309 pinctrl-names = "default"; 2310 pinctrl-0 = <&i2s2m0_lrck 2311 &i2s2m0_sclk 2312 &i2s2m0_sdi 2313 &i2s2m0_sdo>; 2314 #sound-dai-cells = <0>; 2315 status = "disabled"; 2316 }; 2317 2318 pdm: pdm@ff830000 { 2319 compatible = "rockchip,rk3562-pdm", "rockchip,rv1126-pdm"; 2320 reg = <0x0 0xff830000 0x0 0x1000>; 2321 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; 2322 clock-names = "pdm_clk", "pdm_hclk"; 2323 assigned-clocks = <&cru MCLK_PDM>; 2324 assigned-clock-parents = <&cru PLL_HPLL>; 2325 dmas = <&dmac 31>; 2326 dma-names = "rx"; 2327 pinctrl-names = "default"; 2328 pinctrl-0 = <&pdmm0_clk0 2329 &pdmm0_clk1 2330 &pdmm0_sdi0 2331 &pdmm0_sdi1 2332 &pdmm0_sdi2 2333 &pdmm0_sdi3>; 2334 #sound-dai-cells = <0>; 2335 status = "disabled"; 2336 }; 2337 2338 spdif_8ch: spdif@ff840000 { 2339 compatible = "rockchip,rk3562-spdif", "rockchip,rk3568-spdif"; 2340 reg = <0x0 0xff840000 0x0 0x1000>; 2341 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 2342 dmas = <&dmac 30>; 2343 dma-names = "tx"; 2344 clock-names = "mclk", "hclk"; 2345 clocks = <&cru MCLK_SPDIF>, <&cru HCLK_SPDIF>; 2346 assigned-clocks = <&cru CLK_SPDIF_SRC>; 2347 assigned-clock-parents = <&cru PLL_HPLL>; 2348 #sound-dai-cells = <0>; 2349 pinctrl-names = "default"; 2350 pinctrl-0 = <&spdifm0_pins>; 2351 status = "disabled"; 2352 }; 2353 2354 dsm: dsm@ff850000 { 2355 compatible = "rockchip,rk3562-dsm"; 2356 reg = <0x0 0xff850000 0x0 0x1000>; 2357 clocks = <&cru CLK_DSM>, <&cru HCLK_DSM>; 2358 clock-names = "dac", "pclk"; 2359 resets = <&cru SRST_DSM>; 2360 reset-names = "reset" ; 2361 rockchip,grf = <&peri_grf>; 2362 pinctrl-names = "default"; 2363 pinctrl-0 = <&dsm_pins>; 2364 #sound-dai-cells = <0>; 2365 status = "disabled"; 2366 }; 2367 2368 sfc: spi@ff860000 { 2369 compatible = "rockchip,sfc"; 2370 reg = <0x0 0xff860000 0x0 0x10000>; 2371 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 2372 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 2373 clock-names = "clk_sfc", "hclk_sfc"; 2374 assigned-clocks = <&cru SCLK_SFC>; 2375 assigned-clock-rates = <100000000>; 2376 #address-cells = <1>; 2377 #size-cells = <0>; 2378 status = "disabled"; 2379 }; 2380 2381 sdhci: mmc@ff870000 { 2382 compatible = "rockchip,rk3562-dwcmshc", "rockchip,rk3528-dwcmshc"; 2383 reg = <0x0 0xff870000 0x0 0x10000>; 2384 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 2385 assigned-clocks = <&cru BCLK_EMMC>, <&cru CCLK_EMMC>; 2386 assigned-clock-rates = <200000000>, <200000000>; 2387 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 2388 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 2389 <&cru TMCLK_EMMC>; 2390 clock-names = "core", "bus", "axi", "block", "timer"; 2391 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 2392 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 2393 <&cru SRST_T_EMMC>; 2394 reset-names = "core", "bus", "axi", "block", "timer"; 2395 max-frequency = <200000000>; 2396 status = "disabled"; 2397 }; 2398 2399 sdmmc0: mmc@ff880000 { 2400 compatible = "rockchip,rk3562-dw-mshc", 2401 "rockchip,rk3288-dw-mshc"; 2402 reg = <0x0 0xff880000 0x0 0x10000>; 2403 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 2404 max-frequency = <200000000>; 2405 clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SDMMC0>, 2406 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; 2407 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 2408 resets = <&cru SRST_H_SDMMC0>; 2409 reset-names = "reset"; 2410 fifo-depth = <0x100>; 2411 status = "disabled"; 2412 }; 2413 2414 sdmmc1: mmc@ff890000 { 2415 compatible = "rockchip,rk3562-dw-mshc", 2416 "rockchip,rk3288-dw-mshc"; 2417 reg = <0x0 0xff890000 0x0 0x10000>; 2418 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 2419 max-frequency = <200000000>; 2420 clocks = <&cru HCLK_SDMMC1>, <&cru CCLK_SDMMC1>, 2421 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; 2422 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 2423 resets = <&cru SRST_H_SDMMC1>; 2424 reset-names = "reset"; 2425 fifo-depth = <0x100>; 2426 status = "disabled"; 2427 }; 2428 2429 crypto: crypto@ff8a0000 { 2430 compatible = "rockchip,crypto-v4"; 2431 reg = <0x0 0xff8a0000 0x0 0x2000>; 2432 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2433 clocks = <&scmi_clk ACLK_CRYPTO>, <&scmi_clk HCLK_CRYPTO>, 2434 <&scmi_clk CLK_CORE_CRYPTO>, <&scmi_clk CLK_PKA_CRYPTO>, 2435 <&scmi_clk PCLK_CRYPTO>; 2436 clock-names = "aclk", "hclk", "sclk", "pka", "pclk"; 2437 assigned-clocks = <&scmi_clk CLK_CORE_CRYPTO>, <&scmi_clk CLK_PKA_CRYPTO>; 2438 assigned-clock-rates = <200000000>, <300000000>; 2439 resets = <&cru SRST_CORE_CRYPTO>; 2440 reset-names = "crypto-rst"; 2441 status = "disabled"; 2442 }; 2443 2444 rng: rng@ff8e0000 { 2445 compatible = "rockchip,rkrng"; 2446 reg = <0x0 0xff8e0000 0x0 0x200>; 2447 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 2448 clocks = <&scmi_clk HCLK_RK_RNG_NS>; 2449 clock-names = "hclk_trng"; 2450 resets = <&cru SRST_H_RK_RNG_NS>; 2451 reset-names = "reset"; 2452 status = "disabled"; 2453 }; 2454 2455 otp: otp@ff930000 { 2456 compatible = "rockchip,rk3562-otp"; 2457 reg = <0x0 0xff930000 0x0 0x4000>; 2458 #address-cells = <1>; 2459 #size-cells = <1>; 2460 clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>, 2461 <&cru PCLK_OTPC_NS>, <&cru CLK_OTPC_ARB>, 2462 <&cru PCLK_OTPPHY>; 2463 clock-names = "usr", "sbpi", "apb", "arb", "phy"; 2464 resets = <&cru SRST_USER_OTPC_NS>, <&cru SRST_SBPI_OTPC_NS>, 2465 <&cru SRST_P_OTPC_NS>, <&cru SRST_OTPC_ARB>, 2466 <&cru SRST_P_OTPPHY>; 2467 reset-names = "usr", "sbpi", "apb", "arb", "phy"; 2468 2469 /* Data cells */ 2470 cpu_code: cpu-code@2 { 2471 reg = <0x02 0x2>; 2472 }; 2473 otp_cpu_version: cpu-version@8 { 2474 reg = <0x08 0x1>; 2475 bits = <3 3>; 2476 }; 2477 mbist_vmin: mbist-vmin@9 { 2478 reg = <0x09 0x1>; 2479 bits = <0 2>; 2480 }; 2481 log_mbist_vmin: log-mbist-vmin@9 { 2482 reg = <0x09 0x1>; 2483 bits = <4 2>; 2484 }; 2485 otp_id: id@a { 2486 reg = <0x0a 0x10>; 2487 }; 2488 cpu_leakage: cpu-leakage@1a { 2489 reg = <0x1a 0x1>; 2490 }; 2491 log_leakage: log-leakage@1b { 2492 reg = <0x1b 0x1>; 2493 }; 2494 npu_leakage: npu-leakage@1c { 2495 reg = <0x1c 0x1>; 2496 }; 2497 gpu_leakage: gpu-leakage@1d { 2498 reg = <0x1d 0x1>; 2499 }; 2500 cpu_tsadc_trim_l: cpu-tsadc-trim-l@2a { 2501 reg = <0x2a 0x1>; 2502 }; 2503 cpu_tsadc_trim_h: cpu-tsadc-trim-h@2b { 2504 reg = <0x2b 0x1>; 2505 }; 2506 tsadc_trim_base_frac: tsadc-trim-base-frac@2c { 2507 reg = <0x2c 0x1>; 2508 bits = <4 4>; 2509 }; 2510 tsadc_trim_base: tsadc-trim-base@2d { 2511 reg = <0x2d 0x1>; 2512 }; 2513 cpu_opp_info: cpu-opp-info@2e { 2514 reg = <0x2e 0x6>; 2515 }; 2516 gpu_opp_info: gpu-opp-info@34 { 2517 reg = <0x34 0x6>; 2518 }; 2519 npu_opp_info: npu-opp-info@3a { 2520 reg = <0x3a 0x6>; 2521 }; 2522 dmc_opp_info: dmc-opp-info@40 { 2523 reg = <0x40 0x6>; 2524 }; 2525 cpu_pvtpll: cpu-pvtpll@46 { 2526 reg = <0x46 0x2>; 2527 }; 2528 gpu_pvtpll: gpu-pvtpll@48 { 2529 reg = <0x48 0x2>; 2530 }; 2531 npu_pvtpll: npu-pvtpll@4a { 2532 reg = <0x4a 0x2>; 2533 }; 2534 }; 2535 2536 dmac: dma-controller@ff990000 { 2537 compatible = "arm,pl330", "arm,primecell"; 2538 reg = <0x0 0xff990000 0x0 0x4000>; 2539 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2540 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 2541 clocks = <&cru ACLK_DMAC>; 2542 clock-names = "apb_pclk"; 2543 #dma-cells = <1>; 2544 arm,pl330-periph-burst; 2545 }; 2546 2547 rkdmac: dma-controller@ff9a0000 { 2548 compatible = "rockchip,rk3562-dma", "rockchip,dma-v1"; 2549 reg = <0x0 0xff9a0000 0x0 0x4000>; 2550 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2551 clocks = <&cru ACLK_RKDMAC>; 2552 clock-names = "aclk"; 2553 #dma-cells = <1>; 2554 dma-channels = <42>; 2555 dma-requests = <42>; 2556 rockchip,grf = <&peri_grf>; 2557 }; 2558 2559 hwlock: hwspinlock@ff9e0000 { 2560 compatible = "rockchip,hwspinlock"; 2561 reg = <0x0 0xff9e0000 0x0 0x100>; 2562 #hwlock-cells = <1>; 2563 status = "disabled"; 2564 }; 2565 2566 i2c1: i2c@ffa00000 { 2567 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; 2568 reg = <0x0 0xffa00000 0x0 0x1000>; 2569 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 2570 clock-names = "i2c", "pclk"; 2571 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2572 pinctrl-names = "default"; 2573 pinctrl-0 = <&i2c1m0_xfer>; 2574 #address-cells = <1>; 2575 #size-cells = <0>; 2576 status = "disabled"; 2577 }; 2578 2579 i2c2: i2c@ffa10000 { 2580 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; 2581 reg = <0x0 0xffa10000 0x0 0x1000>; 2582 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 2583 clock-names = "i2c", "pclk"; 2584 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2585 pinctrl-names = "default"; 2586 pinctrl-0 = <&i2c2m0_xfer>; 2587 #address-cells = <1>; 2588 #size-cells = <0>; 2589 status = "disabled"; 2590 }; 2591 2592 i2c3: i2c@ffa20000 { 2593 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; 2594 reg = <0x0 0xffa20000 0x0 0x1000>; 2595 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 2596 clock-names = "i2c", "pclk"; 2597 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 2598 pinctrl-names = "default"; 2599 pinctrl-0 = <&i2c3m0_xfer>; 2600 #address-cells = <1>; 2601 #size-cells = <0>; 2602 status = "disabled"; 2603 }; 2604 2605 i2c4: i2c@ffa30000 { 2606 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; 2607 reg = <0x0 0xffa30000 0x0 0x1000>; 2608 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 2609 clock-names = "i2c", "pclk"; 2610 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 2611 pinctrl-names = "default"; 2612 pinctrl-0 = <&i2c4m0_xfer>; 2613 #address-cells = <1>; 2614 #size-cells = <0>; 2615 status = "disabled"; 2616 }; 2617 2618 i2c5: i2c@ffa40000 { 2619 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; 2620 reg = <0x0 0xffa40000 0x0 0x1000>; 2621 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 2622 clock-names = "i2c", "pclk"; 2623 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 2624 pinctrl-names = "default"; 2625 pinctrl-0 = <&i2c5m0_xfer>; 2626 #address-cells = <1>; 2627 #size-cells = <0>; 2628 status = "disabled"; 2629 }; 2630 2631 rktimer: timer@ffa50000 { 2632 compatible = "rockchip,rk3562-timer", "rockchip,rk3288-timer"; 2633 reg = <0x0 0xffa50000 0x0 0x20>; 2634 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2635 clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>; 2636 clock-names = "pclk", "timer"; 2637 }; 2638 2639 wdt: watchdog@ffa60000 { 2640 compatible = "snps,dw-wdt"; 2641 reg = <0x0 0xffa60000 0x0 0x100>; 2642 clocks = <&cru CLK_WDTNS>, <&cru PCLK_WDTNS>; 2643 clock-names = "tclk", "pclk"; 2644 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2645 status = "disabled"; 2646 }; 2647 2648 tsadc: tsadc@ffa70000 { 2649 compatible = "rockchip,rk3562-tsadc"; 2650 reg = <0x0 0xffa70000 0x0 0x400>; 2651 rockchip,grf = <&sys_grf>; 2652 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2653 clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>, <&cru PCLK_TSADC>; 2654 clock-names = "tsadc", "tsadc_tsen", "apb_pclk"; 2655 assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>; 2656 assigned-clock-rates = <1200000>, <12000000>; 2657 resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>, <&cru SRST_TSADCPHY>; 2658 reset-names = "tsadc", "tsadc-apb", "tsadc-phy"; 2659 #thermal-sensor-cells = <1>; 2660 rockchip,hw-tshut-temp = <120000>; 2661 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 2662 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 2663 nvmem-cells = <&cpu_tsadc_trim_l>, <&cpu_tsadc_trim_h>, <&tsadc_trim_base>, <&tsadc_trim_base_frac>; 2664 nvmem-cell-names = "trim_l", "trim_h", "trim_base", "trim_base_frac"; 2665 status = "disabled"; 2666 }; 2667 2668 gmac0: ethernet@ffa80000 { 2669 compatible = "rockchip,rk3562-gmac", "snps,dwmac-4.20a"; 2670 reg = <0x0 0xffa80000 0x0 0x10000>; 2671 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 2672 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 2673 interrupt-names = "macirq", "eth_wake_irq"; 2674 rockchip,grf = <&sys_grf>; 2675 rockchip,php_grf = <&ioc_grf>; 2676 clocks = <&cru CLK_GMAC_125M_CRU_I>, <&cru CLK_GMAC_50M_CRU_I>, 2677 <&cru PCLK_GMAC>, <&cru ACLK_GMAC>; 2678 clock-names = "stmmaceth", "clk_mac_ref", 2679 "pclk_mac", "aclk_mac"; 2680 resets = <&cru SRST_A_GMAC>; 2681 reset-names = "stmmaceth"; 2682 2683 snps,mixed-burst; 2684 snps,tso; 2685 2686 snps,axi-config = <&gmac0_stmmac_axi_setup>; 2687 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 2688 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 2689 status = "disabled"; 2690 2691 mdio0: mdio { 2692 compatible = "snps,dwmac-mdio"; 2693 #address-cells = <0x1>; 2694 #size-cells = <0x0>; 2695 }; 2696 2697 gmac0_stmmac_axi_setup: stmmac-axi-config { 2698 snps,wr_osr_lmt = <4>; 2699 snps,rd_osr_lmt = <8>; 2700 snps,blen = <0 0 0 0 16 8 4>; 2701 }; 2702 2703 gmac0_mtl_rx_setup: rx-queues-config { 2704 snps,rx-queues-to-use = <1>; 2705 queue0 {}; 2706 }; 2707 2708 gmac0_mtl_tx_setup: tx-queues-config { 2709 snps,tx-queues-to-use = <1>; 2710 queue0 {}; 2711 }; 2712 }; 2713 2714 saradc1: saradc@ffaa0000 { 2715 compatible = "rockchip,rk3562-saradc"; 2716 reg = <0x0 0xffaa0000 0x0 0x100>; 2717 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 2718 #io-channel-cells = <1>; 2719 clocks = <&cru CLK_SARADC_VCCIO156>, <&cru PCLK_SARADC_VCCIO156>; 2720 clock-names = "saradc", "apb_pclk"; 2721 resets = <&cru SRST_P_SARADC_VCCIO156>; 2722 reset-names = "saradc-apb"; 2723 status = "disabled"; 2724 }; 2725 2726 mailbox: mailbox@ffae0000 { 2727 compatible = "rockchip,rk3562-mailbox", 2728 "rockchip,rk3368-mailbox"; 2729 reg = <0x0 0xffae0000 0x0 0x200>; 2730 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 2731 clocks = <&cru PCLK_MAILBOX>; 2732 clock-names = "pclk_mailbox"; 2733 #mbox-cells = <1>; 2734 status = "disabled"; 2735 }; 2736 2737 dsi: dsi@ffb10000 { 2738 compatible = "rockchip,rk3562-mipi-dsi"; 2739 reg = <0x0 0xffb10000 0x0 0x10000>; 2740 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 2741 clocks = <&cru PCLK_DSITX>; 2742 clock-names = "pclk"; 2743 resets = <&cru SRST_P_DSITX>; 2744 reset-names = "apb"; 2745 phys = <&video_phy>; 2746 phy-names = "dphy"; 2747 rockchip,grf = <&sys_grf>; 2748 #address-cells = <1>; 2749 #size-cells = <0>; 2750 status = "disabled"; 2751 2752 ports { 2753 #address-cells = <1>; 2754 #size-cells = <0>; 2755 2756 dsi_in: port@0 { 2757 reg = <0>; 2758 #address-cells = <1>; 2759 #size-cells = <0>; 2760 2761 dsi_in_vp0: endpoint@0 { 2762 reg = <0>; 2763 remote-endpoint = <&vp0_out_dsi>; 2764 status = "disabled"; 2765 }; 2766 }; 2767 }; 2768 }; 2769 2770 video_phy: phy@ffb20000 { 2771 compatible = "rockchip,rk3562-dsi-dphy", "rockchip,rk3562-video-phy", 2772 "rockchip,rk3568-dsi-dphy", "rockchip,rk3568-video-phy"; 2773 reg = <0x0 0xffb20000 0x0 0x10000>, 2774 <0x0 0xffb10000 0x0 0x10000>; 2775 reg-names = "phy", "host"; 2776 clocks = <&cru CLK_MIPIDSIPHY_REF>, 2777 <&cru PCLK_DSIPHY>, <&cru PCLK_DSITX>; 2778 clock-names = "ref", "pclk", "pclk_host"; 2779 #clock-cells = <0>; 2780 resets = <&cru SRST_P_DSIPHY>; 2781 reset-names = "apb"; 2782 #phy-cells = <0>; 2783 status = "disabled"; 2784 }; 2785 2786 gmac1: ethernet@ffb30000 { 2787 compatible = "rockchip,rk3562-gmac"; 2788 reg = <0x0 0xffb30000 0x0 0x10000>; 2789 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 2790 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 2791 interrupt-names = "macirq", "eth_wake_irq"; 2792 rockchip,grf = <&sys_grf>; 2793 rockchip,php_grf = <&ioc_grf>; 2794 clocks = <&cru CLK_MAC100_50M_MATRIX>, <&cru CLK_MAC100_50M_MATRIX>, 2795 <&cru PCLK_MAC100>, <&cru ACLK_MAC100>; 2796 clock-names = "stmmaceth", "clk_mac_ref", 2797 "pclk_mac", "aclk_mac"; 2798 resets = <&cru SRST_A_MAC100>; 2799 reset-names = "stmmaceth"; 2800 status = "disabled"; 2801 2802 mdio1: mdio { 2803 compatible = "snps,dwmac-mdio"; 2804 #address-cells = <0x1>; 2805 #size-cells = <0x0>; 2806 }; 2807 }; 2808 2809 pinctrl: pinctrl { 2810 compatible = "rockchip,rk3562-pinctrl"; 2811 rockchip,grf = <&ioc_grf>; 2812 #address-cells = <2>; 2813 #size-cells = <2>; 2814 ranges; 2815 2816 gpio0: gpio@ff260000 { 2817 compatible = "rockchip,gpio-bank"; 2818 reg = <0x0 0xff260000 0x0 0x100>; 2819 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 2820 clocks = <&cru PCLK_PMU0_GPIO0>, <&cru DBCLK_PMU0_GPIO0>; 2821 2822 gpio-controller; 2823 #gpio-cells = <2>; 2824 gpio-ranges = <&pinctrl 0 0 32>; 2825 interrupt-controller; 2826 #interrupt-cells = <2>; 2827 }; 2828 2829 gpio1: gpio@ff620000 { 2830 compatible = "rockchip,gpio-bank"; 2831 reg = <0x0 0xff620000 0x0 0x100>; 2832 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 2833 clocks = <&cru PCLK_PERI_GPIO1>, <&cru DCLK_PERI_GPIO1>; 2834 2835 gpio-controller; 2836 #gpio-cells = <2>; 2837 gpio-ranges = <&pinctrl 0 32 32>; 2838 interrupt-controller; 2839 #interrupt-cells = <2>; 2840 }; 2841 2842 gpio2: gpio@ff630000 { 2843 compatible = "rockchip,gpio-bank"; 2844 reg = <0x0 0xff630000 0x0 0x100>; 2845 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 2846 clocks = <&cru PCLK_PERI_GPIO2>, <&cru DCLK_PERI_GPIO2>; 2847 2848 gpio-controller; 2849 #gpio-cells = <2>; 2850 gpio-ranges = <&pinctrl 0 64 32>; 2851 interrupt-controller; 2852 #interrupt-cells = <2>; 2853 }; 2854 2855 gpio3: gpio@ffac0000 { 2856 compatible = "rockchip,gpio-bank"; 2857 reg = <0x0 0xffac0000 0x0 0x100>; 2858 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 2859 clocks = <&cru PCLK_GPIO3_VCCIO156>, <&cru DCLK_BUS_GPIO3>; 2860 2861 gpio-controller; 2862 #gpio-cells = <2>; 2863 gpio-ranges = <&pinctrl 0 96 32>; 2864 interrupt-controller; 2865 #interrupt-cells = <2>; 2866 }; 2867 2868 gpio4: gpio@ffad0000 { 2869 compatible = "rockchip,gpio-bank"; 2870 reg = <0x0 0xffad0000 0x0 0x100>; 2871 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 2872 clocks = <&cru PCLK_GPIO4_VCCIO156>, <&cru DCLK_BUS_GPIO4>; 2873 2874 gpio-controller; 2875 #gpio-cells = <2>; 2876 gpio-ranges = <&pinctrl 0 128 32>; 2877 interrupt-controller; 2878 #interrupt-cells = <2>; 2879 }; 2880 }; 2881 2882 rockchip_suspend: rockchip-suspend { 2883 compatible = "rockchip,pm-rk3562"; 2884 status = "disabled"; 2885 rockchip,sleep-debug-en = <1>; 2886 rockchip,sleep-mode-config = < 2887 (0 2888 | RKPM_SLP_DEEP1_MODE 2889 | RKPM_SLP_PMIC_LP 2890 | RKPM_SLP_HW_PLLS_OFF 2891 | RKPM_SLP_PMUALIVE_32K 2892 | RKPM_SLP_OSC_DIS 2893 | RKPM_SLP_32K_PVTM 2894 ) 2895 >; 2896 rockchip,wakeup-config = < 2897 (0 2898 | RKPM_GPIO0_WKUP_EN 2899 ) 2900 >; 2901 }; 2902}; 2903 2904#include "rk3562-pinctrl.dtsi" 2905
