1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Rockchip SoC MIPI RX0 D-PHY Device Tree Bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Helen Koike <helen.koike@collabora.com> 11*4882a593Smuzhiyun - Ezequiel Garcia <ezequiel@collabora.com> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundescription: | 14*4882a593Smuzhiyun The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to 15*4882a593Smuzhiyun the ISP1 (Image Signal Processing unit v1.0) for CSI cameras. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyunproperties: 18*4882a593Smuzhiyun compatible: 19*4882a593Smuzhiyun const: rockchip,rk3399-mipi-dphy-rx0 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun clocks: 22*4882a593Smuzhiyun items: 23*4882a593Smuzhiyun - description: MIPI D-PHY ref clock 24*4882a593Smuzhiyun - description: MIPI D-PHY RX0 cfg clock 25*4882a593Smuzhiyun - description: Video in/out general register file clock 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun clock-names: 28*4882a593Smuzhiyun items: 29*4882a593Smuzhiyun - const: dphy-ref 30*4882a593Smuzhiyun - const: dphy-cfg 31*4882a593Smuzhiyun - const: grf 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun '#phy-cells': 34*4882a593Smuzhiyun const: 0 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun power-domains: 37*4882a593Smuzhiyun description: Video in/out power domain. 38*4882a593Smuzhiyun maxItems: 1 39*4882a593Smuzhiyun 40*4882a593Smuzhiyunrequired: 41*4882a593Smuzhiyun - compatible 42*4882a593Smuzhiyun - clocks 43*4882a593Smuzhiyun - clock-names 44*4882a593Smuzhiyun - '#phy-cells' 45*4882a593Smuzhiyun - power-domains 46*4882a593Smuzhiyun 47*4882a593SmuzhiyunadditionalProperties: false 48*4882a593Smuzhiyun 49*4882a593Smuzhiyunexamples: 50*4882a593Smuzhiyun - | 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* 53*4882a593Smuzhiyun * MIPI D-PHY RX0 use registers in "general register files", it 54*4882a593Smuzhiyun * should be a child of the GRF. 55*4882a593Smuzhiyun * 56*4882a593Smuzhiyun * grf: syscon@ff770000 { 57*4882a593Smuzhiyun * compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 58*4882a593Smuzhiyun * ... 59*4882a593Smuzhiyun * }; 60*4882a593Smuzhiyun */ 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #include <dt-bindings/clock/rk3399-cru.h> 63*4882a593Smuzhiyun #include <dt-bindings/power/rk3399-power.h> 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun mipi_dphy_rx0: mipi-dphy-rx0 { 66*4882a593Smuzhiyun compatible = "rockchip,rk3399-mipi-dphy-rx0"; 67*4882a593Smuzhiyun clocks = <&cru SCLK_MIPIDPHY_REF>, 68*4882a593Smuzhiyun <&cru SCLK_DPHY_RX0_CFG>, 69*4882a593Smuzhiyun <&cru PCLK_VIO_GRF>; 70*4882a593Smuzhiyun clock-names = "dphy-ref", "dphy-cfg", "grf"; 71*4882a593Smuzhiyun power-domains = <&power RK3399_PD_VIO>; 72*4882a593Smuzhiyun #phy-cells = <0>; 73*4882a593Smuzhiyun }; 74