Lines Matching +full:dphy +full:- +full:ref
1 // SPDX-License-Identifier: GPL-2.0+
5 * Chris Zhong <zyw@rock-chips.com>
6 * Nickey Yang <nickey.yang@rock-chips.com>
41 #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
93 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
96 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
97 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf)
285 /* dual-channel */
289 /* optional external dphy */
315 /* The table is based on 27MHz DPHY pll reference clock. */
366 return -EINVAL; in max_mbps_to_parameter()
371 writel(val, dsi->base + reg); in dsi_write()
376 return readl(dsi->base + reg); in dsi_read()
413 * ns2bc - Nanoseconds to byte clock cycles
417 return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000); in ns2bc()
421 * ns2ui - Nanoseconds to UI time periods
425 return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000); in ns2ui()
430 if (dsi->cdata->lanecfg1_grf_reg) in dw_mipi_dsi_phy_tx_config()
431 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg, in dw_mipi_dsi_phy_tx_config()
432 dsi->cdata->lanecfg1); in dw_mipi_dsi_phy_tx_config()
434 if (dsi->cdata->lanecfg2_grf_reg) in dw_mipi_dsi_phy_tx_config()
435 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg, in dw_mipi_dsi_phy_tx_config()
436 dsi->cdata->lanecfg2); in dw_mipi_dsi_phy_tx_config()
438 if (dsi->cdata->enable_grf_reg) in dw_mipi_dsi_phy_tx_config()
439 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg, in dw_mipi_dsi_phy_tx_config()
440 dsi->cdata->enable); in dw_mipi_dsi_phy_tx_config()
450 if (dsi->phy) in dw_mipi_dsi_phy_init()
456 * 000 - between 80 and 200 MHz in dw_mipi_dsi_phy_init()
457 * 001 - between 200 and 300 MHz in dw_mipi_dsi_phy_init()
458 * 010 - between 300 and 500 MHz in dw_mipi_dsi_phy_init()
459 * 011 - between 500 and 700 MHz in dw_mipi_dsi_phy_init()
460 * 100 - between 700 and 900 MHz in dw_mipi_dsi_phy_init()
461 * 101 - between 900 and 1100 MHz in dw_mipi_dsi_phy_init()
462 * 110 - between 1100 and 1300 MHz in dw_mipi_dsi_phy_init()
463 * 111 - between 1300 and 1500 MHz in dw_mipi_dsi_phy_init()
465 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200; in dw_mipi_dsi_phy_init()
467 i = max_mbps_to_parameter(dsi->lane_mbps); in dw_mipi_dsi_phy_init()
469 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_phy_init()
471 dsi->lane_mbps); in dw_mipi_dsi_phy_init()
491 INPUT_DIVIDER(dsi->input_div)); in dw_mipi_dsi_phy_init()
493 LOOP_DIV_LOW_SEL(dsi->feedback_div) | in dw_mipi_dsi_phy_init()
504 LOOP_DIV_HIGH_SEL(dsi->feedback_div) | in dw_mipi_dsi_phy_init()
557 if (dsi->phy_enabled) in dw_mipi_dsi_phy_power_on()
560 phy_power_on(dsi->phy); in dw_mipi_dsi_phy_power_on()
561 dsi->phy_enabled = true; in dw_mipi_dsi_phy_power_on()
568 if (!dsi->phy_enabled) in dw_mipi_dsi_phy_power_off()
571 phy_power_off(dsi->phy); in dw_mipi_dsi_phy_power_off()
572 dsi->phy_enabled = false; in dw_mipi_dsi_phy_power_off()
579 struct device *dev = dsi->dev; in dw_mipi_dsi_calculate_lane_mpbs()
585 if (dsi->is_slave) in dw_mipi_dsi_calculate_lane_mpbs()
586 return dsi->lane_mbps; in dw_mipi_dsi_calculate_lane_mpbs()
588 max_mbps = dsi->cdata->max_bit_rate_per_lane / USEC_PER_SEC; in dw_mipi_dsi_calculate_lane_mpbs()
591 if (!of_property_read_u32(dev->of_node, "rockchip,lane-rate", &value)) { in dw_mipi_dsi_calculate_lane_mpbs()
594 mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC); in dw_mipi_dsi_calculate_lane_mpbs()
601 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_calculate_lane_mpbs()
602 "DPHY clock frequency is out of range\n"); in dw_mipi_dsi_calculate_lane_mpbs()
608 if (dsi->slave) in dw_mipi_dsi_calculate_lane_mpbs()
609 dsi->slave->lane_mbps = target_mbps; in dw_mipi_dsi_calculate_lane_mpbs()
630 dsi->format = format; in dw_mipi_dsi_get_lane_mbps()
631 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); in dw_mipi_dsi_get_lane_mbps()
633 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_get_lane_mbps()
635 dsi->format); in dw_mipi_dsi_get_lane_mbps()
642 if (dsi->phy) { in dw_mipi_dsi_get_lane_mbps()
646 &dsi->phy_opts.mipi_dphy); in dw_mipi_dsi_get_lane_mbps()
647 ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY); in dw_mipi_dsi_get_lane_mbps()
649 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_get_lane_mbps()
654 phy_configure(dsi->phy, &dsi->phy_opts); in dw_mipi_dsi_get_lane_mbps()
655 hs_clk_rate = dsi->phy_opts.mipi_dphy.hs_clk_rate; in dw_mipi_dsi_get_lane_mbps()
656 dsi->lane_mbps = DIV_ROUND_UP(hs_clk_rate, USEC_PER_SEC); in dw_mipi_dsi_get_lane_mbps()
657 *lane_mbps = dsi->lane_mbps; in dw_mipi_dsi_get_lane_mbps()
662 fin = clk_get_rate(dsi->pllref_clk); in dw_mipi_dsi_get_lane_mbps()
681 * Due to the use of a "by 2 pre-scaler," the range of the in dw_mipi_dsi_get_lane_mbps()
695 delta = abs(fout - tmp); in dw_mipi_dsi_get_lane_mbps()
705 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC); in dw_mipi_dsi_get_lane_mbps()
706 *lane_mbps = dsi->lane_mbps; in dw_mipi_dsi_get_lane_mbps()
707 dsi->input_div = best_prediv; in dw_mipi_dsi_get_lane_mbps()
708 dsi->feedback_div = best_fbdiv; in dw_mipi_dsi_get_lane_mbps()
710 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n"); in dw_mipi_dsi_get_lane_mbps()
711 return -EINVAL; in dw_mipi_dsi_get_lane_mbps()
750 mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, in dw_mipi_dsi_rockchip_vop_routing()
751 &dsi->encoder); in dw_mipi_dsi_rockchip_vop_routing()
755 if (dsi->cdata->lcdsel_grf_reg) { in dw_mipi_dsi_rockchip_vop_routing()
756 regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg, in dw_mipi_dsi_rockchip_vop_routing()
757 mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big); in dw_mipi_dsi_rockchip_vop_routing()
759 if (dsi->slave && dsi->slave->cdata->lcdsel_grf_reg) in dw_mipi_dsi_rockchip_vop_routing()
760 regmap_write(dsi->slave->grf_regmap, in dw_mipi_dsi_rockchip_vop_routing()
761 dsi->slave->cdata->lcdsel_grf_reg, in dw_mipi_dsi_rockchip_vop_routing()
762 mux ? dsi->slave->cdata->lcdsel_lit : in dw_mipi_dsi_rockchip_vop_routing()
763 dsi->slave->cdata->lcdsel_big); in dw_mipi_dsi_rockchip_vop_routing()
774 struct drm_connector *connector = conn_state->connector; in dw_mipi_dsi_encoder_atomic_check()
775 struct drm_display_info *info = &connector->display_info; in dw_mipi_dsi_encoder_atomic_check()
777 switch (dsi->format) { in dw_mipi_dsi_encoder_atomic_check()
779 s->output_mode = ROCKCHIP_OUT_MODE_P888; in dw_mipi_dsi_encoder_atomic_check()
782 s->output_mode = ROCKCHIP_OUT_MODE_P666; in dw_mipi_dsi_encoder_atomic_check()
785 s->output_mode = ROCKCHIP_OUT_MODE_P565; in dw_mipi_dsi_encoder_atomic_check()
789 return -EINVAL; in dw_mipi_dsi_encoder_atomic_check()
792 if (info->num_bus_formats) in dw_mipi_dsi_encoder_atomic_check()
793 s->bus_format = info->bus_formats[0]; in dw_mipi_dsi_encoder_atomic_check()
795 s->bus_format = MEDIA_BUS_FMT_RGB888_1X24; in dw_mipi_dsi_encoder_atomic_check()
797 s->bus_flags = info->bus_flags; in dw_mipi_dsi_encoder_atomic_check()
799 if (dsi->cdata->soc_type == RK3568) { in dw_mipi_dsi_encoder_atomic_check()
800 s->bus_flags &= ~DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE; in dw_mipi_dsi_encoder_atomic_check()
801 s->bus_flags |= DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE; in dw_mipi_dsi_encoder_atomic_check()
804 s->output_type = DRM_MODE_CONNECTOR_DSI; in dw_mipi_dsi_encoder_atomic_check()
805 s->tv_state = &conn_state->tv; in dw_mipi_dsi_encoder_atomic_check()
806 s->color_space = V4L2_COLORSPACE_DEFAULT; in dw_mipi_dsi_encoder_atomic_check()
807 s->output_if = dsi->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0; in dw_mipi_dsi_encoder_atomic_check()
808 if (dsi->slave) { in dw_mipi_dsi_encoder_atomic_check()
809 s->output_flags |= ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE; in dw_mipi_dsi_encoder_atomic_check()
810 s->output_if |= VOP_OUTPUT_IF_MIPI1; in dw_mipi_dsi_encoder_atomic_check()
814 if (dsi->id && dsi->cdata->soc_type == RK3399) in dw_mipi_dsi_encoder_atomic_check()
815 s->output_flags |= ROCKCHIP_OUTPUT_DATA_SWAP; in dw_mipi_dsi_encoder_atomic_check()
817 if (dsi->dsc_enable) { in dw_mipi_dsi_encoder_atomic_check()
818 s->dsc_enable = 1; in dw_mipi_dsi_encoder_atomic_check()
819 s->dsc_sink_cap.version_major = dsi->version_major; in dw_mipi_dsi_encoder_atomic_check()
820 s->dsc_sink_cap.version_minor = dsi->version_minor; in dw_mipi_dsi_encoder_atomic_check()
821 s->dsc_sink_cap.slice_width = dsi->slice_width; in dw_mipi_dsi_encoder_atomic_check()
822 s->dsc_sink_cap.slice_height = dsi->slice_height; in dw_mipi_dsi_encoder_atomic_check()
824 s->dsc_sink_cap.target_bits_per_pixel_x16 = 8 << 4; in dw_mipi_dsi_encoder_atomic_check()
825 s->dsc_sink_cap.block_pred = dsi->block_pred_enable; in dw_mipi_dsi_encoder_atomic_check()
826 s->dsc_sink_cap.native_420 = 0; in dw_mipi_dsi_encoder_atomic_check()
828 memcpy(&s->pps, dsi->pps, sizeof(struct drm_dsc_picture_parameter_set)); in dw_mipi_dsi_encoder_atomic_check()
848 pm_runtime_get_sync(dsi->dev); in dw_mipi_dsi_rockchip_loader_protect()
849 phy_init(dsi->phy); in dw_mipi_dsi_rockchip_loader_protect()
850 dsi->phy_enabled = true; in dw_mipi_dsi_rockchip_loader_protect()
851 if (dsi->phy) in dw_mipi_dsi_rockchip_loader_protect()
852 dsi->phy->power_count++; in dw_mipi_dsi_rockchip_loader_protect()
854 pm_runtime_put(dsi->dev); in dw_mipi_dsi_rockchip_loader_protect()
855 phy_exit(dsi->phy); in dw_mipi_dsi_rockchip_loader_protect()
856 dsi->phy_enabled = false; in dw_mipi_dsi_rockchip_loader_protect()
857 if (dsi->phy) in dw_mipi_dsi_rockchip_loader_protect()
858 dsi->phy->power_count--; in dw_mipi_dsi_rockchip_loader_protect()
861 if (dsi->slave) in dw_mipi_dsi_rockchip_loader_protect()
862 dw_mipi_dsi_rockchip_loader_protect(dsi->slave, on); in dw_mipi_dsi_rockchip_loader_protect()
870 if (dsi->panel) in dw_mipi_dsi_rockchip_encoder_loader_protect()
871 panel_simple_loader_protect(dsi->panel); in dw_mipi_dsi_rockchip_encoder_loader_protect()
888 struct drm_encoder *encoder = &dsi->encoder; in rockchip_dsi_drm_create_encoder()
891 encoder->possible_crtcs = rockchip_drm_of_find_possible_crtcs(drm_dev, in rockchip_dsi_drm_create_encoder()
892 dsi->dev->of_node); in rockchip_dsi_drm_create_encoder()
912 node = of_parse_phandle(dsi->dev->of_node, "rockchip,dual-channel", 0); in dw_mipi_dsi_rockchip_find_second()
916 return ERR_PTR(-EPROBE_DEFER); in dw_mipi_dsi_rockchip_find_second()
921 return ERR_PTR(-EPROBE_DEFER); in dw_mipi_dsi_rockchip_find_second()
924 return &pdev->dev; in dw_mipi_dsi_rockchip_find_second()
943 return -ENODEV; in dw_mipi_dsi_get_dsc_info_from_sink()
946 np = panel->dev->of_node; in dw_mipi_dsi_get_dsc_info_from_sink()
948 np = bridge->of_node; in dw_mipi_dsi_get_dsc_info_from_sink()
950 dsi->c_option = of_property_read_bool(np, "phy-c-option"); in dw_mipi_dsi_get_dsc_info_from_sink()
951 dsi->scrambling_en = of_property_read_bool(np, "scrambling-enable"); in dw_mipi_dsi_get_dsc_info_from_sink()
952 dsi->dsc_enable = of_property_read_bool(np, "compressed-data"); in dw_mipi_dsi_get_dsc_info_from_sink()
953 dsi->block_pred_enable = of_property_read_bool(np, "blk-pred-enable"); in dw_mipi_dsi_get_dsc_info_from_sink()
954 of_property_read_u32(np, "slice-width", &dsi->slice_width); in dw_mipi_dsi_get_dsc_info_from_sink()
955 of_property_read_u32(np, "slice-height", &dsi->slice_height); in dw_mipi_dsi_get_dsc_info_from_sink()
956 of_property_read_u32(np, "slice-per-pkt", &dsi->slice_per_pkt); in dw_mipi_dsi_get_dsc_info_from_sink()
957 of_property_read_u8(np, "version-major", &dsi->version_major); in dw_mipi_dsi_get_dsc_info_from_sink()
958 of_property_read_u8(np, "version-minor", &dsi->version_minor); in dw_mipi_dsi_get_dsc_info_from_sink()
960 data = of_get_property(np, "panel-init-sequence", &len); in dw_mipi_dsi_get_dsc_info_from_sink()
962 return -EINVAL; in dw_mipi_dsi_get_dsc_info_from_sink()
964 d = devm_kmemdup(dsi->dev, data, len, GFP_KERNEL); in dw_mipi_dsi_get_dsc_info_from_sink()
966 return -ENOMEM; in dw_mipi_dsi_get_dsc_info_from_sink()
971 len -= sizeof(*header); in dw_mipi_dsi_get_dsc_info_from_sink()
973 if (header->payload_length > len) in dw_mipi_dsi_get_dsc_info_from_sink()
974 return -EINVAL; in dw_mipi_dsi_get_dsc_info_from_sink()
976 if (header->cmd_type == MIPI_DSI_PICTURE_PARAMETER_SET) { in dw_mipi_dsi_get_dsc_info_from_sink()
977 dsc_packed_pps = devm_kmemdup(dsi->dev, d, in dw_mipi_dsi_get_dsc_info_from_sink()
978 header->payload_length, GFP_KERNEL); in dw_mipi_dsi_get_dsc_info_from_sink()
980 return -ENOMEM; in dw_mipi_dsi_get_dsc_info_from_sink()
986 d += header->payload_length; in dw_mipi_dsi_get_dsc_info_from_sink()
987 len -= header->payload_length; in dw_mipi_dsi_get_dsc_info_from_sink()
989 dsi->pps = pps; in dw_mipi_dsi_get_dsc_info_from_sink()
1008 /* we are the slave in dual-DSI */ in dw_mipi_dsi_rockchip_bind()
1009 dsi->slave = dev_get_drvdata(second); in dw_mipi_dsi_rockchip_bind()
1010 if (!dsi->slave) { in dw_mipi_dsi_rockchip_bind()
1012 return -ENODEV; in dw_mipi_dsi_rockchip_bind()
1015 dsi->slave->is_slave = true; in dw_mipi_dsi_rockchip_bind()
1016 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd); in dw_mipi_dsi_rockchip_bind()
1020 if (dsi->is_slave) in dw_mipi_dsi_rockchip_bind()
1023 ret = drm_of_find_panel_or_bridge(dsi->dev->of_node, 1, -1, in dw_mipi_dsi_rockchip_bind()
1024 &dsi->panel, &dsi->bridge); in dw_mipi_dsi_rockchip_bind()
1026 dev_err(dsi->dev, "failed to find panel or bridge: %d\n", ret); in dw_mipi_dsi_rockchip_bind()
1030 ret = clk_prepare_enable(dsi->pllref_clk); in dw_mipi_dsi_rockchip_bind()
1042 ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder); in dw_mipi_dsi_rockchip_bind()
1048 if (dsi->panel) in dw_mipi_dsi_rockchip_bind()
1049 dw_mipi_dsi_get_dsc_info_from_sink(dsi, dsi->panel, NULL); in dw_mipi_dsi_rockchip_bind()
1051 dsi->sub_dev.connector = dw_mipi_dsi_get_connector(dsi->dmd); in dw_mipi_dsi_rockchip_bind()
1052 if (dsi->sub_dev.connector) { in dw_mipi_dsi_rockchip_bind()
1053 dsi->sub_dev.of_node = dev->of_node; in dw_mipi_dsi_rockchip_bind()
1054 dsi->sub_dev.loader_protect = dw_mipi_dsi_rockchip_encoder_loader_protect; in dw_mipi_dsi_rockchip_bind()
1055 rockchip_drm_register_sub_dev(&dsi->sub_dev); in dw_mipi_dsi_rockchip_bind()
1067 if (dsi->is_slave) in dw_mipi_dsi_rockchip_unbind()
1070 if (dsi->sub_dev.connector) in dw_mipi_dsi_rockchip_unbind()
1071 rockchip_drm_unregister_sub_dev(&dsi->sub_dev); in dw_mipi_dsi_rockchip_unbind()
1073 dw_mipi_dsi_unbind(dsi->dmd); in dw_mipi_dsi_rockchip_unbind()
1075 clk_disable_unprepare(dsi->pllref_clk); in dw_mipi_dsi_rockchip_unbind()
1087 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops); in dw_mipi_dsi_rockchip_component_add()
1089 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n", in dw_mipi_dsi_rockchip_component_add()
1099 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops); in dw_mipi_dsi_rockchip_component_del()
1106 struct device *dev = &pdev->dev; in dw_mipi_dsi_rockchip_probe()
1107 struct device_node *np = dev->of_node; in dw_mipi_dsi_rockchip_probe()
1116 return -ENOMEM; in dw_mipi_dsi_rockchip_probe()
1119 dsi->base = devm_ioremap_resource(dev, res); in dw_mipi_dsi_rockchip_probe()
1120 if (IS_ERR(dsi->base)) { in dw_mipi_dsi_rockchip_probe()
1122 return PTR_ERR(dsi->base); in dw_mipi_dsi_rockchip_probe()
1127 if (cdata[i].reg == res->start) { in dw_mipi_dsi_rockchip_probe()
1128 dsi->cdata = &cdata[i]; in dw_mipi_dsi_rockchip_probe()
1129 dsi->id = i; in dw_mipi_dsi_rockchip_probe()
1136 if (!dsi->cdata) { in dw_mipi_dsi_rockchip_probe()
1137 DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name); in dw_mipi_dsi_rockchip_probe()
1138 return -EINVAL; in dw_mipi_dsi_rockchip_probe()
1141 /* try to get a possible external dphy */ in dw_mipi_dsi_rockchip_probe()
1142 dsi->phy = devm_phy_optional_get(dev, "dphy"); in dw_mipi_dsi_rockchip_probe()
1143 if (IS_ERR(dsi->phy)) { in dw_mipi_dsi_rockchip_probe()
1144 ret = PTR_ERR(dsi->phy); in dw_mipi_dsi_rockchip_probe()
1145 DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret); in dw_mipi_dsi_rockchip_probe()
1149 dsi->pclk = devm_clk_get(dev, "pclk"); in dw_mipi_dsi_rockchip_probe()
1150 if (IS_ERR(dsi->pclk)) { in dw_mipi_dsi_rockchip_probe()
1151 ret = PTR_ERR(dsi->pclk); in dw_mipi_dsi_rockchip_probe()
1156 dsi->pllref_clk = devm_clk_get(dev, "ref"); in dw_mipi_dsi_rockchip_probe()
1157 if (IS_ERR(dsi->pllref_clk)) { in dw_mipi_dsi_rockchip_probe()
1158 if (dsi->phy) { in dw_mipi_dsi_rockchip_probe()
1163 dsi->pllref_clk = NULL; in dw_mipi_dsi_rockchip_probe()
1165 ret = PTR_ERR(dsi->pllref_clk); in dw_mipi_dsi_rockchip_probe()
1173 if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) { in dw_mipi_dsi_rockchip_probe()
1174 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); in dw_mipi_dsi_rockchip_probe()
1175 if (IS_ERR(dsi->phy_cfg_clk)) { in dw_mipi_dsi_rockchip_probe()
1176 ret = PTR_ERR(dsi->phy_cfg_clk); in dw_mipi_dsi_rockchip_probe()
1183 if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) { in dw_mipi_dsi_rockchip_probe()
1184 dsi->grf_clk = devm_clk_get(dev, "grf"); in dw_mipi_dsi_rockchip_probe()
1185 if (IS_ERR(dsi->grf_clk)) { in dw_mipi_dsi_rockchip_probe()
1186 ret = PTR_ERR(dsi->grf_clk); in dw_mipi_dsi_rockchip_probe()
1192 if (dsi->cdata->flags & DW_MIPI_NEEDS_HCLK) { in dw_mipi_dsi_rockchip_probe()
1193 dsi->hclk = devm_clk_get(dev, "hclk"); in dw_mipi_dsi_rockchip_probe()
1194 if (IS_ERR(dsi->hclk)) { in dw_mipi_dsi_rockchip_probe()
1195 ret = PTR_ERR(dsi->hclk); in dw_mipi_dsi_rockchip_probe()
1201 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); in dw_mipi_dsi_rockchip_probe()
1202 if (IS_ERR(dsi->grf_regmap)) { in dw_mipi_dsi_rockchip_probe()
1203 DRM_DEV_ERROR(dsi->dev, "Unable to get rockchip,grf\n"); in dw_mipi_dsi_rockchip_probe()
1204 return PTR_ERR(dsi->grf_regmap); in dw_mipi_dsi_rockchip_probe()
1207 dsi->dev = dev; in dw_mipi_dsi_rockchip_probe()
1208 dsi->pdata.base = dsi->base; in dw_mipi_dsi_rockchip_probe()
1209 dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes; in dw_mipi_dsi_rockchip_probe()
1210 dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops; in dw_mipi_dsi_rockchip_probe()
1211 dsi->pdata.priv_data = dsi; in dw_mipi_dsi_rockchip_probe()
1214 dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata); in dw_mipi_dsi_rockchip_probe()
1215 if (IS_ERR(dsi->dmd)) { in dw_mipi_dsi_rockchip_probe()
1216 ret = PTR_ERR(dsi->dmd); in dw_mipi_dsi_rockchip_probe()
1217 if (ret != -EPROBE_DEFER) in dw_mipi_dsi_rockchip_probe()
1225 dw_mipi_dsi_remove(dsi->dmd); in dw_mipi_dsi_rockchip_probe()
1232 clk_disable_unprepare(dsi->pllref_clk); in dw_mipi_dsi_rockchip_probe()
1242 dw_mipi_dsi_remove(dsi->dmd); in dw_mipi_dsi_rockchip_remove()
1251 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_runtime_suspend()
1252 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_runtime_suspend()
1253 clk_disable_unprepare(dsi->hclk); in dw_mipi_dsi_runtime_suspend()
1254 clk_disable_unprepare(dsi->phy_cfg_clk); in dw_mipi_dsi_runtime_suspend()
1263 clk_prepare_enable(dsi->phy_cfg_clk); in dw_mipi_dsi_runtime_resume()
1264 clk_prepare_enable(dsi->hclk); in dw_mipi_dsi_runtime_resume()
1265 clk_prepare_enable(dsi->pclk); in dw_mipi_dsi_runtime_resume()
1266 clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_runtime_resume()
1449 .compatible = "rockchip,px30-mipi-dsi",
1452 .compatible = "rockchip,rk3128-mipi-dsi",
1455 .compatible = "rockchip,rk3288-mipi-dsi",
1458 .compatible = "rockchip,rk3399-mipi-dsi",
1461 .compatible = "rockchip,rk3562-mipi-dsi",
1464 .compatible = "rockchip,rk3568-mipi-dsi",
1467 .compatible = "rockchip,rv1126-mipi-dsi",
1480 .name = "dw-mipi-dsi-rockchip",
1482 * For dual-DSI display, one DSI pokes at the other DSI's