1*4882a593SmuzhiyunROCKCHIP MIPI DPHY WITH INNO IP BLOCK 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun - compatible : must be one of: 5*4882a593Smuzhiyun "rockchip,rk1808-mipi-dphy"; 6*4882a593Smuzhiyun "rockchip,rv1126-mipi-dphy"; 7*4882a593Smuzhiyun - reg : the address offset of register for mipi-dphy configuration. 8*4882a593Smuzhiyun - #phy-cells : must be 0. See ./phy-bindings.txt for details. 9*4882a593Smuzhiyun - clocks and clock-names: 10*4882a593Smuzhiyun - the "pclk" clock is required by the phy module, used to register 11*4882a593Smuzhiyun configuration 12*4882a593Smuzhiyun - the "ref" clock is used to get the rate of the reference clock 13*4882a593Smuzhiyun provided to the PHY module 14*4882a593Smuzhiyun - clock-output-names: from common clock binding. 15*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 16*4882a593Smuzhiyun - #clock-cells : from common clock binding; shall be set to 0. 17*4882a593Smuzhiyun - resets : phandle to the reset of MIPI DSI PHY APB clock. 18*4882a593Smuzhiyun - reset-names : should be "apb". 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunExample: 21*4882a593Smuzhiyun mipi_dphy: mipi-dphy@ff370000 { 22*4882a593Smuzhiyun compatible = "rockchip,rk1808-mipi-dphy"; 23*4882a593Smuzhiyun reg = <0x0 0xff370000 0x0 0x500>; 24*4882a593Smuzhiyun clocks = <&cru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>; 25*4882a593Smuzhiyun clock-names = "ref", "pclk"; 26*4882a593Smuzhiyun clock-output-names = "mipi_dphy_pll"; 27*4882a593Smuzhiyun #clock-cells = <0>; 28*4882a593Smuzhiyun resets = <&cru SRST_MIPIDSIPHY_P>; 29*4882a593Smuzhiyun reset-names = "apb"; 30*4882a593Smuzhiyun #phy-cells = <0>; 31*4882a593Smuzhiyun rockchip,grf = <&grf>; 32*4882a593Smuzhiyun status = "disabled"; 33*4882a593Smuzhiyun }; 34