Lines Matching +full:dphy +full:- +full:ref
1 // SPDX-License-Identifier: GPL-2.0+
30 #include "rockchip-mipi-csi-tx.h"
74 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
77 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
78 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0x1f)
111 /* The table is based on 27MHz DPHY pll reference clock. */
180 const u32 field = csi->pdata->csi0_grf_reg_fields[index]; in grf_field_write()
184 if (!field || !csi->grf) in grf_field_write()
191 regmap_write(csi->grf, reg, (val << lsb) | (GENMASK(msb, lsb) << 16)); in grf_field_write()
196 writel(v, csi->regs + offset); in csi_writel()
197 csi->regsbak[offset >> 2] = v; in csi_writel()
202 return readl(csi->regs + offset); in csi_readl()
209 u32 cached_val = csi->regsbak[offset >> 2]; in csi_mask_write()
216 writel(v, csi->regs + offset); in csi_mask_write()
227 return -EINVAL; in phy_max_mbps_to_testdin()
254 writel(0x01000100, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0); in rockchip_mipi_csi_phy_write()
256 csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0); in rockchip_mipi_csi_phy_write()
257 writel(0x02000200, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0); in rockchip_mipi_csi_phy_write()
258 writel(0x01000000, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0); in rockchip_mipi_csi_phy_write()
259 writel(0x02000000, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0); in rockchip_mipi_csi_phy_write()
260 writel(0x01000000, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0); in rockchip_mipi_csi_phy_write()
262 csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0); in rockchip_mipi_csi_phy_write()
263 writel(0x01000100, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0); in rockchip_mipi_csi_phy_write()
272 csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0); in rockchip_mipi_csi_phy_read()
273 writel(0x01000000, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0); in rockchip_mipi_csi_phy_read()
275 val = readl(csi->test_code_regs + FPGA_DSI_PHY_TST_READ) & 0xff; in rockchip_mipi_csi_phy_read()
276 writel(0x03000100, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0); in rockchip_mipi_csi_phy_read()
283 writel(0x04000000, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0); in rockchip_bidir4l_board_phy_reset()
284 writel(0x08000000, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0); in rockchip_bidir4l_board_phy_reset()
285 writel(0x01000100, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0); in rockchip_bidir4l_board_phy_reset()
286 writel(0x80008000, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0); in rockchip_bidir4l_board_phy_reset()
287 writel(0x80000000, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0); in rockchip_bidir4l_board_phy_reset()
288 writel(0x40004000, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0); in rockchip_bidir4l_board_phy_reset()
293 writel(0x01000100, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0); in rockchip_bidir4l_board_phy_enable()
294 writel(0x02000000, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0); in rockchip_bidir4l_board_phy_enable()
295 writel(0x08000800, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0); in rockchip_bidir4l_board_phy_enable()
296 writel(0x04000400, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0); in rockchip_bidir4l_board_phy_enable()
302 writel(m_ERR_INTR_EN | m_ERR_INTR_MASK, csi->regs + CSITX_ERR_INTR_EN); in rockchip_mipi_csi_irq_init()
305 writel(m_FRM_END_TX | v_FRM_END_TX(0), csi->regs + CSITX_INTR_EN); in rockchip_mipi_csi_irq_init()
311 writel(m_ERR_INTR_MASK, csi->regs + CSITX_ERR_INTR_EN); in rockchip_mipi_csi_irq_disable()
314 writel(m_INTR_MASK, csi->regs + CSITX_INTR_EN); in rockchip_mipi_csi_irq_disable()
319 if (csi->dphy.phy) in rockchip_mipi_dphy_power_on()
320 phy_power_on(csi->dphy.phy); in rockchip_mipi_dphy_power_on()
329 if (csi->dphy.phy) in rockchip_mipi_dphy_power_off()
330 phy_power_off(csi->dphy.phy); in rockchip_mipi_dphy_power_off()
337 /* enable csi tx, dphy and config lane num */ in rockchip_mipi_csi_tx_en()
339 val = v_CSITX_EN(1) | v_DPHY_EN(1) | v_LANE_NUM(csi->lanes - 1); in rockchip_mipi_csi_tx_en()
361 /* disable csi tx, dphy and config lane num */ in rockchip_mipi_csi_host_power_off()
372 INPUT_DIVIDER(csi->dphy.input_div)); in rockchip_mipi_csi_phy_pll_init()
374 LOOP_DIV_LOW_SEL(csi->dphy.feedback_div) | in rockchip_mipi_csi_phy_pll_init()
379 LOOP_DIV_HIGH_SEL(csi->dphy.feedback_div) | in rockchip_mipi_csi_phy_pll_init()
390 vco = (csi->lane_mbps < 200) ? 0 : (csi->lane_mbps + 100) / 200; in rockchip_mipi_csi_phy_init()
392 testdin = phy_max_mbps_to_testdin(csi->lane_mbps); in rockchip_mipi_csi_phy_init()
394 dev_err(csi->dev, in rockchip_mipi_csi_phy_init()
396 csi->lane_mbps); in rockchip_mipi_csi_phy_init()
401 rockchip_mipi_csi_phy_write(csi, 0xac, csi->lanes - 1); in rockchip_mipi_csi_phy_init()
441 * mipi_csi_pixel_format_to_bpp - obtain the number of bits per pixel for any
460 return -EINVAL; in mipi_csi_pixel_format_to_bpp()
470 struct device_node *np = csi->dev->of_node; in rockchip_mipi_csi_calc_bandwidth()
475 if (!of_property_read_u32(np, "rockchip,lane-rate", &value)) in rockchip_mipi_csi_calc_bandwidth()
478 max_mbps = csi->pdata->max_bit_rate_per_lane / USEC_PER_SEC; in rockchip_mipi_csi_calc_bandwidth()
480 bpp = mipi_csi_pixel_format_to_bpp(csi->format); in rockchip_mipi_csi_calc_bandwidth()
482 dev_err(csi->dev, "failed to get bpp for pixel format %d\n", in rockchip_mipi_csi_calc_bandwidth()
483 csi->format); in rockchip_mipi_csi_calc_bandwidth()
487 lanes = csi->lanes; in rockchip_mipi_csi_calc_bandwidth()
489 mpclk = DIV_ROUND_UP(csi->mode.clock, MSEC_PER_SEC); in rockchip_mipi_csi_calc_bandwidth()
498 dev_err(csi->dev, "DPHY clock freq is out of range\n"); in rockchip_mipi_csi_calc_bandwidth()
515 pllref = DIV_ROUND_UP(clk_get_rate(csi->dphy.ref_clk), USEC_PER_SEC); in rockchip_mipi_csi_get_lane_bps()
530 csi->lane_mbps = pllref / n * m; in rockchip_mipi_csi_get_lane_bps()
531 csi->dphy.input_div = n; in rockchip_mipi_csi_get_lane_bps()
532 csi->dphy.feedback_div = m; in rockchip_mipi_csi_get_lane_bps()
546 rate = clk_round_rate(csi->dphy.hs_clk, bw); in rockchip_mipi_csi_set_hs_clk()
547 ret = clk_set_rate(csi->dphy.hs_clk, rate); in rockchip_mipi_csi_set_hs_clk()
549 dev_err(csi->dev, "failed to set hs clock rate: %lu\n", in rockchip_mipi_csi_set_hs_clk()
552 csi->lane_mbps = rate / USEC_PER_SEC; in rockchip_mipi_csi_set_hs_clk()
560 if (device->lanes == 0 || device->lanes > 8) { in rockchip_mipi_csi_host_attach()
561 dev_err(csi->dev, "the number of data lanes(%u) is too many\n", in rockchip_mipi_csi_host_attach()
562 device->lanes); in rockchip_mipi_csi_host_attach()
563 return -EINVAL; in rockchip_mipi_csi_host_attach()
565 csi->client = device->dev.of_node; in rockchip_mipi_csi_host_attach()
566 csi->lanes = device->lanes; in rockchip_mipi_csi_host_attach()
567 csi->channel = device->channel; in rockchip_mipi_csi_host_attach()
568 csi->format = device->format; in rockchip_mipi_csi_host_attach()
569 csi->mode_flags = device->mode_flags; in rockchip_mipi_csi_host_attach()
579 if (csi->panel) in rockchip_mipi_csi_host_detach()
580 drm_panel_detach(csi->panel); in rockchip_mipi_csi_host_detach()
582 csi->panel = NULL; in rockchip_mipi_csi_host_detach()
597 switch (csi->format) { in rockchip_mipi_csi_path_config()
599 vop_wc = csi->mode.hdisplay; in rockchip_mipi_csi_path_config()
603 vop_wc = csi->mode.hdisplay * 5 / 4; in rockchip_mipi_csi_path_config()
607 vop_wc = csi->mode.hdisplay; in rockchip_mipi_csi_path_config()
612 if (csi->path_mode == VOP_PATH) { in rockchip_mipi_csi_path_config()
665 if (csi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { in rockchip_mipi_csi_video_mode_config()
680 /* Configures DPHY Selete */ in rockchip_mipi_dphy_init()
683 /* Configures DPHY to work as a Master */ in rockchip_mipi_dphy_init()
696 grf_field_write(csi, ENABLE_N, map[csi->lanes - 1]); in rockchip_mipi_dphy_init()
700 if (!csi->dphy.phy) { in rockchip_mipi_dphy_init()
701 /* reset dphy */ in rockchip_mipi_dphy_init()
705 /* init dphy */ in rockchip_mipi_dphy_init()
707 rockchip_mipi_csi_phy_write(csi, 0xac, csi->lanes - 1); in rockchip_mipi_dphy_init()
721 /* enable dphy */ in rockchip_mipi_dphy_init()
733 val = v_PIXEL_FORMAT(csi->format); in rockchip_mipi_csi_fmt_config()
737 val = v_CAM_FORMAT(csi->format); in rockchip_mipi_csi_fmt_config()
748 drm_mode_copy(&csi->mode, adjusted_mode); in rockchip_mipi_csi_encoder_mode_set()
756 pm_runtime_put(csi->dev); in rockchip_mipi_csi_post_disable()
757 clk_disable_unprepare(csi->pclk); in rockchip_mipi_csi_post_disable()
758 clk_disable_unprepare(csi->dphy.hs_clk); in rockchip_mipi_csi_post_disable()
759 clk_disable_unprepare(csi->dphy.ref_clk); in rockchip_mipi_csi_post_disable()
766 if (csi->panel) in rockchip_mipi_csi_encoder_disable()
767 drm_panel_disable(csi->panel); in rockchip_mipi_csi_encoder_disable()
769 if (csi->panel) in rockchip_mipi_csi_encoder_disable()
770 drm_panel_unprepare(csi->panel); in rockchip_mipi_csi_encoder_disable()
785 if (csi->dphy.phy) in rockchip_mipi_csi_pre_init()
790 dev_info(csi->dev, "final CSI-Link bandwidth: %u x %d Mbps\n", in rockchip_mipi_csi_pre_init()
791 csi->lane_mbps, csi->lanes); in rockchip_mipi_csi_pre_init()
800 val = v_CSITX_ENABLE_PHY(map[csi->lanes - 1]); in rockchip_mipi_csihost_enable_phy()
806 rockchip_mipi_csi_fmt_config(csi, &csi->mode); in rockchip_mipi_csi_host_init()
824 ret = readl_poll_timeout(csi->regs + CSITX_STATUS1, in rockchip_mipi_csi_calibration()
828 dev_err(csi->dev, "PHY is not locked\n"); in rockchip_mipi_csi_calibration()
833 ret = readl_poll_timeout(csi->regs + CSITX_STATUS1, in rockchip_mipi_csi_calibration()
837 dev_err(csi->dev, "lane module is not in stop state\n"); in rockchip_mipi_csi_calibration()
850 clk_prepare_enable(csi->dphy.ref_clk); in rockchip_mipi_csi_pre_enable()
851 clk_prepare_enable(csi->dphy.hs_clk); in rockchip_mipi_csi_pre_enable()
852 clk_prepare_enable(csi->pclk); in rockchip_mipi_csi_pre_enable()
853 pm_runtime_get_sync(csi->dev); in rockchip_mipi_csi_pre_enable()
856 for (i = 0; i < csi->pdata->rsts_num; i++) { in rockchip_mipi_csi_pre_enable()
857 if (csi->tx_rsts[i]) in rockchip_mipi_csi_pre_enable()
858 reset_control_assert(csi->tx_rsts[i]); in rockchip_mipi_csi_pre_enable()
861 for (i = 0; i < csi->pdata->rsts_num; i++) { in rockchip_mipi_csi_pre_enable()
862 if (csi->tx_rsts[i]) in rockchip_mipi_csi_pre_enable()
863 reset_control_deassert(csi->tx_rsts[i]); in rockchip_mipi_csi_pre_enable()
866 if (!csi->regsbak) { in rockchip_mipi_csi_pre_enable()
867 csi->regsbak = in rockchip_mipi_csi_pre_enable()
868 devm_kzalloc(csi->dev, csi->regs_len, GFP_KERNEL); in rockchip_mipi_csi_pre_enable()
870 if (!csi->regsbak) in rockchip_mipi_csi_pre_enable()
871 return -ENOMEM; in rockchip_mipi_csi_pre_enable()
873 memcpy(csi->regsbak, csi->regs, csi->regs_len); in rockchip_mipi_csi_pre_enable()
891 if (csi->panel) in rockchip_mipi_csi_encoder_enable()
892 drm_panel_prepare(csi->panel); in rockchip_mipi_csi_encoder_enable()
894 if (csi->panel) in rockchip_mipi_csi_encoder_enable()
895 drm_panel_enable(csi->panel); in rockchip_mipi_csi_encoder_enable()
905 struct drm_connector *connector = conn_state->connector; in rockchip_mipi_csi_encoder_atomic_check()
906 struct drm_display_info *info = &connector->display_info; in rockchip_mipi_csi_encoder_atomic_check()
908 switch (csi->format) { in rockchip_mipi_csi_encoder_atomic_check()
910 s->output_mode = ROCKCHIP_OUT_MODE_P888; in rockchip_mipi_csi_encoder_atomic_check()
913 s->output_mode = ROCKCHIP_OUT_MODE_P666; in rockchip_mipi_csi_encoder_atomic_check()
917 s->output_mode = ROCKCHIP_OUT_MODE_P888; in rockchip_mipi_csi_encoder_atomic_check()
921 s->output_type = DRM_MODE_CONNECTOR_DSI; in rockchip_mipi_csi_encoder_atomic_check()
922 if (info->num_bus_formats) in rockchip_mipi_csi_encoder_atomic_check()
923 s->bus_format = info->bus_formats[0]; in rockchip_mipi_csi_encoder_atomic_check()
925 s->bus_format = MEDIA_BUS_FMT_RGB888_1X24; in rockchip_mipi_csi_encoder_atomic_check()
926 s->tv_state = &conn_state->tv; in rockchip_mipi_csi_encoder_atomic_check()
927 s->eotf = TRADITIONAL_GAMMA_SDR; in rockchip_mipi_csi_encoder_atomic_check()
928 s->color_space = V4L2_COLORSPACE_DEFAULT; in rockchip_mipi_csi_encoder_atomic_check()
951 return drm_panel_get_modes(csi->panel); in rockchip_mipi_csi_connector_get_modes()
959 return &csi->encoder; in rockchip_mipi_csi_connector_best_encoder()
967 if (csi->panel) in rockchip_mipi_loader_protect()
968 drm_panel_loader_protect(csi->panel, on); in rockchip_mipi_loader_protect()
970 pm_runtime_get_sync(csi->dev); in rockchip_mipi_loader_protect()
971 if (!csi->regsbak) { in rockchip_mipi_loader_protect()
972 csi->regsbak = devm_kzalloc(csi->dev, csi->regs_len, in rockchip_mipi_loader_protect()
974 if (!csi->regsbak) in rockchip_mipi_loader_protect()
975 return -ENOMEM; in rockchip_mipi_loader_protect()
976 memcpy(csi->regsbak, csi->regs, csi->regs_len); in rockchip_mipi_loader_protect()
979 pm_runtime_put(csi->dev); in rockchip_mipi_loader_protect()
1026 if (property == csi->csi_tx_path_property) { in rockchip_mipi_csi_connector_set_property()
1028 * csi->path_mode = val; in rockchip_mipi_csi_connector_set_property()
1035 return -EINVAL; in rockchip_mipi_csi_connector_set_property()
1046 if (property == csi->csi_tx_path_property) { in rockchip_mipi_csi_connector_get_property()
1047 *val = csi->path_mode; in rockchip_mipi_csi_connector_get_property()
1052 return -EINVAL; in rockchip_mipi_csi_connector_get_property()
1072 prop = drm_property_create_range(csi->connector.dev, 0, in rockchip_mipi_csi_property_create()
1073 "CSI-TX-PATH", in rockchip_mipi_csi_property_create()
1076 csi->csi_tx_path_property = prop; in rockchip_mipi_csi_property_create()
1077 drm_object_attach_property(&csi->connector.base, prop, 0); in rockchip_mipi_csi_property_create()
1086 struct drm_encoder *encoder = &csi->encoder; in rockchip_mipi_csi_register()
1087 struct drm_connector *connector = &csi->connector; in rockchip_mipi_csi_register()
1088 struct device *dev = csi->dev; in rockchip_mipi_csi_register()
1091 encoder->possible_crtcs = rockchip_drm_of_find_possible_crtcs(drm, in rockchip_mipi_csi_register()
1092 dev->of_node); in rockchip_mipi_csi_register()
1099 if (encoder->possible_crtcs == 0) in rockchip_mipi_csi_register()
1100 return -EPROBE_DEFER; in rockchip_mipi_csi_register()
1102 drm_encoder_helper_add(&csi->encoder, in rockchip_mipi_csi_register()
1104 ret = drm_encoder_init(drm, &csi->encoder, in rockchip_mipi_csi_register()
1112 csi->connector.port = dev->of_node; in rockchip_mipi_csi_register()
1113 ret = drm_connector_init(drm, &csi->connector, in rockchip_mipi_csi_register()
1126 ret = drm_panel_attach(csi->panel, &csi->connector); in rockchip_mipi_csi_register()
1147 csi->panel = of_drm_find_panel(csi->client); in rockchip_mipi_csi_bind()
1148 if (!csi->panel) { in rockchip_mipi_csi_bind()
1150 return -EPROBE_DEFER; in rockchip_mipi_csi_bind()
1187 DRM_DEV_ERROR_RATELIMITED(csi->dev, "%s\n", in rockchip_mipi_csi_irq_handler()
1192 DRM_DEV_ERROR_RATELIMITED(csi->dev, "%s\n", in rockchip_mipi_csi_irq_handler()
1194 writel(int_status | m_INTR_MASK, csi->regs + CSITX_INTR_CLR); in rockchip_mipi_csi_irq_handler()
1196 csi->regs + CSITX_ERR_INTR_CLR); in rockchip_mipi_csi_irq_handler()
1203 struct device *dev = csi->dev; in rockchip_mipi_dphy_attach()
1206 csi->dphy.phy = devm_phy_optional_get(dev, "mipi_dphy"); in rockchip_mipi_dphy_attach()
1207 if (IS_ERR(csi->dphy.phy)) { in rockchip_mipi_dphy_attach()
1208 ret = PTR_ERR(csi->dphy.phy); in rockchip_mipi_dphy_attach()
1209 dev_err(dev, "failed to get mipi dphy: %d\n", ret); in rockchip_mipi_dphy_attach()
1213 if (csi->dphy.phy) { in rockchip_mipi_dphy_attach()
1214 dev_dbg(dev, "Use Non-SNPS PHY\n"); in rockchip_mipi_dphy_attach()
1216 csi->dphy.hs_clk = devm_clk_get(dev, "hs_clk"); in rockchip_mipi_dphy_attach()
1217 if (IS_ERR(csi->dphy.hs_clk)) { in rockchip_mipi_dphy_attach()
1218 dev_err(dev, "failed to get PHY high-speed clock\n"); in rockchip_mipi_dphy_attach()
1219 return PTR_ERR(csi->dphy.hs_clk); in rockchip_mipi_dphy_attach()
1223 csi->dphy.ref_clk = devm_clk_get(dev, "ref"); in rockchip_mipi_dphy_attach()
1224 if (IS_ERR(csi->dphy.ref_clk)) { in rockchip_mipi_dphy_attach()
1226 return PTR_ERR(csi->dphy.ref_clk); in rockchip_mipi_dphy_attach()
1235 struct device *dev = csi->dev; in dw_mipi_csi_parse_dt()
1236 struct device_node *np = dev->of_node; in dw_mipi_csi_parse_dt()
1239 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); in dw_mipi_csi_parse_dt()
1246 return -ENODEV; in dw_mipi_csi_parse_dt()
1251 csi->client = remote; in dw_mipi_csi_parse_dt()
1258 struct device *dev = &pdev->dev; in rockchip_mipi_csi_probe()
1260 struct device_node *np = dev->of_node; in rockchip_mipi_csi_probe()
1266 return -ENOMEM; in rockchip_mipi_csi_probe()
1268 csi->dev = dev; in rockchip_mipi_csi_probe()
1269 csi->pdata = of_device_get_match_data(dev); in rockchip_mipi_csi_probe()
1279 csi->regs = devm_ioremap_resource(dev, res); in rockchip_mipi_csi_probe()
1280 if (IS_ERR(csi->regs)) in rockchip_mipi_csi_probe()
1281 return PTR_ERR(csi->regs); in rockchip_mipi_csi_probe()
1282 csi->regs_len = resource_size(res); in rockchip_mipi_csi_probe()
1283 csi->regsbak = NULL; in rockchip_mipi_csi_probe()
1288 csi->test_code_regs = devm_ioremap_resource(dev, res); in rockchip_mipi_csi_probe()
1289 if (IS_ERR(csi->test_code_regs)) in rockchip_mipi_csi_probe()
1293 csi->irq = platform_get_irq(pdev, 0); in rockchip_mipi_csi_probe()
1294 if (csi->irq < 0) { in rockchip_mipi_csi_probe()
1296 return -EINVAL; in rockchip_mipi_csi_probe()
1299 csi->pclk = devm_clk_get(dev, "pclk"); in rockchip_mipi_csi_probe()
1300 if (IS_ERR(csi->pclk)) { in rockchip_mipi_csi_probe()
1301 ret = PTR_ERR(csi->pclk); in rockchip_mipi_csi_probe()
1306 csi->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); in rockchip_mipi_csi_probe()
1307 if (IS_ERR(csi->grf)) { in rockchip_mipi_csi_probe()
1309 csi->grf = NULL; in rockchip_mipi_csi_probe()
1312 for (i = 0; i < csi->pdata->rsts_num; i++) { in rockchip_mipi_csi_probe()
1314 devm_reset_control_get(dev, csi->pdata->rsts[i]); in rockchip_mipi_csi_probe()
1316 dev_err(dev, "failed to get %s\n", csi->pdata->rsts[i]); in rockchip_mipi_csi_probe()
1319 csi->tx_rsts[i] = rst; in rockchip_mipi_csi_probe()
1326 ret = devm_request_irq(dev, csi->irq, rockchip_mipi_csi_irq_handler, in rockchip_mipi_csi_probe()
1333 csi->dsi_host.ops = &rockchip_mipi_csi_host_ops; in rockchip_mipi_csi_probe()
1334 csi->dsi_host.dev = dev; in rockchip_mipi_csi_probe()
1336 ret = mipi_dsi_host_register(&csi->dsi_host); in rockchip_mipi_csi_probe()
1342 mipi_dsi_host_unregister(&csi->dsi_host); in rockchip_mipi_csi_probe()
1344 if (!of_property_read_u32(np, "csi-tx-bypass-mode", &val)) in rockchip_mipi_csi_probe()
1345 csi->path_mode = val; in rockchip_mipi_csi_probe()
1352 struct rockchip_mipi_csi *csi = dev_get_drvdata(&pdev->dev); in rockchip_mipi_csi_remove()
1355 mipi_dsi_host_unregister(&csi->dsi_host); in rockchip_mipi_csi_remove()
1356 component_del(&pdev->dev, &rockchip_mipi_csi_ops); in rockchip_mipi_csi_remove()
1385 { .compatible = "rockchip,rk1808-mipi-csi", .data = &rk1808_socdata, },
1401 MODULE_AUTHOR("Sandy huang <hjc@rock-chips.com>");