Lines Matching +full:dphy +full:- +full:ref
17 #include <linux/clk-provider.h>
280 regmap_update_bits(inno->regmap, reg, mask, val); in inno_update_bits()
327 switch (inno->lanes) { in inno_mipi_dphy_lane_enable()
354 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv)); in inno_mipi_dphy_pll_enable()
356 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv >> 8)); in inno_mipi_dphy_pll_enable()
358 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv)); in inno_mipi_dphy_pll_enable()
380 timing->clkmiss = 0; in mipi_dphy_timing_get_default()
382 * The D-PHY spec define the clk post min time is 60ns + 52UI and in mipi_dphy_timing_get_default()
385 timing->clkpost = 200 + 52 * period / PSEC_PER_NSEC; in mipi_dphy_timing_get_default()
386 timing->clkpre = 8 * period / PSEC_PER_NSEC; in mipi_dphy_timing_get_default()
387 timing->clkprepare = 65; in mipi_dphy_timing_get_default()
388 timing->clksettle = 95; in mipi_dphy_timing_get_default()
389 timing->clktermen = 0; in mipi_dphy_timing_get_default()
390 timing->clktrail = 80; in mipi_dphy_timing_get_default()
391 timing->clkzero = 260; in mipi_dphy_timing_get_default()
392 timing->dtermen = 0; in mipi_dphy_timing_get_default()
393 timing->eot = 0; in mipi_dphy_timing_get_default()
394 timing->hsexit = 120; in mipi_dphy_timing_get_default()
395 timing->hsprepare = 65 + 4 * period / PSEC_PER_NSEC; in mipi_dphy_timing_get_default()
396 timing->hszero = 145 + 6 * period / PSEC_PER_NSEC; in mipi_dphy_timing_get_default()
397 timing->hssettle = 85 + 6 * period / PSEC_PER_NSEC; in mipi_dphy_timing_get_default()
398 timing->hsskip = 40; in mipi_dphy_timing_get_default()
399 timing->hstrail = max(8 * period / PSEC_PER_NSEC, in mipi_dphy_timing_get_default()
401 timing->init = 100000; in mipi_dphy_timing_get_default()
402 timing->lpx = 60; in mipi_dphy_timing_get_default()
403 timing->taget = 5 * timing->lpx; in mipi_dphy_timing_get_default()
404 timing->tago = 4 * timing->lpx; in mipi_dphy_timing_get_default()
405 timing->tasure = 2 * timing->lpx; in mipi_dphy_timing_get_default()
406 timing->wakeup = 1000000; in mipi_dphy_timing_get_default()
414 unsigned int lane_mbps = inno->lane_rate / USEC_PER_SEC; in inno_mipi_dphy_get_timing()
425 --i; in inno_mipi_dphy_get_timing()
442 txbyteclk = inno->lane_rate / 8; in inno_mipi_dphy_timing_init()
443 sys_clk = clk_get_rate(inno->pclk); in inno_mipi_dphy_timing_init()
446 ui = DIV_ROUND_CLOSEST_ULL(PSECS_PER_SEC, inno->lane_rate); in inno_mipi_dphy_timing_init()
448 dev_dbg(inno->dev, "txbyteclk=%ld, ui=%ld, sys_clk=%ld\n", in inno_mipi_dphy_timing_init()
466 lpx = timing->lpx; in inno_mipi_dphy_timing_init()
467 hs_prepare = timing->hs_prepare; in inno_mipi_dphy_timing_init()
468 hs_trail = timing->hs_trail; in inno_mipi_dphy_timing_init()
472 hs_zero = timing->clk_lane_hs_zero; in inno_mipi_dphy_timing_init()
474 hs_zero = timing->data_lane_hs_zero; in inno_mipi_dphy_timing_init()
476 dev_dbg(inno->dev, "lpx=%x\n", lpx); in inno_mipi_dphy_timing_init()
477 dev_dbg(inno->dev, in inno_mipi_dphy_timing_init()
480 dev_dbg(inno->dev, "clk_pre=%x, clk_post=%x\n", in inno_mipi_dphy_timing_init()
482 dev_dbg(inno->dev, "ta_go=%x, ta_sure=%x, ta_wait=%x\n", in inno_mipi_dphy_timing_init()
538 * PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2 in inno_mipi_dphy_pll_round_rate()
542 max_fout = 2 * timings[num_timings - 1].max_lane_mbps; in inno_mipi_dphy_pll_round_rate()
562 delta = abs(fout - tmp); in inno_mipi_dphy_pll_round_rate()
583 clk_prepare_enable(inno->pclk); in inno_mipi_dphy_power_on()
584 pm_runtime_get_sync(inno->dev); in inno_mipi_dphy_power_on()
604 pm_runtime_put(inno->dev); in inno_mipi_dphy_power_off()
605 clk_disable_unprepare(inno->pclk); in inno_mipi_dphy_power_off()
629 dev_dbg(inno->dev, "%s: fin=%lu, req_rate=%lu\n", in inno_mipi_dphy_pll_clk_round_rate()
631 dev_dbg(inno->dev, "%s: fout=%lu, prediv=%u, fbdiv=%u\n", in inno_mipi_dphy_pll_clk_round_rate()
634 inno->pll.prediv = prediv; in inno_mipi_dphy_pll_clk_round_rate()
635 inno->pll.fbdiv = fbdiv; in inno_mipi_dphy_pll_clk_round_rate()
646 dev_dbg(inno->dev, "%s: rate: %lu Hz\n", __func__, rate); in inno_mipi_dphy_pll_clk_set_rate()
648 inno->lane_rate = rate; in inno_mipi_dphy_pll_clk_set_rate()
658 dev_dbg(inno->dev, "%s: rate: %lu Hz\n", __func__, inno->lane_rate); in inno_mipi_dphy_pll_clk_recalc_rate()
660 return inno->lane_rate; in inno_mipi_dphy_pll_clk_recalc_rate()
671 struct device *dev = inno->dev; in inno_mipi_dphy_pll_register()
672 struct device_node *np = dev->of_node; in inno_mipi_dphy_pll_register()
678 parent_name = __clk_get_name(inno->ref_clk); in inno_mipi_dphy_pll_register()
680 ret = of_property_read_string(np, "clock-output-names", &init.name); in inno_mipi_dphy_pll_register()
682 dev_err(dev, "Missing clock-output-names property: %d\n", ret); in inno_mipi_dphy_pll_register()
691 inno->pll.hw.init = &init; in inno_mipi_dphy_pll_register()
692 clk = devm_clk_register(dev, &inno->pll.hw); in inno_mipi_dphy_pll_register()
704 of_clk_del_provider(inno->dev->of_node); in inno_mipi_dphy_pll_unregister()
709 struct device *dev = inno->dev; in inno_mipi_dphy_parse_dt()
711 if (of_property_read_u32(dev->of_node, "inno,lanes", &inno->lanes)) in inno_mipi_dphy_parse_dt()
712 inno->lanes = 4; in inno_mipi_dphy_parse_dt()
726 struct device *dev = &pdev->dev; in inno_mipi_dphy_probe()
736 return -ENOMEM; in inno_mipi_dphy_probe()
738 inno->dev = dev; in inno_mipi_dphy_probe()
752 inno->regmap = devm_regmap_init_mmio(dev, regs, in inno_mipi_dphy_probe()
754 if (IS_ERR(inno->regmap)) { in inno_mipi_dphy_probe()
755 ret = PTR_ERR(inno->regmap); in inno_mipi_dphy_probe()
760 inno->ref_clk = devm_clk_get(dev, "ref"); in inno_mipi_dphy_probe()
761 if (IS_ERR(inno->ref_clk)) { in inno_mipi_dphy_probe()
763 return PTR_ERR(inno->ref_clk); in inno_mipi_dphy_probe()
766 inno->pclk = devm_clk_get(dev, "pclk"); in inno_mipi_dphy_probe()
767 if (IS_ERR(inno->pclk)) { in inno_mipi_dphy_probe()
769 return PTR_ERR(inno->pclk); in inno_mipi_dphy_probe()
772 inno->rst = devm_reset_control_get(dev, "apb"); in inno_mipi_dphy_probe()
773 if (IS_ERR(inno->rst)) { in inno_mipi_dphy_probe()
775 return PTR_ERR(inno->rst); in inno_mipi_dphy_probe()
778 inno->grf = syscon_regmap_lookup_by_phandle(dev->of_node, in inno_mipi_dphy_probe()
780 if (IS_ERR(inno->grf)) { in inno_mipi_dphy_probe()
782 return PTR_ERR(inno->grf); in inno_mipi_dphy_probe()
787 dev_err(dev, "failed to create MIPI D-PHY\n"); in inno_mipi_dphy_probe()
813 pm_runtime_disable(inno->dev); in inno_mipi_dphy_remove()
819 { .compatible = "rockchip,rk1808-mipi-dphy", },
820 { .compatible = "rockchip,rk3568-mipi-dphy", },
821 { .compatible = "rockchip,rv1126-mipi-dphy", },
828 .name = "inno-mipi-dphy",
851 MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
852 MODULE_DESCRIPTION("Innosilicon MIPI D-PHY Driver");