1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
4 *
5 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/clk.h>
10 #include <linux/iopoll.h>
11 #include <linux/clk-provider.h>
12 #include <linux/delay.h>
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/of_device.h>
16 #include <linux/platform_device.h>
17 #include <linux/reset.h>
18 #include <linux/phy/phy.h>
19 #include <linux/phy/phy-mipi-dphy.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/mfd/syscon.h>
22 #include <linux/rockchip/cpu.h>
23
24 #define PSEC_PER_SEC 1000000000000LL
25
26 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
27
28 /*
29 * The offset address[7:0] is distributed two parts, one from the bit7 to bit5
30 * is the first address, the other from the bit4 to bit0 is the second address.
31 * when you configure the registers, you must set both of them. The Clock Lane
32 * and Data Lane use the same registers with the same second address, but the
33 * first address is different.
34 */
35 #define FIRST_ADDRESS(x) (((x) & 0x7) << 5)
36 #define SECOND_ADDRESS(x) (((x) & 0x1f) << 0)
37 #define PHY_REG(first, second) (FIRST_ADDRESS(first) | \
38 SECOND_ADDRESS(second))
39
40 /* Analog Register Part: reg00 */
41 #define BANDGAP_POWER_MASK BIT(7)
42 #define BANDGAP_POWER_DOWN BIT(7)
43 #define BANDGAP_POWER_ON 0
44 #define LANE_EN_MASK GENMASK(6, 2)
45 #define LANE_EN_CK BIT(6)
46 #define LANE_EN_3 BIT(5)
47 #define LANE_EN_2 BIT(4)
48 #define LANE_EN_1 BIT(3)
49 #define LANE_EN_0 BIT(2)
50 #define POWER_WORK_MASK GENMASK(1, 0)
51 #define POWER_WORK_ENABLE UPDATE(1, 1, 0)
52 #define POWER_WORK_DISABLE UPDATE(2, 1, 0)
53 /* Analog Register Part: reg01 */
54 #define REG_SYNCRST_MASK BIT(2)
55 #define REG_SYNCRST_RESET BIT(2)
56 #define REG_SYNCRST_NORMAL 0
57 #define REG_LDOPD_MASK BIT(1)
58 #define REG_LDOPD_POWER_DOWN BIT(1)
59 #define REG_LDOPD_POWER_ON 0
60 #define REG_PLLPD_MASK BIT(0)
61 #define REG_PLLPD_POWER_DOWN BIT(0)
62 #define REG_PLLPD_POWER_ON 0
63 /* Analog Register Part: reg03 */
64 #define REG_FBDIV_HI_MASK BIT(5)
65 #define REG_FBDIV_HI(x) UPDATE((x >> 8), 5, 5)
66 #define REG_PREDIV_MASK GENMASK(4, 0)
67 #define REG_PREDIV(x) UPDATE(x, 4, 0)
68 /* Analog Register Part: reg04 */
69 #define REG_FBDIV_LO_MASK GENMASK(7, 0)
70 #define REG_FBDIV_LO(x) UPDATE(x, 7, 0)
71 /* Analog Register Part: reg05 */
72 #define SAMPLE_CLOCK_PHASE_MASK GENMASK(6, 4)
73 #define SAMPLE_CLOCK_PHASE(x) UPDATE(x, 6, 4)
74 #define CLOCK_LANE_SKEW_PHASE_MASK GENMASK(2, 0)
75 #define CLOCK_LANE_SKEW_PHASE(x) UPDATE(x, 2, 0)
76 /* Analog Register Part: reg06 */
77 #define DATA_LANE_3_SKEW_PHASE_MASK GENMASK(6, 4)
78 #define DATA_LANE_3_SKEW_PHASE(x) UPDATE(x, 6, 4)
79 #define DATA_LANE_2_SKEW_PHASE_MASK GENMASK(2, 0)
80 #define DATA_LANE_2_SKEW_PHASE(x) UPDATE(x, 2, 0)
81 /* Analog Register Part: reg07 */
82 #define DATA_LANE_1_SKEW_PHASE_MASK GENMASK(6, 4)
83 #define DATA_LANE_1_SKEW_PHASE(x) UPDATE(x, 6, 4)
84 #define DATA_LANE_0_SKEW_PHASE_MASK GENMASK(2, 0)
85 #define DATA_LANE_0_SKEW_PHASE(x) UPDATE(x, 2, 0)
86 /* Analog Register Part: reg08 */
87 #define PRE_EMPHASIS_ENABLE_MASK BIT(7)
88 #define PRE_EMPHASIS_ENABLE BIT(7)
89 #define PRE_EMPHASIS_DISABLE 0
90 #define PLL_POST_DIV_ENABLE_MASK BIT(5)
91 #define PLL_POST_DIV_ENABLE BIT(5)
92 #define PLL_POST_DIV_DISABLE 0
93 #define DATA_LANE_VOD_RANGE_SET_MASK GENMASK(3, 0)
94 #define DATA_LANE_VOD_RANGE_SET(x) UPDATE(x, 3, 0)
95 #define SAMPLE_CLOCK_DIRECTION_MASK BIT(4)
96 #define SAMPLE_CLOCK_DIRECTION_REVERSE BIT(4)
97 #define SAMPLE_CLOCK_DIRECTION_FORWARD 0
98 #define LOWFRE_EN_MASK BIT(5)
99 #define PLL_OUTPUT_FREQUENCY_DIV_BY_1 0
100 #define PLL_OUTPUT_FREQUENCY_DIV_BY_2 1
101 /* Analog Register Part: reg1e */
102 #define PLL_MODE_SEL_MASK GENMASK(6, 5)
103 #define PLL_MODE_SEL_LVDS_MODE 0
104 #define PLL_MODE_SEL_MIPI_MODE BIT(5)
105 /* Analog Register Part: reg0b */
106 #define CLOCK_LANE_VOD_RANGE_SET_MASK GENMASK(3, 0)
107 #define CLOCK_LANE_VOD_RANGE_SET(x) UPDATE(x, 3, 0)
108 #define VOD_MIN_RANGE 0x1
109 #define VOD_MID_RANGE 0x3
110 #define VOD_BIG_RANGE 0x7
111 #define VOD_MAX_RANGE 0xf
112 /* Digital Register Part: reg00 */
113 #define REG_DIG_RSTN_MASK BIT(0)
114 #define REG_DIG_RSTN_NORMAL BIT(0)
115 #define REG_DIG_RSTN_RESET 0
116 /* Digital Register Part: reg01 */
117 #define INVERT_TXCLKESC_MASK BIT(1)
118 #define INVERT_TXCLKESC_ENABLE BIT(1)
119 #define INVERT_TXCLKESC_DISABLE 0
120 #define INVERT_TXBYTECLKHS_MASK BIT(0)
121 #define INVERT_TXBYTECLKHS_ENABLE BIT(0)
122 #define INVERT_TXBYTECLKHS_DISABLE 0
123 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg05 */
124 #define T_LPX_CNT_MASK GENMASK(5, 0)
125 #define T_LPX_CNT(x) UPDATE(x, 5, 0)
126 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg06 */
127 #define T_HS_ZERO_CNT_HI_MASK BIT(7)
128 #define T_HS_ZERO_CNT_HI(x) UPDATE(x, 7, 7)
129 #define T_HS_PREPARE_CNT_MASK GENMASK(6, 0)
130 #define T_HS_PREPARE_CNT(x) UPDATE(x, 6, 0)
131 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg07 */
132 #define T_HS_ZERO_CNT_LO_MASK GENMASK(5, 0)
133 #define T_HS_ZERO_CNT_LO(x) UPDATE(x, 5, 0)
134 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg08 */
135 #define T_HS_TRAIL_CNT_MASK GENMASK(6, 0)
136 #define T_HS_TRAIL_CNT(x) UPDATE(x, 6, 0)
137 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg09 */
138 #define T_HS_EXIT_CNT_LO_MASK GENMASK(4, 0)
139 #define T_HS_EXIT_CNT_LO(x) UPDATE(x, 4, 0)
140 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0a */
141 #define T_CLK_POST_CNT_LO_MASK GENMASK(3, 0)
142 #define T_CLK_POST_CNT_LO(x) UPDATE(x, 3, 0)
143 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0c */
144 #define LPDT_TX_PPI_SYNC_MASK BIT(2)
145 #define LPDT_TX_PPI_SYNC_ENABLE BIT(2)
146 #define LPDT_TX_PPI_SYNC_DISABLE 0
147 #define T_WAKEUP_CNT_HI_MASK GENMASK(1, 0)
148 #define T_WAKEUP_CNT_HI(x) UPDATE(x, 1, 0)
149 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0d */
150 #define T_WAKEUP_CNT_LO_MASK GENMASK(7, 0)
151 #define T_WAKEUP_CNT_LO(x) UPDATE(x, 7, 0)
152 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0e */
153 #define T_CLK_PRE_CNT_MASK GENMASK(3, 0)
154 #define T_CLK_PRE_CNT(x) UPDATE(x, 3, 0)
155 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg10 */
156 #define T_CLK_POST_HI_MASK GENMASK(7, 6)
157 #define T_CLK_POST_HI(x) UPDATE(x, 7, 6)
158 #define T_TA_GO_CNT_MASK GENMASK(5, 0)
159 #define T_TA_GO_CNT(x) UPDATE(x, 5, 0)
160 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg11 */
161 #define T_HS_EXIT_CNT_HI_MASK BIT(6)
162 #define T_HS_EXIT_CNT_HI(x) UPDATE(x, 6, 6)
163 #define T_TA_SURE_CNT_MASK GENMASK(5, 0)
164 #define T_TA_SURE_CNT(x) UPDATE(x, 5, 0)
165 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg12 */
166 #define T_TA_WAIT_CNT_MASK GENMASK(5, 0)
167 #define T_TA_WAIT_CNT(x) UPDATE(x, 5, 0)
168 /* LVDS Register Part: reg00 */
169 #define LVDS_DIGITAL_INTERNAL_RESET_MASK BIT(2)
170 #define LVDS_DIGITAL_INTERNAL_RESET_DISABLE BIT(2)
171 #define LVDS_DIGITAL_INTERNAL_RESET_ENABLE 0
172 /* LVDS Register Part: reg01 */
173 #define LVDS_DIGITAL_INTERNAL_ENABLE_MASK BIT(7)
174 #define LVDS_DIGITAL_INTERNAL_ENABLE BIT(7)
175 #define LVDS_DIGITAL_INTERNAL_DISABLE 0
176 /* LVDS Register Part: reg03 */
177 #define MODE_ENABLE_MASK GENMASK(2, 0)
178 #define TTL_MODE_ENABLE BIT(2)
179 #define LVDS_MODE_ENABLE BIT(1)
180 #define MIPI_MODE_ENABLE BIT(0)
181 /* LVDS Register Part: reg0b */
182 #define LVDS_LANE_EN_MASK GENMASK(7, 3)
183 #define LVDS_DATA_LANE0_EN BIT(7)
184 #define LVDS_DATA_LANE1_EN BIT(6)
185 #define LVDS_DATA_LANE2_EN BIT(5)
186 #define LVDS_DATA_LANE3_EN BIT(4)
187 #define LVDS_CLK_LANE_EN BIT(3)
188 #define LVDS_PLL_POWER_MASK BIT(2)
189 #define LVDS_PLL_POWER_OFF BIT(2)
190 #define LVDS_PLL_POWER_ON 0
191 #define LVDS_BANDGAP_POWER_MASK BIT(0)
192 #define LVDS_BANDGAP_POWER_DOWN BIT(0)
193 #define LVDS_BANDGAP_POWER_ON 0
194
195 #define DSI_PHY_RSTZ 0xa0
196 #define PHY_ENABLECLK BIT(2)
197 #define DSI_PHY_STATUS 0xb0
198 #define PHY_LOCK BIT(0)
199
200 enum soc_type {
201 PX30,
202 PX30S,
203 RK3128,
204 RK3368,
205 RK3562,
206 RK3568,
207 RV1126,
208 };
209
210 enum phy_max_rate {
211 MAX_1GHZ,
212 MAX_2_5GHZ,
213 };
214
215 struct inno_mipi_dphy_timing {
216 unsigned int max_lane_mbps;
217 u8 lpx;
218 u8 hs_prepare;
219 u8 clk_lane_hs_zero;
220 u8 data_lane_hs_zero;
221 u8 hs_trail;
222 };
223
224 struct inno_dsidphy {
225 struct device *dev;
226 struct clk *ref_clk;
227 struct clk *pclk_phy;
228 struct clk *pclk_host;
229 void __iomem *phy_base;
230 void __iomem *host_base;
231 struct reset_control *rst;
232 struct phy_configure_opts_mipi_dphy dphy_cfg;
233 unsigned int lanes;
234 const struct inno_dsidphy_plat_data *pdata;
235
236 struct clk *pll_clk;
237 struct {
238 struct clk_hw hw;
239 u8 prediv;
240 u16 fbdiv;
241 unsigned long rate;
242 } pll;
243 };
244
245 struct inno_dsidphy_plat_data {
246 enum soc_type soc_type;
247 const struct inno_mipi_dphy_timing *inno_mipi_dphy_timing_table;
248 const unsigned int num_timings;
249 enum phy_max_rate max_rate;
250 };
251
252 enum {
253 REGISTER_PART_ANALOG,
254 REGISTER_PART_DIGITAL,
255 REGISTER_PART_CLOCK_LANE,
256 REGISTER_PART_DATA0_LANE,
257 REGISTER_PART_DATA1_LANE,
258 REGISTER_PART_DATA2_LANE,
259 REGISTER_PART_DATA3_LANE,
260 REGISTER_PART_LVDS,
261 };
262
263 static const
264 struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1GHz[] = {
265 { 110, 0x0, 0x20, 0x16, 0x02, 0x22},
266 { 150, 0x0, 0x06, 0x16, 0x03, 0x45},
267 { 200, 0x0, 0x18, 0x17, 0x04, 0x0b},
268 { 250, 0x0, 0x05, 0x17, 0x05, 0x16},
269 { 300, 0x0, 0x51, 0x18, 0x06, 0x2c},
270 { 400, 0x0, 0x64, 0x19, 0x07, 0x33},
271 { 500, 0x0, 0x20, 0x1b, 0x07, 0x4e},
272 { 600, 0x0, 0x6a, 0x1d, 0x08, 0x3a},
273 { 700, 0x0, 0x3e, 0x1e, 0x08, 0x6a},
274 { 800, 0x0, 0x21, 0x1f, 0x09, 0x29},
275 {1000, 0x0, 0x09, 0x20, 0x09, 0x27},
276 };
277
278 static const
279 struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_2_5GHz[] = {
280 { 110, 0x02, 0x7f, 0x16, 0x02, 0x02},
281 { 150, 0x02, 0x7f, 0x16, 0x03, 0x02},
282 { 200, 0x02, 0x7f, 0x17, 0x04, 0x02},
283 { 250, 0x02, 0x7f, 0x17, 0x05, 0x04},
284 { 300, 0x02, 0x7f, 0x18, 0x06, 0x04},
285 { 400, 0x03, 0x7e, 0x19, 0x07, 0x04},
286 { 500, 0x03, 0x7c, 0x1b, 0x07, 0x08},
287 { 600, 0x03, 0x70, 0x1d, 0x08, 0x10},
288 { 700, 0x05, 0x40, 0x1e, 0x08, 0x30},
289 { 800, 0x05, 0x02, 0x1f, 0x09, 0x30},
290 {1000, 0x05, 0x08, 0x20, 0x09, 0x30},
291 {1200, 0x06, 0x03, 0x32, 0x14, 0x0f},
292 {1400, 0x09, 0x03, 0x32, 0x14, 0x0f},
293 {1600, 0x0d, 0x42, 0x36, 0x0e, 0x0f},
294 {1800, 0x0e, 0x47, 0x7a, 0x0e, 0x0f},
295 {2000, 0x11, 0x64, 0x7a, 0x0e, 0x0b},
296 {2200, 0x13, 0x64, 0x7e, 0x15, 0x0b},
297 {2400, 0x13, 0x33, 0x7f, 0x15, 0x6a},
298 {2500, 0x15, 0x54, 0x7f, 0x15, 0x6a},
299 };
300
hw_to_inno(struct clk_hw * hw)301 static inline struct inno_dsidphy *hw_to_inno(struct clk_hw *hw)
302 {
303 return container_of(hw, struct inno_dsidphy, pll.hw);
304 }
305
phy_update_bits(struct inno_dsidphy * inno,u8 first,u8 second,u8 mask,u8 val)306 static void phy_update_bits(struct inno_dsidphy *inno,
307 u8 first, u8 second, u8 mask, u8 val)
308 {
309 u32 reg = PHY_REG(first, second) << 2;
310 unsigned int tmp, orig;
311
312 orig = readl(inno->phy_base + reg);
313 tmp = orig & ~mask;
314 tmp |= val & mask;
315 writel(tmp, inno->phy_base + reg);
316 }
317
host_update_bits(struct inno_dsidphy * inno,u32 reg,u32 mask,u32 val)318 static void host_update_bits(struct inno_dsidphy *inno,
319 u32 reg, u32 mask, u32 val)
320 {
321 unsigned int tmp, orig;
322
323 orig = readl(inno->host_base + reg);
324 tmp = orig & ~mask;
325 tmp |= val & mask;
326 writel(tmp, inno->host_base + reg);
327 }
328
inno_dsidphy_pll_calc_rate(struct inno_dsidphy * inno,unsigned long rate)329 static unsigned long inno_dsidphy_pll_calc_rate(struct inno_dsidphy *inno,
330 unsigned long rate)
331 {
332 unsigned long prate = clk_get_rate(inno->ref_clk);
333 unsigned long best_freq = 0;
334 unsigned long fref, fout;
335 u8 min_prediv, max_prediv;
336 u8 _prediv, best_prediv = 1;
337 u16 _fbdiv, best_fbdiv = 1;
338 u32 min_delta = UINT_MAX;
339
340 /*
341 * The PLL output frequency can be calculated using a simple formula:
342 * PLL_Output_Frequency = (FREF / PREDIV * FBDIV) / 2
343 * PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2
344 */
345 fref = prate / 2;
346 if (rate > 1000000000UL)
347 fout = 1000000000UL;
348 else
349 fout = rate;
350
351 /* 5Mhz < Fref / prediv < 40MHz */
352 min_prediv = DIV_ROUND_UP(fref, 40000000);
353 max_prediv = fref / 5000000;
354
355 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
356 u64 tmp;
357 u32 delta;
358
359 tmp = (u64)fout * _prediv;
360 do_div(tmp, fref);
361 _fbdiv = tmp;
362
363 /*
364 * The possible settings of feedback divider are
365 * 12, 13, 14, 16, ~ 511
366 */
367 if (_fbdiv == 15)
368 continue;
369
370 if (_fbdiv < 12 || _fbdiv > 511)
371 continue;
372
373 tmp = (u64)_fbdiv * fref;
374 do_div(tmp, _prediv);
375
376 delta = abs(fout - tmp);
377 if (!delta) {
378 best_prediv = _prediv;
379 best_fbdiv = _fbdiv;
380 best_freq = tmp;
381 break;
382 } else if (delta < min_delta) {
383 best_prediv = _prediv;
384 best_fbdiv = _fbdiv;
385 best_freq = tmp;
386 min_delta = delta;
387 }
388 }
389
390 if (best_freq) {
391 inno->pll.prediv = best_prediv;
392 inno->pll.fbdiv = best_fbdiv;
393 inno->pll.rate = best_freq;
394 }
395
396 return best_freq;
397 }
398
399 static const struct inno_mipi_dphy_timing *
inno_mipi_dphy_get_timing(struct inno_dsidphy * inno)400 inno_mipi_dphy_get_timing(struct inno_dsidphy *inno)
401 {
402 const struct inno_mipi_dphy_timing *timings;
403 unsigned int num_timings;
404 unsigned int lane_mbps = inno->pll.rate / USEC_PER_SEC;
405 unsigned int i;
406
407 timings = inno->pdata->inno_mipi_dphy_timing_table;
408 num_timings = inno->pdata->num_timings;
409
410 for (i = 0; i < num_timings; i++)
411 if (lane_mbps <= timings[i].max_lane_mbps)
412 break;
413
414 if (i == num_timings)
415 --i;
416
417 return &timings[i];
418 }
419
inno_mipi_dphy_max_2_5GHz_pll_enable(struct inno_dsidphy * inno)420 static void inno_mipi_dphy_max_2_5GHz_pll_enable(struct inno_dsidphy *inno)
421 {
422
423 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
424 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv));
425 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
426 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv));
427 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
428 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv));
429 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
430 PLL_POST_DIV_ENABLE_MASK, PLL_POST_DIV_ENABLE);
431 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b,
432 CLOCK_LANE_VOD_RANGE_SET_MASK,
433 CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE));
434 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
435 REG_LDOPD_MASK | REG_PLLPD_MASK,
436 REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON);
437 }
438
inno_mipi_dphy_max_1GHz_pll_enable(struct inno_dsidphy * inno)439 static void inno_mipi_dphy_max_1GHz_pll_enable(struct inno_dsidphy *inno)
440 {
441 /* Configure PLL */
442 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
443 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv));
444 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
445 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv));
446 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
447 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv));
448 /* Enable PLL and LDO */
449 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
450 REG_LDOPD_MASK | REG_PLLPD_MASK,
451 REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON);
452 }
453
inno_mipi_dphy_reset(struct inno_dsidphy * inno)454 static void inno_mipi_dphy_reset(struct inno_dsidphy *inno)
455 {
456 /* Reset analog */
457 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
458 REG_SYNCRST_MASK, REG_SYNCRST_RESET);
459 udelay(1);
460 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
461 REG_SYNCRST_MASK, REG_SYNCRST_NORMAL);
462 /* Reset digital */
463 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
464 REG_DIG_RSTN_MASK, REG_DIG_RSTN_RESET);
465 udelay(1);
466 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
467 REG_DIG_RSTN_MASK, REG_DIG_RSTN_NORMAL);
468 }
469
inno_mipi_dphy_timing_init(struct inno_dsidphy * inno)470 static void inno_mipi_dphy_timing_init(struct inno_dsidphy *inno)
471 {
472 struct phy_configure_opts_mipi_dphy *cfg = &inno->dphy_cfg;
473 u32 t_txbyteclkhs, t_txclkesc;
474 u32 txbyteclkhs, txclkesc, esc_clk_div;
475 u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait;
476 u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero;
477 const struct inno_mipi_dphy_timing *timing;
478 unsigned int i;
479
480 txbyteclkhs = inno->pll.rate / 8;
481 t_txbyteclkhs = div_u64(PSEC_PER_SEC, txbyteclkhs);
482
483 esc_clk_div = DIV_ROUND_UP(txbyteclkhs, 20000000);
484 txclkesc = txbyteclkhs / esc_clk_div;
485 t_txclkesc = div_u64(PSEC_PER_SEC, txclkesc);
486
487 /*
488 * The value of counter for HS Ths-exit
489 * Ths-exit = Tpin_txbyteclkhs * value
490 */
491 hs_exit = DIV_ROUND_UP(cfg->hs_exit, t_txbyteclkhs);
492 /*
493 * The value of counter for HS Tclk-post
494 * Tclk-post = Tpin_txbyteclkhs * value
495 */
496 clk_post = DIV_ROUND_UP(cfg->clk_post, t_txbyteclkhs);
497 /*
498 * The value of counter for HS Tclk-pre
499 * Tclk-pre = Tpin_txbyteclkhs * value
500 */
501 clk_pre = DIV_ROUND_UP(cfg->clk_pre, t_txbyteclkhs);
502 /*
503 * The value of counter for HS Tta-go
504 * Tta-go for turnaround
505 * Tta-go = Ttxclkesc * value
506 */
507 ta_go = DIV_ROUND_UP(cfg->ta_go, t_txclkesc);
508 /*
509 * The value of counter for HS Tta-sure
510 * Tta-sure for turnaround
511 * Tta-sure = Ttxclkesc * value
512 */
513 ta_sure = DIV_ROUND_UP(cfg->ta_sure, t_txclkesc);
514 /*
515 * The value of counter for HS Tta-wait
516 * Tta-wait for turnaround
517 * Tta-wait = Ttxclkesc * value
518 */
519 ta_wait = DIV_ROUND_UP(cfg->ta_get, t_txclkesc);
520
521 timing = inno_mipi_dphy_get_timing(inno);
522 /*
523 * The value of counter for HS Tlpx Time
524 * Tlpx = Tpin_txbyteclkhs * (2 + value)
525 */
526 if (inno->pdata->max_rate == MAX_1GHZ) {
527 lpx = DIV_ROUND_UP(cfg->lpx, t_txbyteclkhs);
528 if (lpx >= 2)
529 lpx -= 2;
530 } else
531 lpx = timing->lpx;
532
533 hs_prepare = timing->hs_prepare;
534 hs_trail = timing->hs_trail;
535 clk_lane_hs_zero = timing->clk_lane_hs_zero;
536 data_lane_hs_zero = timing->data_lane_hs_zero;
537 wakeup = 0x3ff;
538
539 for (i = REGISTER_PART_CLOCK_LANE; i <= REGISTER_PART_DATA3_LANE; i++) {
540 if (i == REGISTER_PART_CLOCK_LANE)
541 hs_zero = clk_lane_hs_zero;
542 else
543 hs_zero = data_lane_hs_zero;
544
545 phy_update_bits(inno, i, 0x05, T_LPX_CNT_MASK,
546 T_LPX_CNT(lpx));
547 phy_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK,
548 T_HS_PREPARE_CNT(hs_prepare));
549
550 if (inno->pdata->max_rate == MAX_2_5GHZ)
551 phy_update_bits(inno, i, 0x06, T_HS_ZERO_CNT_HI_MASK,
552 T_HS_ZERO_CNT_HI(hs_zero >> 6));
553
554 phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_LO_MASK,
555 T_HS_ZERO_CNT_LO(hs_zero));
556 phy_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK,
557 T_HS_TRAIL_CNT(hs_trail));
558
559 if (inno->pdata->max_rate == MAX_2_5GHZ)
560 phy_update_bits(inno, i, 0x11, T_HS_EXIT_CNT_HI_MASK,
561 T_HS_EXIT_CNT_HI(hs_exit >> 5));
562
563 phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_LO_MASK,
564 T_HS_EXIT_CNT_LO(hs_exit));
565
566 if (inno->pdata->max_rate == MAX_2_5GHZ)
567 phy_update_bits(inno, i, 0x10, T_CLK_POST_HI_MASK,
568 T_CLK_POST_HI(clk_post >> 4));
569
570 phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_LO_MASK,
571 T_CLK_POST_CNT_LO(clk_post));
572 phy_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK,
573 T_CLK_PRE_CNT(clk_pre));
574 phy_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK,
575 T_WAKEUP_CNT_HI(wakeup >> 8));
576 phy_update_bits(inno, i, 0x0d, T_WAKEUP_CNT_LO_MASK,
577 T_WAKEUP_CNT_LO(wakeup));
578 phy_update_bits(inno, i, 0x10, T_TA_GO_CNT_MASK,
579 T_TA_GO_CNT(ta_go));
580 phy_update_bits(inno, i, 0x11, T_TA_SURE_CNT_MASK,
581 T_TA_SURE_CNT(ta_sure));
582 phy_update_bits(inno, i, 0x12, T_TA_WAIT_CNT_MASK,
583 T_TA_WAIT_CNT(ta_wait));
584 }
585 }
586
inno_mipi_dphy_lane_enable(struct inno_dsidphy * inno)587 static void inno_mipi_dphy_lane_enable(struct inno_dsidphy *inno)
588 {
589 u8 val = LANE_EN_CK;
590
591 switch (inno->lanes) {
592 case 1:
593 val |= LANE_EN_0;
594 break;
595 case 2:
596 val |= LANE_EN_1 | LANE_EN_0;
597 break;
598 case 3:
599 val |= LANE_EN_2 | LANE_EN_1 | LANE_EN_0;
600 break;
601 case 4:
602 default:
603 val |= LANE_EN_3 | LANE_EN_2 | LANE_EN_1 | LANE_EN_0;
604 break;
605 }
606
607 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, val);
608 }
609
inno_dsidphy_mipi_mode_enable(struct inno_dsidphy * inno)610 static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno)
611 {
612 /* Select MIPI mode */
613 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
614 MODE_ENABLE_MASK, MIPI_MODE_ENABLE);
615
616 /* set pin_txclkesc_0 pin_txbyteclk invert disable */
617 if (inno->pdata->soc_type == PX30S)
618 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x01,
619 INVERT_TXCLKESC_MASK, INVERT_TXCLKESC_DISABLE);
620
621 if (inno->pdata->max_rate == MAX_2_5GHZ)
622 inno_mipi_dphy_max_2_5GHz_pll_enable(inno);
623 else
624 inno_mipi_dphy_max_1GHz_pll_enable(inno);
625
626 inno_mipi_dphy_reset(inno);
627 inno_mipi_dphy_timing_init(inno);
628 inno_mipi_dphy_lane_enable(inno);
629 inno_mipi_dphy_lane_enable(inno);
630 }
631
inno_dsidphy_lvds_mode_enable(struct inno_dsidphy * inno)632 static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno)
633 {
634 u8 prediv = 2;
635 u16 fbdiv = 28;
636
637 /* Sample clock reverse direction */
638 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
639 SAMPLE_CLOCK_DIRECTION_MASK | LOWFRE_EN_MASK,
640 SAMPLE_CLOCK_DIRECTION_REVERSE |
641 PLL_OUTPUT_FREQUENCY_DIV_BY_1);
642
643 /* Reset LVDS digital logic */
644 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
645 LVDS_DIGITAL_INTERNAL_RESET_MASK,
646 LVDS_DIGITAL_INTERNAL_RESET_ENABLE);
647 udelay(1);
648 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
649 LVDS_DIGITAL_INTERNAL_RESET_MASK,
650 LVDS_DIGITAL_INTERNAL_RESET_DISABLE);
651
652 /* Select LVDS mode */
653 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
654 MODE_ENABLE_MASK, LVDS_MODE_ENABLE);
655 /* Configure PLL */
656 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
657 REG_PREDIV_MASK, REG_PREDIV(prediv));
658 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
659 REG_FBDIV_HI_MASK, REG_FBDIV_HI(fbdiv));
660 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
661 REG_FBDIV_LO_MASK, REG_FBDIV_LO(fbdiv));
662 phy_update_bits(inno, REGISTER_PART_LVDS, 0x08, 0xff, 0xfc);
663 /* Enable PLL and Bandgap */
664 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
665 LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK,
666 LVDS_PLL_POWER_ON | LVDS_BANDGAP_POWER_ON);
667
668 msleep(20);
669
670 /* Select PLL mode */
671 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1e,
672 PLL_MODE_SEL_MASK, PLL_MODE_SEL_LVDS_MODE);
673
674 /* Enable LVDS digital logic */
675 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
676 LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
677 LVDS_DIGITAL_INTERNAL_ENABLE);
678 /* Enable LVDS analog driver */
679 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
680 LVDS_LANE_EN_MASK, LVDS_CLK_LANE_EN |
681 LVDS_DATA_LANE0_EN | LVDS_DATA_LANE1_EN |
682 LVDS_DATA_LANE2_EN | LVDS_DATA_LANE3_EN);
683 }
684
inno_dsidphy_phy_ttl_mode_enable(struct inno_dsidphy * inno)685 static void inno_dsidphy_phy_ttl_mode_enable(struct inno_dsidphy *inno)
686 {
687 /* Reset digital logic */
688 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
689 LVDS_DIGITAL_INTERNAL_RESET_MASK,
690 LVDS_DIGITAL_INTERNAL_RESET_ENABLE);
691 udelay(1);
692 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
693 LVDS_DIGITAL_INTERNAL_RESET_MASK,
694 LVDS_DIGITAL_INTERNAL_RESET_DISABLE);
695
696 /* Select TTL mode */
697 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
698 MODE_ENABLE_MASK, TTL_MODE_ENABLE);
699
700 /* Enable digital logic */
701 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
702 LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
703 LVDS_DIGITAL_INTERNAL_ENABLE);
704 /* Enable analog driver */
705 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
706 LVDS_LANE_EN_MASK, LVDS_CLK_LANE_EN |
707 LVDS_DATA_LANE0_EN | LVDS_DATA_LANE1_EN |
708 LVDS_DATA_LANE2_EN | LVDS_DATA_LANE3_EN);
709 /* Enable for clk lane in TTL mode */
710 host_update_bits(inno, DSI_PHY_RSTZ, PHY_ENABLECLK, PHY_ENABLECLK);
711 }
712
inno_dsidphy_power_on(struct phy * phy)713 static int inno_dsidphy_power_on(struct phy *phy)
714 {
715 struct inno_dsidphy *inno = phy_get_drvdata(phy);
716 enum phy_mode mode = phy_get_mode(phy);
717
718 clk_prepare_enable(inno->pclk_phy);
719 clk_prepare_enable(inno->ref_clk);
720 pm_runtime_get_sync(inno->dev);
721
722 /* Bandgap power on */
723 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
724 BANDGAP_POWER_MASK, BANDGAP_POWER_ON);
725 /* Enable power work */
726 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
727 POWER_WORK_MASK, POWER_WORK_ENABLE);
728
729 switch (mode) {
730 case PHY_MODE_MIPI_DPHY:
731 inno_dsidphy_mipi_mode_enable(inno);
732 break;
733 case PHY_MODE_LVDS:
734 inno_dsidphy_lvds_mode_enable(inno);
735 break;
736 default:
737 inno_dsidphy_phy_ttl_mode_enable(inno);
738 }
739
740 return 0;
741 }
742
inno_dsidphy_power_off(struct phy * phy)743 static int inno_dsidphy_power_off(struct phy *phy)
744 {
745 struct inno_dsidphy *inno = phy_get_drvdata(phy);
746
747 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, 0);
748 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
749 REG_LDOPD_MASK | REG_PLLPD_MASK,
750 REG_LDOPD_POWER_DOWN | REG_PLLPD_POWER_DOWN);
751 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
752 POWER_WORK_MASK, POWER_WORK_DISABLE);
753 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
754 BANDGAP_POWER_MASK, BANDGAP_POWER_DOWN);
755
756 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, LVDS_LANE_EN_MASK, 0);
757 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
758 LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
759 LVDS_DIGITAL_INTERNAL_DISABLE);
760 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
761 LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK,
762 LVDS_PLL_POWER_OFF | LVDS_BANDGAP_POWER_DOWN);
763
764 pm_runtime_put(inno->dev);
765 clk_disable_unprepare(inno->ref_clk);
766 clk_disable_unprepare(inno->pclk_phy);
767
768 return 0;
769 }
770
inno_dsidphy_set_mode(struct phy * phy,enum phy_mode mode,int submode)771 static int inno_dsidphy_set_mode(struct phy *phy, enum phy_mode mode,
772 int submode)
773 {
774 return 0;
775 }
776
inno_dsidphy_configure(struct phy * phy,union phy_configure_opts * opts)777 static int inno_dsidphy_configure(struct phy *phy,
778 union phy_configure_opts *opts)
779 {
780 struct inno_dsidphy *inno = phy_get_drvdata(phy);
781 struct phy_configure_opts_mipi_dphy *cfg = &inno->dphy_cfg;
782 enum phy_mode mode = phy_get_mode(phy);
783 int ret;
784
785 if (mode != PHY_MODE_MIPI_DPHY)
786 return -EINVAL;
787
788 ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy);
789 if (ret)
790 return ret;
791
792 memcpy(&inno->dphy_cfg, &opts->mipi_dphy, sizeof(inno->dphy_cfg));
793
794 inno_dsidphy_pll_calc_rate(inno, cfg->hs_clk_rate);
795 cfg->hs_clk_rate = inno->pll.rate;
796 opts->mipi_dphy.hs_clk_rate = inno->pll.rate;
797
798 return 0;
799 }
800
inno_dsidphy_init(struct phy * phy)801 static int inno_dsidphy_init(struct phy *phy)
802 {
803 struct inno_dsidphy *inno = phy_get_drvdata(phy);
804
805 clk_prepare_enable(inno->pclk_phy);
806 clk_prepare_enable(inno->ref_clk);
807 pm_runtime_get_sync(inno->dev);
808
809 return 0;
810 }
811
inno_dsidphy_exit(struct phy * phy)812 static int inno_dsidphy_exit(struct phy *phy)
813 {
814 struct inno_dsidphy *inno = phy_get_drvdata(phy);
815
816 pm_runtime_put(inno->dev);
817 clk_disable_unprepare(inno->ref_clk);
818 clk_disable_unprepare(inno->pclk_phy);
819
820 return 0;
821 }
822
823 static const struct phy_ops inno_dsidphy_ops = {
824 .configure = inno_dsidphy_configure,
825 .set_mode = inno_dsidphy_set_mode,
826 .power_on = inno_dsidphy_power_on,
827 .power_off = inno_dsidphy_power_off,
828 .init = inno_dsidphy_init,
829 .exit = inno_dsidphy_exit,
830 .owner = THIS_MODULE,
831 };
832
833 static const struct inno_dsidphy_plat_data px30_video_phy_plat_data = {
834 .soc_type = PX30,
835 .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1GHz,
836 .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1GHz),
837 .max_rate = MAX_1GHZ,
838 };
839
840 static const struct inno_dsidphy_plat_data px30s_video_phy_plat_data = {
841 .soc_type = PX30S,
842 .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5GHz,
843 .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5GHz),
844 .max_rate = MAX_2_5GHZ,
845 };
846
847 static const struct inno_dsidphy_plat_data rk3128_video_phy_plat_data = {
848 .soc_type = RK3128,
849 .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1GHz,
850 .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1GHz),
851 .max_rate = MAX_1GHZ,
852 };
853
854 static const struct inno_dsidphy_plat_data rk3368_video_phy_plat_data = {
855 .soc_type = RK3368,
856 .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1GHz,
857 .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1GHz),
858 .max_rate = MAX_1GHZ,
859 };
860
861 static const struct inno_dsidphy_plat_data rk3562_video_phy_plat_data = {
862 .soc_type = RK3562,
863 .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5GHz,
864 .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5GHz),
865 .max_rate = MAX_2_5GHZ,
866 };
867
868 static const struct inno_dsidphy_plat_data rk3568_video_phy_plat_data = {
869 .soc_type = RK3568,
870 .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5GHz,
871 .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5GHz),
872 .max_rate = MAX_2_5GHZ,
873 };
874
875 static const struct inno_dsidphy_plat_data rv1126_video_phy_plat_data = {
876 .soc_type = RV1126,
877 .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5GHz,
878 .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5GHz),
879 .max_rate = MAX_2_5GHZ,
880 };
881
inno_dsidphy_probe(struct platform_device * pdev)882 static int inno_dsidphy_probe(struct platform_device *pdev)
883 {
884 struct device *dev = &pdev->dev;
885 struct inno_dsidphy *inno;
886 struct phy_provider *phy_provider;
887 struct phy *phy;
888 struct resource *res;
889 int ret;
890
891 inno = devm_kzalloc(dev, sizeof(*inno), GFP_KERNEL);
892 if (!inno)
893 return -ENOMEM;
894
895 inno->dev = dev;
896 inno->pdata = of_device_get_match_data(inno->dev);
897 if (soc_is_px30s())
898 inno->pdata = &px30s_video_phy_plat_data;
899
900 platform_set_drvdata(pdev, inno);
901
902 inno->phy_base = devm_platform_ioremap_resource_byname(pdev, "phy");
903 if (IS_ERR(inno->phy_base))
904 return PTR_ERR(inno->phy_base);
905
906 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "host");
907 if (!res) {
908 dev_err(dev, "invalid host resource\n");
909 return -EINVAL;
910 }
911
912 inno->host_base = devm_ioremap(dev, res->start, resource_size(res));
913 if (IS_ERR(inno->host_base))
914 return PTR_ERR(inno->host_base);
915
916 inno->ref_clk = devm_clk_get(dev, "ref");
917 if (IS_ERR(inno->ref_clk)) {
918 ret = PTR_ERR(inno->ref_clk);
919 dev_err(dev, "failed to get ref clock: %d\n", ret);
920 return ret;
921 }
922
923 inno->pclk_phy = devm_clk_get(dev, "pclk");
924 if (IS_ERR(inno->pclk_phy)) {
925 ret = PTR_ERR(inno->pclk_phy);
926 dev_err(dev, "failed to get phy pclk: %d\n", ret);
927 return ret;
928 }
929
930 inno->pclk_host = devm_clk_get(dev, "pclk_host");
931 if (IS_ERR(inno->pclk_host)) {
932 ret = PTR_ERR(inno->pclk_host);
933 dev_err(dev, "failed to get host pclk: %d\n", ret);
934 return ret;
935 }
936
937 inno->rst = devm_reset_control_get(dev, "apb");
938 if (IS_ERR(inno->rst)) {
939 ret = PTR_ERR(inno->rst);
940 dev_err(dev, "failed to get system reset control: %d\n", ret);
941 return ret;
942 }
943
944 phy = devm_phy_create(dev, NULL, &inno_dsidphy_ops);
945 if (IS_ERR(phy)) {
946 ret = PTR_ERR(phy);
947 dev_err(dev, "failed to create phy: %d\n", ret);
948 return ret;
949 }
950
951 if (of_property_read_u32(dev->of_node, "inno,lanes", &inno->lanes))
952 inno->lanes = 4;
953
954 phy_set_drvdata(phy, inno);
955
956 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
957 if (IS_ERR(phy_provider)) {
958 ret = PTR_ERR(phy_provider);
959 dev_err(dev, "failed to register phy provider: %d\n", ret);
960 return ret;
961 }
962
963 pm_runtime_enable(dev);
964
965 return 0;
966 }
967
inno_dsidphy_remove(struct platform_device * pdev)968 static int inno_dsidphy_remove(struct platform_device *pdev)
969 {
970 struct inno_dsidphy *inno = platform_get_drvdata(pdev);
971
972 pm_runtime_disable(inno->dev);
973
974 return 0;
975 }
976
977 static const struct of_device_id inno_dsidphy_of_match[] = {
978 {
979 .compatible = "rockchip,px30-dsi-dphy",
980 .data = &px30_video_phy_plat_data,
981 }, {
982 .compatible = "rockchip,px30s-dsi-dphy",
983 .data = &px30s_video_phy_plat_data,
984 }, {
985 .compatible = "rockchip,rk3128-dsi-dphy",
986 .data = &rk3128_video_phy_plat_data,
987 }, {
988 .compatible = "rockchip,rk3368-dsi-dphy",
989 .data = &rk3368_video_phy_plat_data,
990 }, {
991 .compatible = "rockchip,rk3562-dsi-dphy",
992 .data = &rk3562_video_phy_plat_data,
993 }, {
994 .compatible = "rockchip,rk3568-dsi-dphy",
995 .data = &rk3568_video_phy_plat_data,
996 }, {
997 .compatible = "rockchip,rv1126-mipi-dphy",
998 .data = &rv1126_video_phy_plat_data,
999 },
1000 {}
1001 };
1002 MODULE_DEVICE_TABLE(of, inno_dsidphy_of_match);
1003
1004 static struct platform_driver inno_dsidphy_driver = {
1005 .driver = {
1006 .name = "inno-dsidphy",
1007 .of_match_table = of_match_ptr(inno_dsidphy_of_match),
1008 },
1009 .probe = inno_dsidphy_probe,
1010 .remove = inno_dsidphy_remove,
1011 };
1012 module_platform_driver(inno_dsidphy_driver);
1013
1014 MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
1015 MODULE_DESCRIPTION("Innosilicon MIPI/LVDS/TTL Video Combo PHY driver");
1016 MODULE_LICENSE("GPL v2");
1017