1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author:
5 * Chris Zhong <zyw@rock-chips.com>
6 * Nickey Yang <nickey.yang@rock-chips.com>
7 */
8
9 #include <linux/clk.h>
10 #include <linux/iopoll.h>
11 #include <linux/math64.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/phy/phy.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18
19 #include <drm/drm_dsc.h>
20 #include <video/mipi_display.h>
21 #include <uapi/linux/videodev2.h>
22 #include <drm/bridge/dw_mipi_dsi.h>
23 #include <drm/drm_mipi_dsi.h>
24 #include <drm/drm_of.h>
25 #include <drm/drm_simple_kms_helper.h>
26
27 #include "rockchip_drm_drv.h"
28 #include "rockchip_drm_vop.h"
29
30 #define DSI_PHY_RSTZ 0xa0
31 #define PHY_DISFORCEPLL 0
32 #define PHY_ENFORCEPLL BIT(3)
33 #define PHY_DISABLECLK 0
34 #define PHY_ENABLECLK BIT(2)
35 #define PHY_RSTZ 0
36 #define PHY_UNRSTZ BIT(1)
37 #define PHY_SHUTDOWNZ 0
38 #define PHY_UNSHUTDOWNZ BIT(0)
39
40 #define DSI_PHY_IF_CFG 0xa4
41 #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
42 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8)
43
44 #define DSI_PHY_STATUS 0xb0
45 #define LOCK BIT(0)
46 #define STOP_STATE_CLK_LANE BIT(2)
47
48 #define DSI_PHY_TST_CTRL0 0xb4
49 #define PHY_TESTCLK BIT(1)
50 #define PHY_UNTESTCLK 0
51 #define PHY_TESTCLR BIT(0)
52 #define PHY_UNTESTCLR 0
53
54 #define DSI_PHY_TST_CTRL1 0xb8
55 #define PHY_TESTEN BIT(16)
56 #define PHY_UNTESTEN 0
57 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8)
58 #define PHY_TESTDIN(n) (((n) & 0xff) << 0)
59
60 #define DSI_INT_ST0 0xbc
61 #define DSI_INT_ST1 0xc0
62 #define DSI_INT_MSK0 0xc4
63 #define DSI_INT_MSK1 0xc8
64
65 #define PHY_STATUS_TIMEOUT_US 10000
66 #define CMD_PKT_STATUS_TIMEOUT_US 20000
67
68 #define BYPASS_VCO_RANGE BIT(7)
69 #define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3)
70 #define VCO_IN_CAP_CON_DEFAULT (0x0 << 1)
71 #define VCO_IN_CAP_CON_LOW (0x1 << 1)
72 #define VCO_IN_CAP_CON_HIGH (0x2 << 1)
73 #define REF_BIAS_CUR_SEL BIT(0)
74
75 #define CP_CURRENT_3UA 0x1
76 #define CP_CURRENT_4_5UA 0x2
77 #define CP_CURRENT_7_5UA 0x6
78 #define CP_CURRENT_6UA 0x9
79 #define CP_CURRENT_12UA 0xb
80 #define CP_CURRENT_SEL(val) ((val) & 0xf)
81 #define CP_PROGRAM_EN BIT(7)
82
83 #define LPF_RESISTORS_15_5KOHM 0x1
84 #define LPF_RESISTORS_13KOHM 0x2
85 #define LPF_RESISTORS_11_5KOHM 0x4
86 #define LPF_RESISTORS_10_5KOHM 0x8
87 #define LPF_RESISTORS_8KOHM 0x10
88 #define LPF_PROGRAM_EN BIT(6)
89 #define LPF_RESISTORS_SEL(val) ((val) & 0x3f)
90
91 #define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1)
92
93 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
94 #define LOW_PROGRAM_EN 0
95 #define HIGH_PROGRAM_EN BIT(7)
96 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
97 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf)
98 #define PLL_LOOP_DIV_EN BIT(5)
99 #define PLL_INPUT_DIV_EN BIT(4)
100
101 #define POWER_CONTROL BIT(6)
102 #define INTERNAL_REG_CURRENT BIT(3)
103 #define BIAS_BLOCK_ON BIT(2)
104 #define BANDGAP_ON BIT(0)
105
106 #define TER_RESISTOR_HIGH BIT(7)
107 #define TER_RESISTOR_LOW 0
108 #define LEVEL_SHIFTERS_ON BIT(6)
109 #define TER_CAL_DONE BIT(5)
110 #define SETRD_MAX (0x7 << 2)
111 #define POWER_MANAGE BIT(1)
112 #define TER_RESISTORS_ON BIT(0)
113
114 #define BIASEXTR_SEL(val) ((val) & 0x7)
115 #define BANDGAP_SEL(val) ((val) & 0x7)
116 #define TLP_PROGRAM_EN BIT(7)
117 #define THS_PRE_PROGRAM_EN BIT(7)
118 #define THS_ZERO_PROGRAM_EN BIT(6)
119
120 #define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL 0x10
121 #define PLL_CP_CONTROL_PLL_LOCK_BYPASS 0x11
122 #define PLL_LPF_AND_CP_CONTROL 0x12
123 #define PLL_INPUT_DIVIDER_RATIO 0x17
124 #define PLL_LOOP_DIVIDER_RATIO 0x18
125 #define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL 0x19
126 #define BANDGAP_AND_BIAS_CONTROL 0x20
127 #define TERMINATION_RESISTER_CONTROL 0x21
128 #define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY 0x22
129 #define HS_RX_CONTROL_OF_LANE_0 0x44
130 #define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL 0x60
131 #define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL 0x61
132 #define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL 0x62
133 #define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL 0x63
134 #define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL 0x64
135 #define HS_TX_CLOCK_LANE_POST_TIME_CONTROL 0x65
136 #define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL 0x70
137 #define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL 0x71
138 #define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL 0x72
139 #define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL 0x73
140 #define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL 0x74
141
142 #define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0)
143 #define DW_MIPI_NEEDS_GRF_CLK BIT(1)
144 #define DW_MIPI_NEEDS_HCLK BIT(2)
145
146 #define PX30_GRF_PD_VO_CON1 0x0438
147 #define PX30_DSI_FORCETXSTOPMODE (0xf << 7)
148 #define PX30_DSI_FORCERXMODE BIT(6)
149 #define PX30_DSI_TURNDISABLE BIT(5)
150 #define PX30_DSI_LCDC_SEL BIT(0)
151
152 #define RK3128_GRF_LVDS_CON0 0x0150
153 #define RK3128_DSI_FORCETXSTOPMODE (0xf << 10)
154 #define RK3128_DSI_FORCERXMODE (0x1 << 9)
155 #define RK3128_DSI_TURNDISABLE (0x1 << 8)
156
157 #define RK3288_GRF_SOC_CON6 0x025c
158 #define RK3288_DSI0_LCDC_SEL BIT(6)
159 #define RK3288_DSI1_LCDC_SEL BIT(9)
160
161 #define RK3399_GRF_SOC_CON20 0x6250
162 #define RK3399_DSI0_LCDC_SEL BIT(0)
163 #define RK3399_DSI1_LCDC_SEL BIT(4)
164
165 #define RK3399_GRF_SOC_CON22 0x6258
166 #define RK3399_DSI0_TURNREQUEST (0xf << 12)
167 #define RK3399_DSI0_TURNDISABLE (0xf << 8)
168 #define RK3399_DSI0_FORCETXSTOPMODE (0xf << 4)
169 #define RK3399_DSI0_FORCERXMODE (0xf << 0)
170
171 #define RK3399_GRF_SOC_CON23 0x625c
172 #define RK3399_DSI1_TURNDISABLE (0xf << 12)
173 #define RK3399_DSI1_FORCETXSTOPMODE (0xf << 8)
174 #define RK3399_DSI1_FORCERXMODE (0xf << 4)
175 #define RK3399_DSI1_ENABLE (0xf << 0)
176
177 #define RK3399_GRF_SOC_CON24 0x6260
178 #define RK3399_TXRX_MASTERSLAVEZ BIT(7)
179 #define RK3399_TXRX_ENABLECLK BIT(6)
180 #define RK3399_TXRX_BASEDIR BIT(5)
181
182 #define RK3562_SYS_GRF_VO_CON1 0x05d4
183 #define RK3562_DSI_FORCETXSTOPMODE (0xf << 4)
184 #define RK3562_DSI_TURNDISABLE (0x1 << 2)
185 #define RK3562_DSI_FORCERXMODE (0x1 << 0)
186
187 #define RK3568_GRF_VO_CON2 0x0368
188 #define RK3568_GRF_VO_CON3 0x036c
189 #define RK3568_DSI_FORCETXSTOPMODE (0xf << 4)
190 #define RK3568_DSI_TURNDISABLE (0x1 << 2)
191 #define RK3568_DSI_FORCERXMODE (0x1 << 0)
192
193 #define RV1126_GRF_DSIPHY_CON 0x10220
194 #define RV1126_DSI_FORCETXSTOPMODE (0xf << 4)
195 #define RV1126_DSI_TURNDISABLE (0x1 << 2)
196 #define RV1126_DSI_FORCERXMODE (0x1 << 0)
197
198 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
199
200 #define to_dsi(nm) container_of(nm, struct dw_mipi_dsi_rockchip, nm)
201
202 enum {
203 BANDGAP_97_07,
204 BANDGAP_98_05,
205 BANDGAP_99_02,
206 BANDGAP_100_00,
207 BANDGAP_93_17,
208 BANDGAP_94_15,
209 BANDGAP_95_12,
210 BANDGAP_96_10,
211 };
212
213 enum {
214 BIASEXTR_87_1,
215 BIASEXTR_91_5,
216 BIASEXTR_95_9,
217 BIASEXTR_100,
218 BIASEXTR_105_94,
219 BIASEXTR_111_88,
220 BIASEXTR_118_8,
221 BIASEXTR_127_7,
222 };
223
224 enum soc_type {
225 PX30,
226 RK3128,
227 RK3288,
228 RK3399,
229 RK3562,
230 RK3568,
231 RV1126,
232 };
233
234 struct cmd_header {
235 u8 cmd_type;
236 u8 delay;
237 u8 payload_length;
238 };
239
240 struct rockchip_dw_dsi_chip_data {
241 u32 reg;
242
243 u32 lcdsel_grf_reg;
244 u32 lcdsel_big;
245 u32 lcdsel_lit;
246
247 u32 enable_grf_reg;
248 u32 enable;
249
250 u32 lanecfg1_grf_reg;
251 u32 lanecfg1;
252 u32 lanecfg2_grf_reg;
253 u32 lanecfg2;
254
255 enum soc_type soc_type;
256 unsigned int flags;
257 unsigned int max_data_lanes;
258 unsigned long max_bit_rate_per_lane;
259 };
260
261 struct dw_mipi_dsi_rockchip {
262 struct device *dev;
263 struct drm_encoder encoder;
264 void __iomem *base;
265 int id;
266
267 bool c_option;
268 bool scrambling_en;
269 unsigned int slice_width;
270 unsigned int slice_height;
271 unsigned int slice_per_pkt;
272 bool block_pred_enable;
273 bool dsc_enable;
274 u8 version_major;
275 u8 version_minor;
276
277 struct drm_dsc_picture_parameter_set *pps;
278 struct regmap *grf_regmap;
279 struct clk *pllref_clk;
280 struct clk *pclk;
281 struct clk *grf_clk;
282 struct clk *phy_cfg_clk;
283 struct clk *hclk;
284
285 /* dual-channel */
286 bool is_slave;
287 struct dw_mipi_dsi_rockchip *slave;
288
289 /* optional external dphy */
290 bool phy_enabled;
291 struct phy *phy;
292 union phy_configure_opts phy_opts;
293
294 unsigned int lane_mbps; /* per lane */
295 u16 input_div;
296 u16 feedback_div;
297 u32 format;
298
299 struct dw_mipi_dsi *dmd;
300 const struct rockchip_dw_dsi_chip_data *cdata;
301 struct dw_mipi_dsi_plat_data pdata;
302 int devcnt;
303 struct rockchip_drm_sub_dev sub_dev;
304 struct drm_panel *panel;
305 struct drm_bridge *bridge;
306 };
307
308 struct dphy_pll_parameter_map {
309 unsigned int max_mbps;
310 u8 hsfreqrange;
311 u8 icpctrl;
312 u8 lpfctrl;
313 };
314
315 /* The table is based on 27MHz DPHY pll reference clock. */
316 static const struct dphy_pll_parameter_map dppa_map[] = {
317 { 89, 0x00, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
318 { 99, 0x10, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
319 { 109, 0x20, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
320 { 129, 0x01, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
321 { 139, 0x11, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
322 { 149, 0x21, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
323 { 169, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
324 { 179, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
325 { 199, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
326 { 219, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
327 { 239, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
328 { 249, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
329 { 269, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM },
330 { 299, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM },
331 { 329, 0x05, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
332 { 359, 0x15, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
333 { 399, 0x25, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
334 { 449, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
335 { 499, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
336 { 549, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM },
337 { 599, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM },
338 { 649, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
339 { 699, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
340 { 749, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
341 { 799, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
342 { 849, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
343 { 899, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
344 { 949, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
345 { 999, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
346 {1049, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
347 {1099, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
348 {1149, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
349 {1199, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
350 {1249, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
351 {1299, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
352 {1349, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
353 {1399, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
354 {1449, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
355 {1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }
356 };
357
max_mbps_to_parameter(unsigned int max_mbps)358 static int max_mbps_to_parameter(unsigned int max_mbps)
359 {
360 int i;
361
362 for (i = 0; i < ARRAY_SIZE(dppa_map); i++)
363 if (dppa_map[i].max_mbps >= max_mbps)
364 return i;
365
366 return -EINVAL;
367 }
368
dsi_write(struct dw_mipi_dsi_rockchip * dsi,u32 reg,u32 val)369 static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val)
370 {
371 writel(val, dsi->base + reg);
372 }
373
dsi_read(struct dw_mipi_dsi_rockchip * dsi,u32 reg)374 static inline u32 dsi_read(struct dw_mipi_dsi_rockchip *dsi, u32 reg)
375 {
376 return readl(dsi->base + reg);
377 }
378
dsi_set(struct dw_mipi_dsi_rockchip * dsi,u32 reg,u32 mask)379 static inline void dsi_set(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 mask)
380 {
381 dsi_write(dsi, reg, dsi_read(dsi, reg) | mask);
382 }
383
dsi_update_bits(struct dw_mipi_dsi_rockchip * dsi,u32 reg,u32 mask,u32 val)384 static inline void dsi_update_bits(struct dw_mipi_dsi_rockchip *dsi, u32 reg,
385 u32 mask, u32 val)
386 {
387 dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
388 }
389
dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip * dsi,u8 test_code,u8 test_data)390 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi,
391 u8 test_code,
392 u8 test_data)
393 {
394 /*
395 * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
396 * is latched internally as the current test code. Test data is
397 * programmed internally by rising edge on TESTCLK.
398 */
399 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
400
401 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
402 PHY_TESTDIN(test_code));
403
404 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
405
406 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
407 PHY_TESTDIN(test_data));
408
409 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
410 }
411
412 /**
413 * ns2bc - Nanoseconds to byte clock cycles
414 */
ns2bc(struct dw_mipi_dsi_rockchip * dsi,int ns)415 static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns)
416 {
417 return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000);
418 }
419
420 /**
421 * ns2ui - Nanoseconds to UI time periods
422 */
ns2ui(struct dw_mipi_dsi_rockchip * dsi,int ns)423 static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns)
424 {
425 return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000);
426 }
427
dw_mipi_dsi_phy_tx_config(struct dw_mipi_dsi_rockchip * dsi)428 static void dw_mipi_dsi_phy_tx_config(struct dw_mipi_dsi_rockchip *dsi)
429 {
430 if (dsi->cdata->lanecfg1_grf_reg)
431 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg,
432 dsi->cdata->lanecfg1);
433
434 if (dsi->cdata->lanecfg2_grf_reg)
435 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg,
436 dsi->cdata->lanecfg2);
437
438 if (dsi->cdata->enable_grf_reg)
439 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg,
440 dsi->cdata->enable);
441 }
442
dw_mipi_dsi_phy_init(void * priv_data)443 static int dw_mipi_dsi_phy_init(void *priv_data)
444 {
445 struct dw_mipi_dsi_rockchip *dsi = priv_data;
446 int i, vco;
447
448 dw_mipi_dsi_phy_tx_config(dsi);
449
450 if (dsi->phy)
451 return 0;
452
453 /*
454 * Get vco from frequency(lane_mbps)
455 * vco frequency table
456 * 000 - between 80 and 200 MHz
457 * 001 - between 200 and 300 MHz
458 * 010 - between 300 and 500 MHz
459 * 011 - between 500 and 700 MHz
460 * 100 - between 700 and 900 MHz
461 * 101 - between 900 and 1100 MHz
462 * 110 - between 1100 and 1300 MHz
463 * 111 - between 1300 and 1500 MHz
464 */
465 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
466
467 i = max_mbps_to_parameter(dsi->lane_mbps);
468 if (i < 0) {
469 DRM_DEV_ERROR(dsi->dev,
470 "failed to get parameter for %dmbps clock\n",
471 dsi->lane_mbps);
472 return i;
473 }
474
475 dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL,
476 BYPASS_VCO_RANGE |
477 VCO_RANGE_CON_SEL(vco) |
478 VCO_IN_CAP_CON_LOW |
479 REF_BIAS_CUR_SEL);
480
481 dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS,
482 CP_CURRENT_SEL(dppa_map[i].icpctrl));
483 dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL,
484 CP_PROGRAM_EN | LPF_PROGRAM_EN |
485 LPF_RESISTORS_SEL(dppa_map[i].lpfctrl));
486
487 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0,
488 HSFREQRANGE_SEL(dppa_map[i].hsfreqrange));
489
490 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO,
491 INPUT_DIVIDER(dsi->input_div));
492 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
493 LOOP_DIV_LOW_SEL(dsi->feedback_div) |
494 LOW_PROGRAM_EN);
495 /*
496 * We need set PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL immediately
497 * to make the configured LSB effective according to IP simulation
498 * and lab test results.
499 * Only in this way can we get correct mipi phy pll frequency.
500 */
501 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
502 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
503 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
504 LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
505 HIGH_PROGRAM_EN);
506 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
507 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
508
509 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
510 LOW_PROGRAM_EN | BIASEXTR_SEL(BIASEXTR_127_7));
511 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
512 HIGH_PROGRAM_EN | BANDGAP_SEL(BANDGAP_96_10));
513
514 dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL,
515 POWER_CONTROL | INTERNAL_REG_CURRENT |
516 BIAS_BLOCK_ON | BANDGAP_ON);
517
518 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
519 TER_RESISTOR_LOW | TER_CAL_DONE |
520 SETRD_MAX | TER_RESISTORS_ON);
521 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
522 TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
523 SETRD_MAX | POWER_MANAGE |
524 TER_RESISTORS_ON);
525
526 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL,
527 TLP_PROGRAM_EN | ns2bc(dsi, 60));
528 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL,
529 THS_PRE_PROGRAM_EN | ns2ui(dsi, 40));
530 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL,
531 THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300));
532 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL,
533 THS_PRE_PROGRAM_EN | ns2ui(dsi, 100));
534 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL,
535 BIT(5) | ns2bc(dsi, 100));
536 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL,
537 BIT(5) | (ns2bc(dsi, 60) + 7));
538
539 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL,
540 TLP_PROGRAM_EN | ns2bc(dsi, 60));
541 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL,
542 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20));
543 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL,
544 THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2));
545 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL,
546 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8));
547 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL,
548 BIT(5) | ns2bc(dsi, 100));
549
550 return 0;
551 }
552
dw_mipi_dsi_phy_power_on(void * priv_data)553 static void dw_mipi_dsi_phy_power_on(void *priv_data)
554 {
555 struct dw_mipi_dsi_rockchip *dsi = priv_data;
556
557 if (dsi->phy_enabled)
558 return;
559
560 phy_power_on(dsi->phy);
561 dsi->phy_enabled = true;
562 }
563
dw_mipi_dsi_phy_power_off(void * priv_data)564 static void dw_mipi_dsi_phy_power_off(void *priv_data)
565 {
566 struct dw_mipi_dsi_rockchip *dsi = priv_data;
567
568 if (!dsi->phy_enabled)
569 return;
570
571 phy_power_off(dsi->phy);
572 dsi->phy_enabled = false;
573 }
574
dw_mipi_dsi_calculate_lane_mpbs(struct dw_mipi_dsi_rockchip * dsi,const struct drm_display_mode * mode,u32 lanes,int bpp)575 static unsigned int dw_mipi_dsi_calculate_lane_mpbs(struct dw_mipi_dsi_rockchip *dsi,
576 const struct drm_display_mode *mode,
577 u32 lanes, int bpp)
578 {
579 struct device *dev = dsi->dev;
580 unsigned int target_mbps = 1000;
581 unsigned int max_mbps;
582 unsigned int value;
583 unsigned long mpclk, tmp;
584
585 if (dsi->is_slave)
586 return dsi->lane_mbps;
587
588 max_mbps = dsi->cdata->max_bit_rate_per_lane / USEC_PER_SEC;
589
590 /* optional override of the desired bandwidth */
591 if (!of_property_read_u32(dev->of_node, "rockchip,lane-rate", &value)) {
592 target_mbps = value;
593 } else {
594 mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
595 if (mpclk) {
596 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
597 tmp = mpclk * (bpp / lanes) * 10 / 9;
598 if (tmp < max_mbps)
599 target_mbps = tmp;
600 else {
601 DRM_DEV_ERROR(dsi->dev,
602 "DPHY clock frequency is out of range\n");
603 target_mbps = max_mbps;
604 }
605 }
606 }
607
608 if (dsi->slave)
609 dsi->slave->lane_mbps = target_mbps;
610
611 return target_mbps;
612 }
613
614 static int
dw_mipi_dsi_get_lane_mbps(void * priv_data,const struct drm_display_mode * mode,unsigned long mode_flags,u32 lanes,u32 format,unsigned int * lane_mbps)615 dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
616 unsigned long mode_flags, u32 lanes, u32 format,
617 unsigned int *lane_mbps)
618 {
619 struct dw_mipi_dsi_rockchip *dsi = priv_data;
620 unsigned long best_freq = 0;
621 unsigned long fvco_min, fvco_max, fin, fout;
622 unsigned int min_prediv, max_prediv;
623 unsigned int _prediv, best_prediv;
624 unsigned long _fbdiv, best_fbdiv;
625 unsigned long min_delta = ULONG_MAX;
626 unsigned long target_pclk, hs_clk_rate;
627 unsigned int target_mbps;
628 int bpp, ret;
629
630 dsi->format = format;
631 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
632 if (bpp < 0) {
633 DRM_DEV_ERROR(dsi->dev,
634 "failed to get bpp for pixel format %d\n",
635 dsi->format);
636 return bpp;
637 }
638
639 target_mbps = dw_mipi_dsi_calculate_lane_mpbs(dsi, mode, lanes, bpp);
640
641 /* for external phy only a the mipi_dphy_config is necessary */
642 if (dsi->phy) {
643 target_pclk = DIV_ROUND_CLOSEST_ULL(target_mbps * lanes, bpp);
644 phy_mipi_dphy_get_default_config(target_pclk * USEC_PER_SEC,
645 bpp, lanes,
646 &dsi->phy_opts.mipi_dphy);
647 ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY);
648 if (ret) {
649 DRM_DEV_ERROR(dsi->dev,
650 "failed to set phy mode: %d\n", ret);
651 return ret;
652 }
653
654 phy_configure(dsi->phy, &dsi->phy_opts);
655 hs_clk_rate = dsi->phy_opts.mipi_dphy.hs_clk_rate;
656 dsi->lane_mbps = DIV_ROUND_UP(hs_clk_rate, USEC_PER_SEC);
657 *lane_mbps = dsi->lane_mbps;
658
659 return 0;
660 }
661
662 fin = clk_get_rate(dsi->pllref_clk);
663 fout = target_mbps * USEC_PER_SEC;
664
665 /* constraint: 5Mhz <= Fref / N <= 40MHz */
666 min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC);
667 max_prediv = fin / (5 * USEC_PER_SEC);
668
669 /* constraint: 80MHz <= Fvco <= 1500Mhz */
670 fvco_min = 80 * USEC_PER_SEC;
671 fvco_max = 1500 * USEC_PER_SEC;
672
673 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
674 u64 tmp;
675 u32 delta;
676 /* Fvco = Fref * M / N */
677 tmp = (u64)fout * _prediv;
678 do_div(tmp, fin);
679 _fbdiv = tmp;
680 /*
681 * Due to the use of a "by 2 pre-scaler," the range of the
682 * feedback multiplication value M is limited to even division
683 * numbers, and m must be greater than 6, not bigger than 512.
684 */
685 if (_fbdiv < 6 || _fbdiv > 512)
686 continue;
687
688 _fbdiv += _fbdiv % 2;
689
690 tmp = (u64)_fbdiv * fin;
691 do_div(tmp, _prediv);
692 if (tmp < fvco_min || tmp > fvco_max)
693 continue;
694
695 delta = abs(fout - tmp);
696 if (delta < min_delta) {
697 best_prediv = _prediv;
698 best_fbdiv = _fbdiv;
699 min_delta = delta;
700 best_freq = tmp;
701 }
702 }
703
704 if (best_freq) {
705 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC);
706 *lane_mbps = dsi->lane_mbps;
707 dsi->input_div = best_prediv;
708 dsi->feedback_div = best_fbdiv;
709 } else {
710 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n");
711 return -EINVAL;
712 }
713
714 return 0;
715 }
716
717 struct hstt {
718 unsigned int maxfreq;
719 struct dw_mipi_dsi_dphy_timing timing;
720 };
721
722 struct dw_mipi_dsi_dphy_timing dphy_hstt = {
723 .clk_lp2hs = 0x40,
724 .clk_hs2lp = 0x40,
725 .data_lp2hs = 0x10,
726 .data_hs2lp = 0x14,
727 };
728
729 static int
dw_mipi_dsi_phy_get_timing(void * priv_data,unsigned int lane_mbps,struct dw_mipi_dsi_dphy_timing * timing)730 dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
731 struct dw_mipi_dsi_dphy_timing *timing)
732 {
733 *timing = dphy_hstt;
734
735 return 0;
736 }
737
738 static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = {
739 .init = dw_mipi_dsi_phy_init,
740 .power_on = dw_mipi_dsi_phy_power_on,
741 .power_off = dw_mipi_dsi_phy_power_off,
742 .get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
743 .get_timing = dw_mipi_dsi_phy_get_timing,
744 };
745
dw_mipi_dsi_rockchip_vop_routing(struct dw_mipi_dsi_rockchip * dsi)746 static void dw_mipi_dsi_rockchip_vop_routing(struct dw_mipi_dsi_rockchip *dsi)
747 {
748 int mux;
749
750 mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node,
751 &dsi->encoder);
752 if (mux < 0)
753 return;
754
755 if (dsi->cdata->lcdsel_grf_reg) {
756 regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg,
757 mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big);
758
759 if (dsi->slave && dsi->slave->cdata->lcdsel_grf_reg)
760 regmap_write(dsi->slave->grf_regmap,
761 dsi->slave->cdata->lcdsel_grf_reg,
762 mux ? dsi->slave->cdata->lcdsel_lit :
763 dsi->slave->cdata->lcdsel_big);
764 }
765 }
766
767 static int
dw_mipi_dsi_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)768 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
769 struct drm_crtc_state *crtc_state,
770 struct drm_connector_state *conn_state)
771 {
772 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
773 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
774 struct drm_connector *connector = conn_state->connector;
775 struct drm_display_info *info = &connector->display_info;
776
777 switch (dsi->format) {
778 case MIPI_DSI_FMT_RGB888:
779 s->output_mode = ROCKCHIP_OUT_MODE_P888;
780 break;
781 case MIPI_DSI_FMT_RGB666:
782 s->output_mode = ROCKCHIP_OUT_MODE_P666;
783 break;
784 case MIPI_DSI_FMT_RGB565:
785 s->output_mode = ROCKCHIP_OUT_MODE_P565;
786 break;
787 default:
788 WARN_ON(1);
789 return -EINVAL;
790 }
791
792 if (info->num_bus_formats)
793 s->bus_format = info->bus_formats[0];
794 else
795 s->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
796
797 s->bus_flags = info->bus_flags;
798 /* rk356x series drive mipi pixdata on posedge */
799 if (dsi->cdata->soc_type == RK3568) {
800 s->bus_flags &= ~DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE;
801 s->bus_flags |= DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE;
802 }
803
804 s->output_type = DRM_MODE_CONNECTOR_DSI;
805 s->tv_state = &conn_state->tv;
806 s->color_space = V4L2_COLORSPACE_DEFAULT;
807 s->output_if = dsi->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0;
808 if (dsi->slave) {
809 s->output_flags |= ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE;
810 s->output_if |= VOP_OUTPUT_IF_MIPI1;
811 }
812
813 /* dual link dsi for rk3399 */
814 if (dsi->id && dsi->cdata->soc_type == RK3399)
815 s->output_flags |= ROCKCHIP_OUTPUT_DATA_SWAP;
816
817 if (dsi->dsc_enable) {
818 s->dsc_enable = 1;
819 s->dsc_sink_cap.version_major = dsi->version_major;
820 s->dsc_sink_cap.version_minor = dsi->version_minor;
821 s->dsc_sink_cap.slice_width = dsi->slice_width;
822 s->dsc_sink_cap.slice_height = dsi->slice_height;
823 /* only can support rgb888 panel now */
824 s->dsc_sink_cap.target_bits_per_pixel_x16 = 8 << 4;
825 s->dsc_sink_cap.block_pred = dsi->block_pred_enable;
826 s->dsc_sink_cap.native_420 = 0;
827
828 memcpy(&s->pps, dsi->pps, sizeof(struct drm_dsc_picture_parameter_set));
829 }
830
831 return 0;
832 }
833
dw_mipi_dsi_encoder_enable(struct drm_encoder * encoder)834 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
835 {
836 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
837
838 dw_mipi_dsi_rockchip_vop_routing(dsi);
839 }
840
dw_mipi_dsi_encoder_disable(struct drm_encoder * encoder)841 static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
842 {
843 }
844
dw_mipi_dsi_rockchip_loader_protect(struct dw_mipi_dsi_rockchip * dsi,bool on)845 static void dw_mipi_dsi_rockchip_loader_protect(struct dw_mipi_dsi_rockchip *dsi, bool on)
846 {
847 if (on) {
848 pm_runtime_get_sync(dsi->dev);
849 phy_init(dsi->phy);
850 dsi->phy_enabled = true;
851 if (dsi->phy)
852 dsi->phy->power_count++;
853 } else {
854 pm_runtime_put(dsi->dev);
855 phy_exit(dsi->phy);
856 dsi->phy_enabled = false;
857 if (dsi->phy)
858 dsi->phy->power_count--;
859 }
860
861 if (dsi->slave)
862 dw_mipi_dsi_rockchip_loader_protect(dsi->slave, on);
863 }
864
dw_mipi_dsi_rockchip_encoder_loader_protect(struct drm_encoder * encoder,bool on)865 static int dw_mipi_dsi_rockchip_encoder_loader_protect(struct drm_encoder *encoder,
866 bool on)
867 {
868 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
869
870 if (dsi->panel)
871 panel_simple_loader_protect(dsi->panel);
872
873 dw_mipi_dsi_rockchip_loader_protect(dsi, on);
874
875 return 0;
876 }
877
878 static const struct drm_encoder_helper_funcs
879 dw_mipi_dsi_encoder_helper_funcs = {
880 .atomic_check = dw_mipi_dsi_encoder_atomic_check,
881 .enable = dw_mipi_dsi_encoder_enable,
882 .disable = dw_mipi_dsi_encoder_disable,
883 };
884
rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip * dsi,struct drm_device * drm_dev)885 static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi,
886 struct drm_device *drm_dev)
887 {
888 struct drm_encoder *encoder = &dsi->encoder;
889 int ret;
890
891 encoder->possible_crtcs = rockchip_drm_of_find_possible_crtcs(drm_dev,
892 dsi->dev->of_node);
893
894 ret = drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_DSI);
895 if (ret) {
896 DRM_ERROR("Failed to initialize encoder with drm\n");
897 return ret;
898 }
899
900 drm_encoder_helper_add(encoder, &dw_mipi_dsi_encoder_helper_funcs);
901
902 return 0;
903 }
904
905 static struct device
dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip * dsi)906 *dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi)
907 {
908 struct device_node *node = NULL;
909 struct platform_device *pdev;
910 struct dw_mipi_dsi_rockchip *dsi2;
911
912 node = of_parse_phandle(dsi->dev->of_node, "rockchip,dual-channel", 0);
913 if (node) {
914 pdev = of_find_device_by_node(node);
915 if (!pdev)
916 return ERR_PTR(-EPROBE_DEFER);
917
918 dsi2 = platform_get_drvdata(pdev);
919 if (!dsi2) {
920 platform_device_put(pdev);
921 return ERR_PTR(-EPROBE_DEFER);
922 }
923
924 return &pdev->dev;
925 }
926
927 return NULL;
928 }
929
dw_mipi_dsi_get_dsc_info_from_sink(struct dw_mipi_dsi_rockchip * dsi,struct drm_panel * panel,struct drm_bridge * bridge)930 static int dw_mipi_dsi_get_dsc_info_from_sink(struct dw_mipi_dsi_rockchip *dsi,
931 struct drm_panel *panel,
932 struct drm_bridge *bridge)
933 {
934 struct drm_dsc_picture_parameter_set *pps = NULL;
935 struct device_node *np = NULL;
936 struct cmd_header *header;
937 const void *data;
938 char *d;
939 uint8_t *dsc_packed_pps;
940 int len;
941
942 if (!panel && !bridge)
943 return -ENODEV;
944
945 if (panel)
946 np = panel->dev->of_node;
947 else
948 np = bridge->of_node;
949
950 dsi->c_option = of_property_read_bool(np, "phy-c-option");
951 dsi->scrambling_en = of_property_read_bool(np, "scrambling-enable");
952 dsi->dsc_enable = of_property_read_bool(np, "compressed-data");
953 dsi->block_pred_enable = of_property_read_bool(np, "blk-pred-enable");
954 of_property_read_u32(np, "slice-width", &dsi->slice_width);
955 of_property_read_u32(np, "slice-height", &dsi->slice_height);
956 of_property_read_u32(np, "slice-per-pkt", &dsi->slice_per_pkt);
957 of_property_read_u8(np, "version-major", &dsi->version_major);
958 of_property_read_u8(np, "version-minor", &dsi->version_minor);
959
960 data = of_get_property(np, "panel-init-sequence", &len);
961 if (!data)
962 return -EINVAL;
963
964 d = devm_kmemdup(dsi->dev, data, len, GFP_KERNEL);
965 if (!d)
966 return -ENOMEM;
967
968 while (len > sizeof(*header)) {
969 header = (struct cmd_header *)d;
970 d += sizeof(*header);
971 len -= sizeof(*header);
972
973 if (header->payload_length > len)
974 return -EINVAL;
975
976 if (header->cmd_type == MIPI_DSI_PICTURE_PARAMETER_SET) {
977 dsc_packed_pps = devm_kmemdup(dsi->dev, d,
978 header->payload_length, GFP_KERNEL);
979 if (!dsc_packed_pps)
980 return -ENOMEM;
981
982 pps = (struct drm_dsc_picture_parameter_set *)dsc_packed_pps;
983 break;
984 }
985
986 d += header->payload_length;
987 len -= header->payload_length;
988 }
989 dsi->pps = pps;
990
991 return 0;
992 }
993
dw_mipi_dsi_rockchip_bind(struct device * dev,struct device * master,void * data)994 static int dw_mipi_dsi_rockchip_bind(struct device *dev,
995 struct device *master,
996 void *data)
997 {
998 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
999 struct drm_device *drm_dev = data;
1000 struct device *second;
1001 int ret;
1002
1003 second = dw_mipi_dsi_rockchip_find_second(dsi);
1004 if (IS_ERR(second))
1005 return PTR_ERR(second);
1006
1007 if (second) {
1008 /* we are the slave in dual-DSI */
1009 dsi->slave = dev_get_drvdata(second);
1010 if (!dsi->slave) {
1011 DRM_DEV_ERROR(dev, "could not get slaves data\n");
1012 return -ENODEV;
1013 }
1014
1015 dsi->slave->is_slave = true;
1016 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd);
1017 put_device(second);
1018 }
1019
1020 if (dsi->is_slave)
1021 return 0;
1022
1023 ret = drm_of_find_panel_or_bridge(dsi->dev->of_node, 1, -1,
1024 &dsi->panel, &dsi->bridge);
1025 if (ret) {
1026 dev_err(dsi->dev, "failed to find panel or bridge: %d\n", ret);
1027 return ret;
1028 }
1029
1030 ret = clk_prepare_enable(dsi->pllref_clk);
1031 if (ret) {
1032 DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret);
1033 return ret;
1034 }
1035
1036 ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev);
1037 if (ret) {
1038 DRM_DEV_ERROR(dev, "Failed to create drm encoder\n");
1039 return ret;
1040 }
1041
1042 ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder);
1043 if (ret) {
1044 DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
1045 return ret;
1046 }
1047
1048 if (dsi->panel)
1049 dw_mipi_dsi_get_dsc_info_from_sink(dsi, dsi->panel, NULL);
1050
1051 dsi->sub_dev.connector = dw_mipi_dsi_get_connector(dsi->dmd);
1052 if (dsi->sub_dev.connector) {
1053 dsi->sub_dev.of_node = dev->of_node;
1054 dsi->sub_dev.loader_protect = dw_mipi_dsi_rockchip_encoder_loader_protect;
1055 rockchip_drm_register_sub_dev(&dsi->sub_dev);
1056 }
1057
1058 return 0;
1059 }
1060
dw_mipi_dsi_rockchip_unbind(struct device * dev,struct device * master,void * data)1061 static void dw_mipi_dsi_rockchip_unbind(struct device *dev,
1062 struct device *master,
1063 void *data)
1064 {
1065 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
1066
1067 if (dsi->is_slave)
1068 return;
1069
1070 if (dsi->sub_dev.connector)
1071 rockchip_drm_unregister_sub_dev(&dsi->sub_dev);
1072
1073 dw_mipi_dsi_unbind(dsi->dmd);
1074
1075 clk_disable_unprepare(dsi->pllref_clk);
1076 }
1077
1078 static const struct component_ops dw_mipi_dsi_rockchip_ops = {
1079 .bind = dw_mipi_dsi_rockchip_bind,
1080 .unbind = dw_mipi_dsi_rockchip_unbind,
1081 };
1082
dw_mipi_dsi_rockchip_component_add(struct dw_mipi_dsi_rockchip * dsi)1083 static int dw_mipi_dsi_rockchip_component_add(struct dw_mipi_dsi_rockchip *dsi)
1084 {
1085 int ret;
1086
1087 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops);
1088 if (ret) {
1089 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n",
1090 ret);
1091 return ret;
1092 }
1093
1094 return 0;
1095 }
1096
dw_mipi_dsi_rockchip_component_del(struct dw_mipi_dsi_rockchip * dsi)1097 static int dw_mipi_dsi_rockchip_component_del(struct dw_mipi_dsi_rockchip *dsi)
1098 {
1099 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops);
1100
1101 return 0;
1102 }
1103
dw_mipi_dsi_rockchip_probe(struct platform_device * pdev)1104 static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
1105 {
1106 struct device *dev = &pdev->dev;
1107 struct device_node *np = dev->of_node;
1108 struct dw_mipi_dsi_rockchip *dsi;
1109 struct resource *res;
1110 const struct rockchip_dw_dsi_chip_data *cdata =
1111 of_device_get_match_data(dev);
1112 int ret, i;
1113
1114 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1115 if (!dsi)
1116 return -ENOMEM;
1117
1118 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1119 dsi->base = devm_ioremap_resource(dev, res);
1120 if (IS_ERR(dsi->base)) {
1121 DRM_DEV_ERROR(dev, "Unable to get dsi registers\n");
1122 return PTR_ERR(dsi->base);
1123 }
1124
1125 i = 0;
1126 while (cdata[i].reg) {
1127 if (cdata[i].reg == res->start) {
1128 dsi->cdata = &cdata[i];
1129 dsi->id = i;
1130 break;
1131 }
1132
1133 i++;
1134 }
1135
1136 if (!dsi->cdata) {
1137 DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name);
1138 return -EINVAL;
1139 }
1140
1141 /* try to get a possible external dphy */
1142 dsi->phy = devm_phy_optional_get(dev, "dphy");
1143 if (IS_ERR(dsi->phy)) {
1144 ret = PTR_ERR(dsi->phy);
1145 DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret);
1146 return ret;
1147 }
1148
1149 dsi->pclk = devm_clk_get(dev, "pclk");
1150 if (IS_ERR(dsi->pclk)) {
1151 ret = PTR_ERR(dsi->pclk);
1152 dev_err(dev, "Unable to get pclk: %d\n", ret);
1153 return ret;
1154 }
1155
1156 dsi->pllref_clk = devm_clk_get(dev, "ref");
1157 if (IS_ERR(dsi->pllref_clk)) {
1158 if (dsi->phy) {
1159 /*
1160 * if external phy is present, pll will be
1161 * generated there.
1162 */
1163 dsi->pllref_clk = NULL;
1164 } else {
1165 ret = PTR_ERR(dsi->pllref_clk);
1166 DRM_DEV_ERROR(dev,
1167 "Unable to get pll reference clock: %d\n",
1168 ret);
1169 return ret;
1170 }
1171 }
1172
1173 if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) {
1174 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
1175 if (IS_ERR(dsi->phy_cfg_clk)) {
1176 ret = PTR_ERR(dsi->phy_cfg_clk);
1177 DRM_DEV_ERROR(dev,
1178 "Unable to get phy_cfg_clk: %d\n", ret);
1179 return ret;
1180 }
1181 }
1182
1183 if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) {
1184 dsi->grf_clk = devm_clk_get(dev, "grf");
1185 if (IS_ERR(dsi->grf_clk)) {
1186 ret = PTR_ERR(dsi->grf_clk);
1187 DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret);
1188 return ret;
1189 }
1190 }
1191
1192 if (dsi->cdata->flags & DW_MIPI_NEEDS_HCLK) {
1193 dsi->hclk = devm_clk_get(dev, "hclk");
1194 if (IS_ERR(dsi->hclk)) {
1195 ret = PTR_ERR(dsi->hclk);
1196 DRM_DEV_ERROR(dev, "Unable to get hclk: %d\n", ret);
1197 return ret;
1198 }
1199 }
1200
1201 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1202 if (IS_ERR(dsi->grf_regmap)) {
1203 DRM_DEV_ERROR(dsi->dev, "Unable to get rockchip,grf\n");
1204 return PTR_ERR(dsi->grf_regmap);
1205 }
1206
1207 dsi->dev = dev;
1208 dsi->pdata.base = dsi->base;
1209 dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes;
1210 dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops;
1211 dsi->pdata.priv_data = dsi;
1212 platform_set_drvdata(pdev, dsi);
1213
1214 dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata);
1215 if (IS_ERR(dsi->dmd)) {
1216 ret = PTR_ERR(dsi->dmd);
1217 if (ret != -EPROBE_DEFER)
1218 DRM_DEV_ERROR(dev,
1219 "Failed to probe dw_mipi_dsi: %d\n", ret);
1220 goto err_clkdisable;
1221 }
1222
1223 ret = dw_mipi_dsi_rockchip_component_add(dsi);
1224 if (ret < 0) {
1225 dw_mipi_dsi_remove(dsi->dmd);
1226 goto err_clkdisable;
1227 }
1228
1229 return 0;
1230
1231 err_clkdisable:
1232 clk_disable_unprepare(dsi->pllref_clk);
1233 return ret;
1234 }
1235
dw_mipi_dsi_rockchip_remove(struct platform_device * pdev)1236 static int dw_mipi_dsi_rockchip_remove(struct platform_device *pdev)
1237 {
1238 struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev);
1239
1240
1241 dw_mipi_dsi_rockchip_component_del(dsi);
1242 dw_mipi_dsi_remove(dsi->dmd);
1243
1244 return 0;
1245 }
1246
dw_mipi_dsi_runtime_suspend(struct device * dev)1247 static __maybe_unused int dw_mipi_dsi_runtime_suspend(struct device *dev)
1248 {
1249 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
1250
1251 clk_disable_unprepare(dsi->grf_clk);
1252 clk_disable_unprepare(dsi->pclk);
1253 clk_disable_unprepare(dsi->hclk);
1254 clk_disable_unprepare(dsi->phy_cfg_clk);
1255
1256 return 0;
1257 }
1258
dw_mipi_dsi_runtime_resume(struct device * dev)1259 static __maybe_unused int dw_mipi_dsi_runtime_resume(struct device *dev)
1260 {
1261 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
1262
1263 clk_prepare_enable(dsi->phy_cfg_clk);
1264 clk_prepare_enable(dsi->hclk);
1265 clk_prepare_enable(dsi->pclk);
1266 clk_prepare_enable(dsi->grf_clk);
1267
1268 return 0;
1269 }
1270
1271 static const struct dev_pm_ops dw_mipi_dsi_rockchip_pm_ops = {
1272 SET_RUNTIME_PM_OPS(dw_mipi_dsi_runtime_suspend,
1273 dw_mipi_dsi_runtime_resume, NULL)
1274 };
1275
1276 static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = {
1277 {
1278 .reg = 0xff450000,
1279 .lcdsel_grf_reg = PX30_GRF_PD_VO_CON1,
1280 .lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL),
1281 .lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL,
1282 PX30_DSI_LCDC_SEL),
1283
1284 .lanecfg1_grf_reg = PX30_GRF_PD_VO_CON1,
1285 .lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE |
1286 PX30_DSI_FORCERXMODE |
1287 PX30_DSI_FORCETXSTOPMODE),
1288
1289 .max_data_lanes = 4,
1290 .max_bit_rate_per_lane = 1000000000UL,
1291 .soc_type = PX30,
1292 },
1293 { /* sentinel */ }
1294 };
1295
1296 static const struct rockchip_dw_dsi_chip_data rk3128_chip_data[] = {
1297 {
1298 .reg = 0x10110000,
1299 .lanecfg1_grf_reg = RK3128_GRF_LVDS_CON0,
1300 .lanecfg1 = HIWORD_UPDATE(0, RK3128_DSI_TURNDISABLE |
1301 RK3128_DSI_FORCETXSTOPMODE |
1302 RK3128_DSI_FORCERXMODE),
1303 .flags = DW_MIPI_NEEDS_HCLK,
1304 .max_data_lanes = 4,
1305 .max_bit_rate_per_lane = 1000000000UL,
1306 .soc_type = RK3128,
1307 },
1308 { /* sentinel */ }
1309 };
1310
1311 static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = {
1312 {
1313 .reg = 0xff960000,
1314 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
1315 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL),
1316 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL),
1317
1318 .max_data_lanes = 4,
1319 .max_bit_rate_per_lane = 1500000000UL,
1320 .soc_type = RK3288,
1321 },
1322 {
1323 .reg = 0xff964000,
1324 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
1325 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL),
1326 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL),
1327
1328 .max_data_lanes = 4,
1329 .max_bit_rate_per_lane = 1500000000UL,
1330 .soc_type = RK3288,
1331 },
1332 { /* sentinel */ }
1333 };
1334
1335 static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = {
1336 {
1337 .reg = 0xff960000,
1338 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
1339 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL),
1340 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL,
1341 RK3399_DSI0_LCDC_SEL),
1342
1343 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON22,
1344 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST |
1345 RK3399_DSI0_TURNDISABLE |
1346 RK3399_DSI0_FORCETXSTOPMODE |
1347 RK3399_DSI0_FORCERXMODE),
1348
1349 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
1350 .max_data_lanes = 4,
1351 .max_bit_rate_per_lane = 1500000000UL,
1352 .soc_type = RK3399,
1353 },
1354 {
1355 .reg = 0xff968000,
1356 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
1357 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL),
1358 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL,
1359 RK3399_DSI1_LCDC_SEL),
1360
1361 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON23,
1362 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE |
1363 RK3399_DSI1_FORCETXSTOPMODE |
1364 RK3399_DSI1_FORCERXMODE |
1365 RK3399_DSI1_ENABLE),
1366
1367 .lanecfg2_grf_reg = RK3399_GRF_SOC_CON24,
1368 .lanecfg2 = HIWORD_UPDATE(RK3399_TXRX_MASTERSLAVEZ |
1369 RK3399_TXRX_ENABLECLK,
1370 RK3399_TXRX_MASTERSLAVEZ |
1371 RK3399_TXRX_ENABLECLK |
1372 RK3399_TXRX_BASEDIR),
1373
1374 .enable_grf_reg = RK3399_GRF_SOC_CON23,
1375 .enable = HIWORD_UPDATE(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE),
1376
1377 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
1378 .max_data_lanes = 4,
1379 .max_bit_rate_per_lane = 1500000000UL,
1380 .soc_type = RK3399,
1381 },
1382 { /* sentinel */ }
1383 };
1384
1385 static const struct rockchip_dw_dsi_chip_data rk3562_chip_data[] = {
1386 {
1387 .reg = 0xffb10000,
1388
1389 .lanecfg1_grf_reg = RK3562_SYS_GRF_VO_CON1,
1390 .lanecfg1 = HIWORD_UPDATE(0, RK3562_DSI_TURNDISABLE |
1391 RK3562_DSI_FORCERXMODE |
1392 RK3562_DSI_FORCETXSTOPMODE),
1393
1394 .max_data_lanes = 4,
1395 .max_bit_rate_per_lane = 1200000000UL,
1396 .soc_type = RK3562,
1397 },
1398 { /* sentinel */ }
1399 };
1400
1401 static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = {
1402 {
1403 .reg = 0xfe060000,
1404
1405 .lanecfg1_grf_reg = RK3568_GRF_VO_CON2,
1406 .lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI_TURNDISABLE |
1407 RK3568_DSI_FORCERXMODE |
1408 RK3568_DSI_FORCETXSTOPMODE),
1409
1410 .flags = DW_MIPI_NEEDS_HCLK,
1411 .max_data_lanes = 4,
1412 .max_bit_rate_per_lane = 1200000000UL,
1413 .soc_type = RK3568,
1414 },
1415 {
1416 .reg = 0xfe070000,
1417
1418 .lanecfg1_grf_reg = RK3568_GRF_VO_CON3,
1419 .lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI_TURNDISABLE |
1420 RK3568_DSI_FORCERXMODE |
1421 RK3568_DSI_FORCETXSTOPMODE),
1422
1423 .flags = DW_MIPI_NEEDS_HCLK,
1424 .max_data_lanes = 4,
1425 .max_bit_rate_per_lane = 1200000000UL,
1426 .soc_type = RK3568,
1427 },
1428 { /* sentinel */ }
1429 };
1430
1431 static const struct rockchip_dw_dsi_chip_data rv1126_chip_data[] = {
1432 {
1433 .reg = 0xffb30000,
1434
1435 .lanecfg1_grf_reg = RV1126_GRF_DSIPHY_CON,
1436 .lanecfg1 = HIWORD_UPDATE(0, RV1126_DSI_TURNDISABLE |
1437 RV1126_DSI_FORCERXMODE |
1438 RV1126_DSI_FORCETXSTOPMODE),
1439 .flags = DW_MIPI_NEEDS_HCLK,
1440 .max_data_lanes = 4,
1441 .max_bit_rate_per_lane = 1000000000UL,
1442 .soc_type = RV1126,
1443 },
1444 { /* sentinel */ }
1445 };
1446
1447 static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = {
1448 {
1449 .compatible = "rockchip,px30-mipi-dsi",
1450 .data = &px30_chip_data,
1451 }, {
1452 .compatible = "rockchip,rk3128-mipi-dsi",
1453 .data = &rk3128_chip_data,
1454 }, {
1455 .compatible = "rockchip,rk3288-mipi-dsi",
1456 .data = &rk3288_chip_data,
1457 }, {
1458 .compatible = "rockchip,rk3399-mipi-dsi",
1459 .data = &rk3399_chip_data,
1460 }, {
1461 .compatible = "rockchip,rk3562-mipi-dsi",
1462 .data = &rk3562_chip_data,
1463 }, {
1464 .compatible = "rockchip,rk3568-mipi-dsi",
1465 .data = &rk3568_chip_data,
1466 }, {
1467 .compatible = "rockchip,rv1126-mipi-dsi",
1468 .data = &rv1126_chip_data,
1469 },
1470 { /* sentinel */ }
1471 };
1472 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_rockchip_dt_ids);
1473
1474 struct platform_driver dw_mipi_dsi_rockchip_driver = {
1475 .probe = dw_mipi_dsi_rockchip_probe,
1476 .remove = dw_mipi_dsi_rockchip_remove,
1477 .driver = {
1478 .of_match_table = dw_mipi_dsi_rockchip_dt_ids,
1479 .pm = &dw_mipi_dsi_rockchip_pm_ops,
1480 .name = "dw-mipi-dsi-rockchip",
1481 /*
1482 * For dual-DSI display, one DSI pokes at the other DSI's
1483 * drvdata in dw_mipi_dsi_rockchip_find_second(). This is not
1484 * safe for asynchronous probe.
1485 */
1486 .probe_type = PROBE_FORCE_SYNCHRONOUS,
1487 },
1488 };
1489