Lines Matching +full:dphy +full:- +full:ref
2 * Rockchip MIPI RX Synopsys/Innosilicon DPHY driver
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
46 #include <media/media-entity.h>
47 #include <media/v4l2-ctrls.h>
48 #include <media/v4l2-fwnode.h>
49 #include <media/v4l2-subdev.h>
50 #include <media/v4l2-device.h>
129 /* Configure the count time of the THS-SETTLE by protocol. */
341 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
608 const struct dphy_reg *reg = &priv->grf_regs[index]; in write_grf_reg()
609 unsigned int val = HIWORD_UPDATE(value, reg->mask, reg->shift); in write_grf_reg()
611 if (reg->offset) in write_grf_reg()
612 regmap_write(priv->regmap_grf, reg->offset, val); in write_grf_reg()
617 const struct dphy_reg *reg = &priv->grf_regs[index]; in read_grf_reg()
620 if (reg->offset) { in read_grf_reg()
621 regmap_read(priv->regmap_grf, reg->offset, &val); in read_grf_reg()
622 val = (val >> reg->shift) & reg->mask; in read_grf_reg()
630 const struct txrx_reg *reg = &priv->txrx_regs[index]; in write_txrx_reg()
632 if (reg->offset) in write_txrx_reg()
633 writel(value, priv->txrx_base_addr + reg->offset); in write_txrx_reg()
671 const struct csiphy_reg *reg = &priv->csiphy_regs[index]; in write_csiphy_reg()
673 if (reg->offset != MIPI_CSI_DPHY_CTRL_INVALID_OFFSET) in write_csiphy_reg()
674 writel(value, priv->csihost_base_addr + reg->offset); in write_csiphy_reg()
680 const struct csiphy_reg *reg = &priv->csiphy_regs[index]; in read_csiphy_reg()
682 if (reg->offset != MIPI_CSI_DPHY_CTRL_INVALID_OFFSET) in read_csiphy_reg()
683 *value = readl(priv->csihost_base_addr + reg->offset); in read_csiphy_reg()
722 local = &sd->entity.pads[MIPI_DPHY_RX_PAD_SINK]; in get_remote_sensor()
725 v4l2_warn(sd, "No link between dphy and sensor\n"); in get_remote_sensor()
729 sensor_me = media_entity_remote_pad(local)->entity; in get_remote_sensor()
738 for (i = 0; i < priv->num_sensors; ++i) in sd_to_sensor()
739 if (priv->sensors[i].sd == sd) in sd_to_sensor()
740 return &priv->sensors[i]; in sd_to_sensor()
754 return -ENODEV; in mipidphy_get_sensor_data_rate()
756 link_freq = v4l2_ctrl_find(sensor_sd->ctrl_handler, V4L2_CID_LINK_FREQ); in mipidphy_get_sensor_data_rate()
759 return -EPIPE; in mipidphy_get_sensor_data_rate()
763 ret = v4l2_querymenu(sensor_sd->ctrl_handler, &qm); in mipidphy_get_sensor_data_rate()
771 return -EINVAL; in mipidphy_get_sensor_data_rate()
773 priv->data_rate_mbps = qm.value * 2; in mipidphy_get_sensor_data_rate()
774 do_div(priv->data_rate_mbps, 1000 * 1000); in mipidphy_get_sensor_data_rate()
775 v4l2_info(sd, "data_rate_mbps %lld\n", priv->data_rate_mbps); in mipidphy_get_sensor_data_rate()
788 return -ENODEV; in mipidphy_update_sensor_mbus()
791 return -ENODEV; in mipidphy_update_sensor_mbus()
796 sensor->mbus = mbus; in mipidphy_update_sensor_mbus()
799 sensor->lanes = 1; in mipidphy_update_sensor_mbus()
802 sensor->lanes = 2; in mipidphy_update_sensor_mbus()
805 sensor->lanes = 3; in mipidphy_update_sensor_mbus()
808 sensor->lanes = 4; in mipidphy_update_sensor_mbus()
811 return -EINVAL; in mipidphy_update_sensor_mbus()
823 model = sd->v4l2_dev->mdev->model; in rk1126_mipidphy_dphy_sel()
826 if (!strncmp(model, "rkcif_lite_mipi_lvds", sizeof("rkcif_lite_mipi_lvds") - 1)) { in rk1126_mipidphy_dphy_sel()
827 if (priv->phy_index == 0) in rk1126_mipidphy_dphy_sel()
831 } else if (!strncmp(model, "rkcif_mipi_lvds", sizeof("rkcif_mipi_lvds") - 1)) { in rk1126_mipidphy_dphy_sel()
832 if (priv->phy_index == 0) in rk1126_mipidphy_dphy_sel()
837 if (priv->phy_index == 0) in rk1126_mipidphy_dphy_sel()
852 if (priv->is_streaming) in mipidphy_s_stream_start()
859 if (priv->drv_data->chip_id == CHIP_ID_RK1126) in mipidphy_s_stream_start()
863 priv->stream_on(priv, sd); in mipidphy_s_stream_start()
865 priv->is_streaming = true; in mipidphy_s_stream_start()
874 if (!priv->is_streaming) in mipidphy_s_stream_stop()
877 if (priv->stream_off) in mipidphy_s_stream_stop()
878 priv->stream_off(priv, sd); in mipidphy_s_stream_stop()
879 priv->is_streaming = false; in mipidphy_s_stream_stop()
889 dev_info(priv->dev, "stream on:%d\n", on); in mipidphy_s_stream()
890 mutex_lock(&priv->mutex); in mipidphy_s_stream()
895 mutex_unlock(&priv->mutex); in mipidphy_s_stream()
907 return -EINVAL; in mipidphy_g_frame_interval()
918 return -ENODEV; in mipidphy_g_mbus_config()
921 return -ENODEV; in mipidphy_g_mbus_config()
923 *config = sensor->mbus; in mipidphy_g_mbus_config()
933 return pm_runtime_get_sync(priv->dev); in mipidphy_s_power()
935 return pm_runtime_put(priv->dev); in mipidphy_s_power()
945 num_clks = priv->drv_data->num_clks; in mipidphy_runtime_suspend()
946 for (i = num_clks - 1; i >= 0; i--) in mipidphy_runtime_suspend()
947 if (!IS_ERR(priv->clks[i])) in mipidphy_runtime_suspend()
948 clk_disable_unprepare(priv->clks[i]); in mipidphy_runtime_suspend()
960 num_clks = priv->drv_data->num_clks; in mipidphy_runtime_resume()
962 if (!IS_ERR(priv->clks[i])) { in mipidphy_runtime_resume()
963 ret = clk_prepare_enable(priv->clks[i]); in mipidphy_runtime_resume()
971 while (--i >= 0) in mipidphy_runtime_resume()
972 clk_disable_unprepare(priv->clks[i]); in mipidphy_runtime_resume()
976 /* dphy accepts all fmt/size from sensor */
990 return -ENODEV; in mipidphy_get_set_fmt()
993 return -ENODEV; in mipidphy_get_set_fmt()
995 if (!ret && fmt->pad == 0) in mipidphy_get_set_fmt()
996 sensor->format = fmt->format; in mipidphy_get_set_fmt()
1089 "dphy-ref",
1094 "dphy-ref",
1102 "dphy-ref",
1103 "dphy-cfg",
1126 * will affect txrx dphy in default state of grf_soc_con24. in rk3399_mipidphy_individual_init()
1137 struct device *dev = priv->dev; in rv1126_mipidphy_individual_init()
1138 struct device_node *parent = dev->of_node; in rv1126_mipidphy_individual_init()
1142 priv->grf_regs = priv->phy_index ? in rv1126_mipidphy_individual_init()
1148 if (strstr(remote->name, "isp")) in rv1126_mipidphy_individual_init()
1149 sel = !priv->phy_index ? 0 : RV1126_GRF_PHY1_SEL_ISP; in rv1126_mipidphy_individual_init()
1151 sel = !priv->phy_index ? 0 : in rv1126_mipidphy_individual_init()
1163 const struct dphy_drv_data *drv_data = priv->drv_data; in mipidphy_rx_stream_on()
1164 const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges; in mipidphy_rx_stream_on()
1165 int num_hsfreq_ranges = drv_data->num_hsfreq_ranges; in mipidphy_rx_stream_on()
1169 return -ENODEV; in mipidphy_rx_stream_on()
1172 return -ENODEV; in mipidphy_rx_stream_on()
1175 if (hsfreq_ranges[i].range_h >= priv->data_rate_mbps) { in mipidphy_rx_stream_on()
1182 i = num_hsfreq_ranges - 1; in mipidphy_rx_stream_on()
1183 dev_warn(priv->dev, "data rate: %lld mbps, max support %d mbps", in mipidphy_rx_stream_on()
1184 priv->data_rate_mbps, hsfreq_ranges[i].range_h + 1); in mipidphy_rx_stream_on()
1188 /* RK3288 isp connected to phy0-rx */ in mipidphy_rx_stream_on()
1239 write_grf_reg(priv, GRF_DPHY_RX0_ENABLE, GENMASK(sensor->lanes - 1, 0)); in mipidphy_rx_stream_on()
1260 const struct dphy_drv_data *drv_data = priv->drv_data; in mipidphy_txrx_stream_on()
1261 const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges; in mipidphy_txrx_stream_on()
1262 int num_hsfreq_ranges = drv_data->num_hsfreq_ranges; in mipidphy_txrx_stream_on()
1266 return -ENODEV; in mipidphy_txrx_stream_on()
1269 return -ENODEV; in mipidphy_txrx_stream_on()
1272 if (hsfreq_ranges[i].range_h >= priv->data_rate_mbps) { in mipidphy_txrx_stream_on()
1279 i = num_hsfreq_ranges - 1; in mipidphy_txrx_stream_on()
1280 dev_warn(priv->dev, "data rate: %lld mbps, max support %d mbps", in mipidphy_txrx_stream_on()
1281 priv->data_rate_mbps, hsfreq_ranges[i].range_h + 1); in mipidphy_txrx_stream_on()
1287 *step1:rk3288 isp connected to phy1-rx in mipidphy_txrx_stream_on()
1288 *step2:rk3288 phy1-rx test bus connected to csi host in mipidphy_txrx_stream_on()
1289 *step3:rk3288 phy1-rx source selected as: isp = 1'b1,csi-host = 1'b0 in mipidphy_txrx_stream_on()
1297 * step1:rk3399 phy1-rx source selected as:1'b0=isp1,1'b1=isp0 in mipidphy_txrx_stream_on()
1302 /* Step1: set RSTZ = 1'b0, phy1-rx controlled by isp */ in mipidphy_txrx_stream_on()
1304 /* Step2: set SHUTDOWNZ = 1'b0, phy1-rx controlled by isp */ in mipidphy_txrx_stream_on()
1361 GENMASK(sensor->lanes - 1, 0)); in mipidphy_txrx_stream_on()
1364 * Step13:Set SHUTDOWNZ=1'b1, phy1-rx controlled by isp, in mipidphy_txrx_stream_on()
1368 /* Step14:Set RSTZ=1'b1, phy1-rx controlled by isp*/ in mipidphy_txrx_stream_on()
1385 const struct dphy_drv_data *drv_data = priv->drv_data; in csi_mipidphy_stream_on()
1386 const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges; in csi_mipidphy_stream_on()
1387 int num_hsfreq_ranges = drv_data->num_hsfreq_ranges; in csi_mipidphy_stream_on()
1393 return -ENODEV; in csi_mipidphy_stream_on()
1396 return -ENODEV; in csi_mipidphy_stream_on()
1405 ((GENMASK(sensor->lanes - 1, 0) << MIPI_CSI_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT) | in csi_mipidphy_stream_on()
1408 /* Reset dphy analog part */ in csi_mipidphy_stream_on()
1412 if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) { in csi_mipidphy_stream_on()
1413 /* Reset dphy digital part */ in csi_mipidphy_stream_on()
1416 if (drv_data->chip_id == CHIP_ID_RK3326S) { in csi_mipidphy_stream_on()
1417 if (sensor->mbus.flags & V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) in csi_mipidphy_stream_on()
1419 else if (sensor->mbus.flags & V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK) in csi_mipidphy_stream_on()
1428 switch (sensor->format.code) { in csi_mipidphy_stream_on()
1454 if (priv->data_rate_mbps > 1500) { in csi_mipidphy_stream_on()
1456 if (sensor->lanes > 0x00) in csi_mipidphy_stream_on()
1458 if (sensor->lanes > 0x01) in csi_mipidphy_stream_on()
1460 if (sensor->lanes > 0x02) in csi_mipidphy_stream_on()
1462 if (sensor->lanes > 0x03) in csi_mipidphy_stream_on()
1468 if (hsfreq_ranges[i].range_h >= priv->data_rate_mbps) { in csi_mipidphy_stream_on()
1475 i = num_hsfreq_ranges - 1; in csi_mipidphy_stream_on()
1476 dev_warn(priv->dev, "data rate: %lld mbps, max support %d mbps", in csi_mipidphy_stream_on()
1477 priv->data_rate_mbps, hsfreq_ranges[i].range_h + 1); in csi_mipidphy_stream_on()
1482 if (sensor->lanes > 0x00) in csi_mipidphy_stream_on()
1484 if (sensor->lanes > 0x01) in csi_mipidphy_stream_on()
1486 if (sensor->lanes > 0x02) in csi_mipidphy_stream_on()
1488 if (sensor->lanes > 0x03) in csi_mipidphy_stream_on()
1494 GENMASK(sensor->lanes - 1, 0)); in csi_mipidphy_stream_on()
1595 .compatible = "rockchip,rk1808-mipi-dphy-rx",
1599 .compatible = "rockchip,rk3288-mipi-dphy",
1603 .compatible = "rockchip,rk3326-mipi-dphy",
1607 .compatible = "rockchip,rk3326s-mipi-dphy",
1611 .compatible = "rockchip,rk3368-mipi-dphy",
1615 .compatible = "rockchip,rk3399-mipi-dphy",
1619 .compatible = "rockchip,rv1126-csi-dphy",
1640 if (priv->num_sensors == ARRAY_SIZE(priv->sensors)) in rockchip_mipidphy_notifier_bound()
1641 return -EBUSY; in rockchip_mipidphy_notifier_bound()
1643 sensor = &priv->sensors[priv->num_sensors++]; in rockchip_mipidphy_notifier_bound()
1644 sensor->lanes = s_asd->lanes; in rockchip_mipidphy_notifier_bound()
1645 sensor->mbus = s_asd->mbus; in rockchip_mipidphy_notifier_bound()
1646 sensor->sd = sd; in rockchip_mipidphy_notifier_bound()
1647 dev_info(priv->dev, "match %s:bus type %d\n", sd->name, s_asd->mbus.type); in rockchip_mipidphy_notifier_bound()
1649 for (pad = 0; pad < sensor->sd->entity.num_pads; pad++) in rockchip_mipidphy_notifier_bound()
1650 if (sensor->sd->entity.pads[pad].flags & MEDIA_PAD_FL_SOURCE) in rockchip_mipidphy_notifier_bound()
1653 if (pad == sensor->sd->entity.num_pads) { in rockchip_mipidphy_notifier_bound()
1654 dev_err(priv->dev, in rockchip_mipidphy_notifier_bound()
1656 sensor->sd->name); in rockchip_mipidphy_notifier_bound()
1658 return -ENXIO; in rockchip_mipidphy_notifier_bound()
1662 &sensor->sd->entity, pad, in rockchip_mipidphy_notifier_bound()
1663 &priv->sd.entity, MIPI_DPHY_RX_PAD_SINK, in rockchip_mipidphy_notifier_bound()
1664 priv->num_sensors != 1 ? 0 : MEDIA_LNK_FL_ENABLED); in rockchip_mipidphy_notifier_bound()
1666 dev_err(priv->dev, in rockchip_mipidphy_notifier_bound()
1668 sensor->sd->name); in rockchip_mipidphy_notifier_bound()
1687 sensor->sd = NULL; in rockchip_mipidphy_notifier_unbind()
1702 struct v4l2_mbus_config *config = &s_asd->mbus; in rockchip_mipidphy_fwnode_parse()
1704 if (vep->base.port != 0) { in rockchip_mipidphy_fwnode_parse()
1706 return -EINVAL; in rockchip_mipidphy_fwnode_parse()
1709 if (vep->bus_type == V4L2_MBUS_CSI2_DPHY) { in rockchip_mipidphy_fwnode_parse()
1710 config->type = V4L2_MBUS_CSI2_DPHY; in rockchip_mipidphy_fwnode_parse()
1711 config->flags = vep->bus.mipi_csi2.flags; in rockchip_mipidphy_fwnode_parse()
1712 s_asd->lanes = vep->bus.mipi_csi2.num_data_lanes; in rockchip_mipidphy_fwnode_parse()
1713 } else if (vep->bus_type == V4L2_MBUS_CCP2) { in rockchip_mipidphy_fwnode_parse()
1715 config->type = V4L2_MBUS_CCP2; in rockchip_mipidphy_fwnode_parse()
1716 s_asd->lanes = vep->bus.mipi_csi1.data_lane; in rockchip_mipidphy_fwnode_parse()
1719 return -EINVAL; in rockchip_mipidphy_fwnode_parse()
1722 switch (s_asd->lanes) { in rockchip_mipidphy_fwnode_parse()
1724 config->flags |= V4L2_MBUS_CSI2_1_LANE; in rockchip_mipidphy_fwnode_parse()
1727 config->flags |= V4L2_MBUS_CSI2_2_LANE; in rockchip_mipidphy_fwnode_parse()
1730 config->flags |= V4L2_MBUS_CSI2_3_LANE; in rockchip_mipidphy_fwnode_parse()
1733 config->flags |= V4L2_MBUS_CSI2_4_LANE; in rockchip_mipidphy_fwnode_parse()
1736 return -EINVAL; in rockchip_mipidphy_fwnode_parse()
1746 priv->pads[MIPI_DPHY_RX_PAD_SOURCE].flags = in rockchip_mipidphy_media_init()
1748 priv->pads[MIPI_DPHY_RX_PAD_SINK].flags = in rockchip_mipidphy_media_init()
1750 priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; in rockchip_mipidphy_media_init()
1751 ret = media_entity_pads_init(&priv->sd.entity, in rockchip_mipidphy_media_init()
1752 MIPI_DPHY_RX_PADS_NUM, priv->pads); in rockchip_mipidphy_media_init()
1756 v4l2_async_notifier_init(&priv->notifier); in rockchip_mipidphy_media_init()
1759 priv->dev, &priv->notifier, in rockchip_mipidphy_media_init()
1765 priv->sd.subdev_notifier = &priv->notifier; in rockchip_mipidphy_media_init()
1766 priv->notifier.ops = &rockchip_mipidphy_async_ops; in rockchip_mipidphy_media_init()
1767 ret = v4l2_async_subdev_notifier_register(&priv->sd, &priv->notifier); in rockchip_mipidphy_media_init()
1769 dev_err(priv->dev, in rockchip_mipidphy_media_init()
1771 v4l2_async_notifier_cleanup(&priv->notifier); in rockchip_mipidphy_media_init()
1775 return v4l2_async_register_subdev(&priv->sd); in rockchip_mipidphy_media_init()
1780 struct device *dev = &pdev->dev; in rockchip_mipidphy_probe()
1791 return -ENOMEM; in rockchip_mipidphy_probe()
1792 priv->dev = dev; in rockchip_mipidphy_probe()
1796 return -EINVAL; in rockchip_mipidphy_probe()
1798 grf = syscon_node_to_regmap(dev->parent->of_node); in rockchip_mipidphy_probe()
1800 grf = syscon_regmap_lookup_by_phandle(dev->of_node, in rockchip_mipidphy_probe()
1804 return -ENODEV; in rockchip_mipidphy_probe()
1807 priv->regmap_grf = grf; in rockchip_mipidphy_probe()
1809 priv->phy_index = of_alias_get_id(dev->of_node, "dphy"); in rockchip_mipidphy_probe()
1810 if (priv->phy_index < 0) in rockchip_mipidphy_probe()
1811 priv->phy_index = 0; in rockchip_mipidphy_probe()
1813 drv_data = of_id->data; in rockchip_mipidphy_probe()
1817 for (i = 0; i < drv_data->num_clks; i++) { in rockchip_mipidphy_probe()
1818 priv->clks[i] = devm_clk_get(dev, drv_data->clks[i]); in rockchip_mipidphy_probe()
1820 if (IS_ERR(priv->clks[i])) in rockchip_mipidphy_probe()
1821 dev_dbg(dev, "Failed to get %s\n", drv_data->clks[i]); in rockchip_mipidphy_probe()
1824 priv->grf_regs = drv_data->grf_regs; in rockchip_mipidphy_probe()
1825 priv->txrx_regs = drv_data->txrx_regs; in rockchip_mipidphy_probe()
1826 priv->csiphy_regs = drv_data->csiphy_regs; in rockchip_mipidphy_probe()
1827 priv->drv_data = drv_data; in rockchip_mipidphy_probe()
1828 if (drv_data->ctl_type == MIPI_DPHY_CTL_CSI_HOST) { in rockchip_mipidphy_probe()
1830 priv->csihost_base_addr = devm_ioremap_resource(dev, res); in rockchip_mipidphy_probe()
1831 priv->stream_on = csi_mipidphy_stream_on; in rockchip_mipidphy_probe()
1832 priv->stream_off = csi_mipidphy_stream_off; in rockchip_mipidphy_probe()
1834 priv->stream_on = mipidphy_txrx_stream_on; in rockchip_mipidphy_probe()
1835 priv->txrx_base_addr = NULL; in rockchip_mipidphy_probe()
1837 priv->txrx_base_addr = devm_ioremap_resource(dev, res); in rockchip_mipidphy_probe()
1838 if (IS_ERR(priv->txrx_base_addr)) in rockchip_mipidphy_probe()
1839 priv->stream_on = mipidphy_rx_stream_on; in rockchip_mipidphy_probe()
1840 priv->stream_off = NULL; in rockchip_mipidphy_probe()
1843 sd = &priv->sd; in rockchip_mipidphy_probe()
1844 mutex_init(&priv->mutex); in rockchip_mipidphy_probe()
1846 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; in rockchip_mipidphy_probe()
1847 snprintf(sd->name, sizeof(sd->name), "rockchip-mipi-dphy-rx"); in rockchip_mipidphy_probe()
1848 sd->dev = dev; in rockchip_mipidphy_probe()
1850 platform_set_drvdata(pdev, &sd->entity); in rockchip_mipidphy_probe()
1856 pm_runtime_enable(&pdev->dev); in rockchip_mipidphy_probe()
1857 drv_data->individual_init(priv); in rockchip_mipidphy_probe()
1861 mutex_destroy(&priv->mutex); in rockchip_mipidphy_probe()
1871 media_entity_cleanup(&sd->entity); in rockchip_mipidphy_remove()
1873 pm_runtime_disable(&pdev->dev); in rockchip_mipidphy_remove()
1874 mutex_destroy(&priv->mutex); in rockchip_mipidphy_remove()
1887 .name = "rockchip-mipi-dphy-rx",
1895 MODULE_DESCRIPTION("Rockchip MIPI RX DPHY driver");