1*4882a593SmuzhiyunFreescale i.MX Media Video Device 2*4882a593Smuzhiyun================================= 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunVideo Media Controller node 5*4882a593Smuzhiyun--------------------------- 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunThis is the media controller node for video capture support. It is a 8*4882a593Smuzhiyunvirtual device that lists the camera serial interface nodes that the 9*4882a593Smuzhiyunmedia device will control. 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunRequired properties: 12*4882a593Smuzhiyun- compatible : "fsl,imx-capture-subsystem"; 13*4882a593Smuzhiyun- ports : Should contain a list of phandles pointing to camera 14*4882a593Smuzhiyun sensor interface ports of IPU devices 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunexample: 17*4882a593Smuzhiyun 18*4882a593Smuzhiyuncapture-subsystem { 19*4882a593Smuzhiyun compatible = "fsl,imx-capture-subsystem"; 20*4882a593Smuzhiyun ports = <&ipu1_csi0>, <&ipu1_csi1>; 21*4882a593Smuzhiyun}; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun 24*4882a593Smuzhiyunmipi_csi2 node 25*4882a593Smuzhiyun-------------- 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunThis is the device node for the MIPI CSI-2 Receiver core in the i.MX 28*4882a593SmuzhiyunSoC. This is a Synopsys Designware MIPI CSI-2 host controller core 29*4882a593Smuzhiyuncombined with a D-PHY core mixed into the same register block. In 30*4882a593Smuzhiyunaddition this device consists of an i.MX-specific "CSI2IPU gasket" 31*4882a593Smuzhiyunglue logic, also controlled from the same register block. The CSI2IPU 32*4882a593Smuzhiyungasket demultiplexes the four virtual channel streams from the host 33*4882a593Smuzhiyuncontroller's 32-bit output image bus onto four 16-bit parallel busses 34*4882a593Smuzhiyunto the i.MX IPU CSIs. 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunRequired properties: 37*4882a593Smuzhiyun- compatible : "fsl,imx6-mipi-csi2"; 38*4882a593Smuzhiyun- reg : physical base address and length of the register set; 39*4882a593Smuzhiyun- clocks : the MIPI CSI-2 receiver requires three clocks: hsi_tx 40*4882a593Smuzhiyun (the D-PHY clock), video_27m (D-PHY PLL reference 41*4882a593Smuzhiyun clock), and eim_podf; 42*4882a593Smuzhiyun- clock-names : must contain "dphy", "ref", "pix"; 43*4882a593Smuzhiyun- port@* : five port nodes must exist, containing endpoints 44*4882a593Smuzhiyun connecting to the source and sink devices according to 45*4882a593Smuzhiyun of_graph bindings. The first port is an input port, 46*4882a593Smuzhiyun connecting with a MIPI CSI-2 source, and ports 1 47*4882a593Smuzhiyun through 4 are output ports connecting with parallel 48*4882a593Smuzhiyun bus sink endpoint nodes and correspond to the four 49*4882a593Smuzhiyun MIPI CSI-2 virtual channel outputs. 50*4882a593Smuzhiyun 51*4882a593SmuzhiyunOptional properties: 52*4882a593Smuzhiyun- interrupts : must contain two level-triggered interrupts, 53*4882a593Smuzhiyun in order: 100 and 101; 54