1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-mipi-dsi.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Allwinner A31 MIPI-DSI Controller Device Tree Bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Chen-Yu Tsai <wens@csie.org> 11*4882a593Smuzhiyun - Maxime Ripard <mripard@kernel.org> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyunproperties: 14*4882a593Smuzhiyun compatible: 15*4882a593Smuzhiyun enum: 16*4882a593Smuzhiyun - allwinner,sun6i-a31-mipi-dsi 17*4882a593Smuzhiyun - allwinner,sun50i-a64-mipi-dsi 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun reg: 20*4882a593Smuzhiyun maxItems: 1 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun interrupts: 23*4882a593Smuzhiyun maxItems: 1 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun clocks: 26*4882a593Smuzhiyun minItems: 1 27*4882a593Smuzhiyun maxItems: 2 28*4882a593Smuzhiyun items: 29*4882a593Smuzhiyun - description: Bus Clock 30*4882a593Smuzhiyun - description: Module Clock 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun clock-names: 33*4882a593Smuzhiyun items: 34*4882a593Smuzhiyun - const: bus 35*4882a593Smuzhiyun - const: mod 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun resets: 38*4882a593Smuzhiyun maxItems: 1 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun vcc-dsi-supply: 41*4882a593Smuzhiyun description: VCC-DSI power supply of the DSI encoder 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun phys: 44*4882a593Smuzhiyun maxItems: 1 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun phy-names: 47*4882a593Smuzhiyun const: dphy 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun port: 50*4882a593Smuzhiyun type: object 51*4882a593Smuzhiyun description: 52*4882a593Smuzhiyun A port node with endpoint definitions as defined in 53*4882a593Smuzhiyun Documentation/devicetree/bindings/media/video-interfaces.txt. That 54*4882a593Smuzhiyun port should be the input endpoint, usually coming from the 55*4882a593Smuzhiyun associated TCON. 56*4882a593Smuzhiyun 57*4882a593Smuzhiyunrequired: 58*4882a593Smuzhiyun - compatible 59*4882a593Smuzhiyun - reg 60*4882a593Smuzhiyun - interrupts 61*4882a593Smuzhiyun - clocks 62*4882a593Smuzhiyun - phys 63*4882a593Smuzhiyun - phy-names 64*4882a593Smuzhiyun - resets 65*4882a593Smuzhiyun - vcc-dsi-supply 66*4882a593Smuzhiyun - port 67*4882a593Smuzhiyun 68*4882a593SmuzhiyunallOf: 69*4882a593Smuzhiyun - $ref: dsi-controller.yaml# 70*4882a593Smuzhiyun - if: 71*4882a593Smuzhiyun properties: 72*4882a593Smuzhiyun compatible: 73*4882a593Smuzhiyun contains: 74*4882a593Smuzhiyun const: allwinner,sun6i-a31-mipi-dsi 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun then: 77*4882a593Smuzhiyun properties: 78*4882a593Smuzhiyun clocks: 79*4882a593Smuzhiyun minItems: 2 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun required: 82*4882a593Smuzhiyun - clock-names 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun - if: 85*4882a593Smuzhiyun properties: 86*4882a593Smuzhiyun compatible: 87*4882a593Smuzhiyun contains: 88*4882a593Smuzhiyun const: allwinner,sun50i-a64-mipi-dsi 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun then: 91*4882a593Smuzhiyun properties: 92*4882a593Smuzhiyun clocks: 93*4882a593Smuzhiyun minItems: 1 94*4882a593Smuzhiyun 95*4882a593SmuzhiyununevaluatedProperties: false 96*4882a593Smuzhiyun 97*4882a593Smuzhiyunexamples: 98*4882a593Smuzhiyun - | 99*4882a593Smuzhiyun dsi0: dsi@1ca0000 { 100*4882a593Smuzhiyun compatible = "allwinner,sun6i-a31-mipi-dsi"; 101*4882a593Smuzhiyun reg = <0x01ca0000 0x1000>; 102*4882a593Smuzhiyun interrupts = <0 89 4>; 103*4882a593Smuzhiyun clocks = <&ccu 23>, <&ccu 96>; 104*4882a593Smuzhiyun clock-names = "bus", "mod"; 105*4882a593Smuzhiyun resets = <&ccu 4>; 106*4882a593Smuzhiyun phys = <&dphy0>; 107*4882a593Smuzhiyun phy-names = "dphy"; 108*4882a593Smuzhiyun vcc-dsi-supply = <®_dcdc1>; 109*4882a593Smuzhiyun #address-cells = <1>; 110*4882a593Smuzhiyun #size-cells = <0>; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun panel@0 { 113*4882a593Smuzhiyun compatible = "bananapi,lhr050h41", "ilitek,ili9881c"; 114*4882a593Smuzhiyun reg = <0>; 115*4882a593Smuzhiyun power-supply = <®_display>; 116*4882a593Smuzhiyun reset-gpios = <&r_pio 0 5 1>; /* PL05 */ 117*4882a593Smuzhiyun backlight = <&pwm_bl>; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun port { 121*4882a593Smuzhiyun dsi0_in_tcon0: endpoint { 122*4882a593Smuzhiyun remote-endpoint = <&tcon0_out_dsi0>; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun... 128