1*4882a593SmuzhiyunRockchip SoC MIPI RX D-PHY 2*4882a593Smuzhiyun------------------------------------------------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun- compatible: value should be one of the following 6*4882a593Smuzhiyun "rockchip,rk1808-mipi-dphy-rx" 7*4882a593Smuzhiyun "rockchip,rk3288-mipi-dphy" 8*4882a593Smuzhiyun "rockchip,rk3326-mipi-dphy" 9*4882a593Smuzhiyun "rockchip,rk3368-mipi-dphy" 10*4882a593Smuzhiyun "rockchip,rk3399-mipi-dphy" 11*4882a593Smuzhiyun "rockchip,rv1126-csi-dphy" 12*4882a593Smuzhiyun- clocks : list of clock specifiers, corresponding to entries in 13*4882a593Smuzhiyun clock-names property; 14*4882a593Smuzhiyun- clock-names: required clock name. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunMIPI RX0 D-PHY use registers in "general register files", it 17*4882a593Smuzhiyunshould be a child of the GRF. 18*4882a593SmuzhiyunMIPI TX1RX1 D-PHY have its own registers, it must have a reg property. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunOptional properties: 21*4882a593Smuzhiyun- reg: offset and length of the register set for the device. 22*4882a593Smuzhiyun- rockchip,grf: MIPI TX1RX1 D-PHY not only has its own register but also 23*4882a593Smuzhiyun the GRF, so it is only necessary for MIPI TX1RX1 D-PHY. 24*4882a593Smuzhiyun 25*4882a593Smuzhiyunport node 26*4882a593Smuzhiyun------------------- 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunThe device node should contain two 'port' child nodes, according to the bindings 29*4882a593Smuzhiyundefined in Documentation/devicetree/bindings/media/video-interfaces.txt. 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunThe first port show the sensors connected in this mipi-dphy. 32*4882a593Smuzhiyun- endpoint: 33*4882a593Smuzhiyun - remote-endpoint: Linked to a sensor with a MIPI CSI-2 video bus. 34*4882a593Smuzhiyun - data-lanes : (required) an array specifying active physical MIPI-CSI2 35*4882a593Smuzhiyun data input lanes and their mapping to logical lanes; the 36*4882a593Smuzhiyun D-PHY can't reroute lanes, so the array's content should 37*4882a593Smuzhiyun be consecutive and only its length is meaningful. 38*4882a593Smuzhiyun For CCP2, v4l2 fwnode endpoint parse this read by u32. 39*4882a593Smuzhiyun - bus-type: data bus type. Possible values are: 40*4882a593Smuzhiyun 0 - autodetect based on other properties (MIPI CSI-2 D-PHY, parallel or Bt656) 41*4882a593Smuzhiyun 1 - MIPI CSI-2 C-PHY, no support 42*4882a593Smuzhiyun 2 - MIPI CSI1, no support 43*4882a593Smuzhiyun 3 - CCP2, using for lvds 44*4882a593SmuzhiyunThe port node must contain at least one endpoint. It could have multiple endpoints 45*4882a593Smuzhiyunlinked to different sensors, but please note that they are not supposed to be 46*4882a593Smuzhiyunactived at the same time. 47*4882a593Smuzhiyun 48*4882a593SmuzhiyunThe second port should be connected to isp node. 49*4882a593Smuzhiyun- endpoint: 50*4882a593Smuzhiyun - remote-endpoint: Linked to Rockchip ISP1, which is defined 51*4882a593Smuzhiyun in rockchip-isp1.txt. 52*4882a593Smuzhiyun 53*4882a593SmuzhiyunDevice node example 54*4882a593Smuzhiyun------------------- 55*4882a593Smuzhiyun 56*4882a593Smuzhiyungrf: syscon@ff770000 { 57*4882a593Smuzhiyun compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun... 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun mipi_dphy_rx0: mipi-dphy-rx0 { 62*4882a593Smuzhiyun compatible = "rockchip,rk3399-mipi-dphy"; 63*4882a593Smuzhiyun clocks = <&cru SCLK_MIPIDPHY_REF>, 64*4882a593Smuzhiyun <&cru SCLK_DPHY_RX0_CFG>, 65*4882a593Smuzhiyun <&cru PCLK_VIO_GRF>; 66*4882a593Smuzhiyun clock-names = "dphy-ref", "dphy-cfg", "grf"; 67*4882a593Smuzhiyun power-domains = <&power RK3399_PD_VIO>; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun ports { 70*4882a593Smuzhiyun #address-cells = <1>; 71*4882a593Smuzhiyun #size-cells = <0>; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun port@0 { 74*4882a593Smuzhiyun reg = <0>; 75*4882a593Smuzhiyun #address-cells = <1>; 76*4882a593Smuzhiyun #size-cells = <0>; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun mipi_in_wcam: endpoint@0 { 79*4882a593Smuzhiyun reg = <0>; 80*4882a593Smuzhiyun remote-endpoint = <&wcam_out>; 81*4882a593Smuzhiyun data-lanes = <1 2>; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun mipi_in_ucam: endpoint@1 { 84*4882a593Smuzhiyun reg = <1>; 85*4882a593Smuzhiyun remote-endpoint = <&ucam_out>; 86*4882a593Smuzhiyun data-lanes = <1>; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun port@1 { 91*4882a593Smuzhiyun reg = <1>; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun dphy_rx0_out: endpoint { 94*4882a593Smuzhiyun remote-endpoint = <&isp0_mipi_in>; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun}; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyunexample for rv1126 node 102*4882a593Smuzhiyuncsi_dphy0 { 103*4882a593Smuzhiyun compatible = "rockchip,rv1126-csi-dphy"; 104*4882a593Smuzhiyun reg = <0xff4b0000 0x8000>; 105*4882a593Smuzhiyun clocks = <&cru PCLK_CSIPHY0>; 106*4882a593Smuzhiyun clock-names = "pclk"; 107*4882a593Smuzhiyun rockchip,grf = <&grf>; 108*4882a593Smuzhiyun status = "okay"; 109*4882a593Smuzhiyun ports { 110*4882a593Smuzhiyun #address-cells = <1>; 111*4882a593Smuzhiyun #size-cells = <0>; 112*4882a593Smuzhiyun port@0 { 113*4882a593Smuzhiyun reg = <0>; 114*4882a593Smuzhiyun #address-cells = <1>; 115*4882a593Smuzhiyun #size-cells = <0>; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun mipi_in_ucam0: endpoint@1 { 118*4882a593Smuzhiyun reg = <1>; 119*4882a593Smuzhiyun remote-endpoint = <&ucam_out0>; 120*4882a593Smuzhiyun /*data-lanes = <1 2 3 4>; //for mipi*/ 121*4882a593Smuzhiyun data-lanes = <4>; //for lvds, note: this diff to mipi 122*4882a593Smuzhiyun bus-type = <3>; //for lvds 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun port@1 { 126*4882a593Smuzhiyun reg = <1>; 127*4882a593Smuzhiyun #address-cells = <1>; 128*4882a593Smuzhiyun #size-cells = <0>; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun csidphy0_out: endpoint@0 { 131*4882a593Smuzhiyun reg = <0>; 132*4882a593Smuzhiyun remote-endpoint = <&isp_in>; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun }; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun}; 137