rockchip: Add arch timer 1Ghz support

Change-Id: I8e58b15be1823e732852a2aa76cc98813e6b4fe9
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>

arm: armv8: add no_fault_handler for rockchip minidump

Change-Id: I1ff770a0b7f8fd6aac1a2f42be765865a1dc53b9
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

common: Add MP boot support

mp_boot build from: a5185c920.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I8f8b2fe45ee87ad0a60e1dfd6f0950f052d4f1e7

common: image: Print '/reserved-memory' regions after board fdt fixup

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I0512c8af34f0581f5e01f3dd8aa0fb1e3724fe1f

arm: v8: Move cpu init from crt0_64.S to start.S

Do init before secondary cpu jump.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Idd247743048907384d7f1ed13abf42403ae813d7

arm: bootm: print generic timer ticks

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ib8305705d161e858cd8a30a820d609dffc0278ff

arm: crt0_64: Support enable Icache early for U-Boot proper

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I5db0b090cc675dd5adb2255250aff11cc97b0155

arm: crt0_64.S: don't require stack align access

That's too strict and it doesn't bring some benifits, let's disable it.
Stack align access issue was found in cpu_suspend().

Signed-off-by: Joseph C

arm: crt0_64.S: don't require stack align access

That's too strict and it doesn't bring some benifits, let's disable it.
Stack align access issue was found in cpu_suspend().

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I9442257b7bb1cf6bafa9de0b7da51d6ddb6ac150

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arm: bootm: parse nonboot cpu mpidr from fdt

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I0aca7766016911aa8fd7afde00e121ece5e17b16

arm: bootm: calculate total time at late

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I1f406b751c9eb75c25a956b36ba32aaf14a85f02

lib: bootm-fdt: fix compile error when not set CONFIG_ARCH_FIXUP_FDT_MEMORY

Showing memory banks is helpful.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I07aa5ae727d52b22e6034c193

lib: bootm-fdt: fix compile error when not set CONFIG_ARCH_FIXUP_FDT_MEMORY

Showing memory banks is helpful.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I07aa5ae727d52b22e6034c1935f133d3b9fd9b71

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arm: crt0_64.S: disable arm64 SError for usbplug

On rk356x platform usbplug mode, we found it occurs SError
when rockusb download.

Issue dump:
.....
Serial: raw, 0xfe660000
dwmmc@fe2b0000: 1,

arm: crt0_64.S: disable arm64 SError for usbplug

On rk356x platform usbplug mode, we found it occurs SError
when rockusb download.

Issue dump:
.....
Serial: raw, 0xfe660000
dwmmc@fe2b0000: 1, dwmmc@fe2c0000: 2, sdhci@fe310000: 0
Bootdev: mmc 0
RKUSB: LUN 0, dev 0, hwpart 0, sector 0x0, count 0x3a3e000
\"Error" handler, esr 0xbe000011

* Reason: Exception from SError interrupt
* PC = 0000000000013c68
* LR = 0000000000010f7c
.....

fixes:
(617c1bec46 arm: v7/v8: Enable SError/Asynchronous external abort for TPL/SPL/U-Boot)

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I6270bd0a8afdd998ac09242f21598cc8acd200ca

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arm: crt0_64.S: don't set SCTLR.A=1

The CPU is able to execute load/store instruction on unaligned address,
and we don't need to avoid special alignment scene.

Now, SCTLR.A=1 causes U-Boot data-abo

arm: crt0_64.S: don't set SCTLR.A=1

The CPU is able to execute load/store instruction on unaligned address,
and we don't need to avoid special alignment scene.

Now, SCTLR.A=1 causes U-Boot data-abort while decompressing the LZ4 kernel.

Fixes: (b25dd131e0 arm: crt0_64: Enable sctlr A/SA bit for EL3/2/1)

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I25f85e10999afb0fbb42a742c39f61c00b8c6f70

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irq: simplify the #if expression

Use CONFIG_IS_ENABLED() is better.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: If4f514cc1dfb9e0f52521954158172bba1eb8f85

arm: v7/v8: Enable SError/Asynchronous external abort for TPL/SPL/U-Boot

Add this patch to support report SError/Asynchronous external abort
immediately in current exception level.

=== issue scene

arm: v7/v8: Enable SError/Asynchronous external abort for TPL/SPL/U-Boot

Add this patch to support report SError/Asynchronous external abort
immediately in current exception level.

=== issue scene ===
When access a illegal address, It results in:
- read: Synchronous data-abort
- write: SError(64-bit)/Asynchronous external abort(32-bit)

=== 64-bit ===
EL3 SError ASynchronous exception in TPL/SPL was already
enabled in start.S and crt0_64.S which sets SCR_EL3.EA=1
and DAIF.A=0. We can test result of TPL/SPL by access address
0xfe108000 in rk3568.
Let's enable SError in U-Boot proper.

=== 32-bit ===
Let's set CPSR.A=0 to enable Asynchronous external abort, we can
test result by access address 0xfe808000 in rv1126.
Note: TPL/SPL vectors only provides "b ." for all exception entry.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Id9f660a9275f69fdc8443ad239aabf79682d95d0

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arm: crt0_64: Enable sctlr A/SA bit for EL3/2/1

Icache is enabled by default for TPL/SPL.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Idf613d816feb4766e1e1ab646cc88a86e6ca0982

arm: bootm: support CONFIG_ARM64_SWITCH_TO_AARCH32

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: If4ac9488db237ee33d3ddc4e492ec84895307b0e

arm: bootm: update amp PE switch API

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: If15d2cc2a683bb2f8d98b99c3d0e3d75002143d6

arm: bootm: support primary amp core parameter

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I2aa08d87b077bbf414f32b1f65dd1dbd68b9f199

rockchip: rv1126: rename periph device region

Adding to whitelist.txt:
CONFIG_PERIPH_DEVICE_START_ADDR
CONFIG_PERIPH_DEVICE_END_ADDR

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id:

rockchip: rv1126: rename periph device region

Adding to whitelist.txt:
CONFIG_PERIPH_DEVICE_START_ADDR
CONFIG_PERIPH_DEVICE_END_ADDR

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ia07a467489e52b7580351829768437dc67e71833

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UPSTREAM: arm: arm64 32bit address relocation

Current relocation code is limited to 21bit PC-relative addressing
which might not be enough for bigger code sizes. The following patch
increases the ad

UPSTREAM: arm: arm64 32bit address relocation

Current relocation code is limited to 21bit PC-relative addressing
which might not be enough for bigger code sizes. The following patch
increases the addressing to 32bit PC-relative. This feature is
specially interesting if U-Boot is build without optimiation (-O0) as
the text section is increased significativelly.

Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Ib54540ff040642588b4bfe2d030e5d9eabf8348c

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dm: serial: support always use uart debug mode

In this mode, uart debug is initialized depends on
configuration from pre-loader or CONFIG_UART_DEBUG_.

The serial is not care about dts "stdout-path"

dm: serial: support always use uart debug mode

In this mode, uart debug is initialized depends on
configuration from pre-loader or CONFIG_UART_DEBUG_.

The serial is not care about dts "stdout-path" and
not register into console framework any more. It's
nice to use pre-loader serial and make serial easy
to configure.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: If4c68229d76b6f1710a35e3ef9a2a91cb306fa9c

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arm: cp15: only map periph device region as dcache off for thunder-boot SPL

Don't waste time to map all 4GB region.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I24ba4e4e42545dcf3a

arm: cp15: only map periph device region as dcache off for thunder-boot SPL

Don't waste time to map all 4GB region.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I24ba4e4e42545dcf3ac6622c36995485956eae1b

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arm: shield executing arm_init_before_mmu in spl

The device do not initialize the cache and mmu in bootrom and ddr,
so the spl do not need to clear the cache and disable mmu in function
arm_init_bef

arm: shield executing arm_init_before_mmu in spl

The device do not initialize the cache and mmu in bootrom and ddr,
so the spl do not need to clear the cache and disable mmu in function
arm_init_before_mmu.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: If7b19fa762c4803dcfc58c7b16fd8236a2262729

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arm: add bootm_headers_t args for announce_and_cleanup()

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I8b709ffa378d2a802e9e9daf192c662af5588161