1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ROCKCHIP_DISPLAY_H 8 #define _ROCKCHIP_DISPLAY_H 9 10 #include <bmp_layout.h> 11 #include <drm_modes.h> 12 #include <edid.h> 13 #include <dm/ofnode.h> 14 15 #define ROCKCHIP_OUTPUT_DSI_DUAL_CHANNEL BIT(0) 16 #define ROCKCHIP_OUTPUT_DSI_DUAL_LINK BIT(1) 17 18 enum data_format { 19 ROCKCHIP_FMT_ARGB8888 = 0, 20 ROCKCHIP_FMT_RGB888, 21 ROCKCHIP_FMT_RGB565, 22 ROCKCHIP_FMT_YUV420SP = 4, 23 ROCKCHIP_FMT_YUV422SP, 24 ROCKCHIP_FMT_YUV444SP, 25 }; 26 27 enum display_mode { 28 ROCKCHIP_DISPLAY_FULLSCREEN, 29 ROCKCHIP_DISPLAY_CENTER, 30 }; 31 32 enum rockchip_cmd_type { 33 CMD_TYPE_DEFAULT, 34 CMD_TYPE_SPI, 35 CMD_TYPE_MCU 36 }; 37 38 enum rockchip_mcu_cmd { 39 MCU_WRCMD = 0, 40 MCU_WRDATA, 41 MCU_SETBYPASS, 42 }; 43 44 /* 45 * display output interface supported by rockchip lcdc 46 */ 47 #define ROCKCHIP_OUT_MODE_P888 0 48 #define ROCKCHIP_OUT_MODE_P666 1 49 #define ROCKCHIP_OUT_MODE_P565 2 50 #define ROCKCHIP_OUT_MODE_S888 8 51 #define ROCKCHIP_OUT_MODE_S888_DUMMY 12 52 #define ROCKCHIP_OUT_MODE_YUV420 14 53 /* for use special outface */ 54 #define ROCKCHIP_OUT_MODE_AAAA 15 55 56 struct rockchip_mcu_timing { 57 int mcu_pix_total; 58 int mcu_cs_pst; 59 int mcu_cs_pend; 60 int mcu_rw_pst; 61 int mcu_rw_pend; 62 int mcu_hold_mode; 63 }; 64 65 struct vop_rect { 66 int width; 67 int height; 68 }; 69 70 struct crtc_state { 71 struct udevice *dev; 72 struct rockchip_crtc *crtc; 73 void *private; 74 ofnode node; 75 int crtc_id; 76 77 int format; 78 u32 dma_addr; 79 int ymirror; 80 int rb_swap; 81 int xvir; 82 int src_x; 83 int src_y; 84 int src_w; 85 int src_h; 86 int crtc_x; 87 int crtc_y; 88 int crtc_w; 89 int crtc_h; 90 bool yuv_overlay; 91 struct rockchip_mcu_timing mcu_timing; 92 u32 dual_channel_swap; 93 struct vop_rect max_output; 94 }; 95 96 struct panel_state { 97 struct rockchip_panel *panel; 98 99 ofnode dsp_lut_node; 100 }; 101 102 struct overscan { 103 int left_margin; 104 int right_margin; 105 int top_margin; 106 int bottom_margin; 107 }; 108 109 struct connector_state { 110 struct udevice *dev; 111 const struct rockchip_connector *connector; 112 struct rockchip_bridge *bridge; 113 struct rockchip_phy *phy; 114 ofnode node; 115 116 void *private; 117 118 struct drm_display_mode mode; 119 struct overscan overscan; 120 u8 edid[EDID_SIZE * 4]; 121 int bus_format; 122 int output_mode; 123 int type; 124 int output_type; 125 int color_space; 126 unsigned int bpc; 127 128 struct { 129 u32 *lut; 130 int size; 131 } gamma; 132 }; 133 134 struct logo_info { 135 int mode; 136 char *mem; 137 bool ymirror; 138 u32 offset; 139 u32 width; 140 int height; 141 u32 bpp; 142 }; 143 144 struct rockchip_logo_cache { 145 struct list_head head; 146 char name[20]; 147 struct logo_info logo; 148 }; 149 150 struct display_state { 151 struct list_head head; 152 153 const void *blob; 154 ofnode node; 155 156 struct crtc_state crtc_state; 157 struct connector_state conn_state; 158 struct panel_state panel_state; 159 160 char ulogo_name[30]; 161 char klogo_name[30]; 162 163 struct logo_info logo; 164 int logo_mode; 165 int charge_logo_mode; 166 void *mem_base; 167 int mem_size; 168 169 int enable; 170 int is_init; 171 int is_enable; 172 }; 173 174 static inline struct rockchip_panel *state_get_panel(struct display_state *s) 175 { 176 struct panel_state *panel_state = &s->panel_state; 177 178 return panel_state->panel; 179 } 180 181 int drm_mode_vrefresh(const struct drm_display_mode *mode); 182 int display_send_mcu_cmd(struct display_state *state, u32 type, u32 val); 183 bool drm_mode_is_420(const struct drm_display_info *display, 184 struct drm_display_mode *mode); 185 186 void drm_mode_max_resolution_filter(struct hdmi_edid_data *edid_data, 187 struct vop_rect *max_output); 188 189 #endif 190