1 /* 2 * (C) Copyright 2024 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _ASM_ARCH_GRF_RV1103B_H 7 #define _ASM_ARCH_GRF_RV1103B_H 8 9 #include <common.h> 10 11 /* 12 * You can choose: 13 * (1) Directly use concrete grf reg, like struct rv1103b_cpu_grf_reg. 14 * (2) Add regs you need to struct rv1103b_grf, use rv1103b_grf directly. 15 */ 16 #define VEPU_GRF 0x20100000 17 #define NPU_GRF 0x20110000 18 #define VI_GRF 0x20120000 19 #define CPU_GRF 0x20130000 20 #define DDR_GRF 0x20140000 21 #define SYS_GRF 0x20150000 22 #define PMU_GRF 0x20160000 23 struct rv1103b_grf { 24 uint32_t reserved0[(SYS_GRF + 0xA0 - VEPU_GRF)/ 4]; 25 uint32_t gmac_con0; /* address offset: 0x00a0 */ 26 uint32_t gmac_clk_con; /* address offset: 0x00a4 */ 27 uint32_t gmac_st; /* address offset: 0x00a8 */ 28 uint32_t reserved00ac; /* address offset: 0x00ac */ 29 uint32_t macphy_con0; /* address offset: 0x00b0 */ 30 uint32_t macphy_con1; /* address offset: 0x00b4 */ 31 uint32_t reserved1[(PMU_GRF + 0x10000 - (SYS_GRF + 0xB4)) / 4]; 32 }; 33 34 check_member(rv1103b_grf, macphy_con1, SYS_GRF + 0xB4 - VEPU_GRF); 35 36 /* grf_cpu register structure define */ 37 struct rv1103b_cpu_grf_reg { 38 uint32_t con0; /* address offset: 0x0000 */ 39 uint32_t mem_cfg_uhdspra; /* address offset: 0x0004 */ 40 uint32_t status; /* address offset: 0x0008 */ 41 }; 42 43 check_member(rv1103b_cpu_grf_reg, status, 0x0008); 44 45 /* grf_ddr register structure define */ 46 struct rv1103b_ddr_grf_reg { 47 uint32_t con0; /* address offset: 0x0000 */ 48 uint32_t con1; /* address offset: 0x0004 */ 49 uint32_t con2; /* address offset: 0x0008 */ 50 uint32_t con3; /* address offset: 0x000c */ 51 uint32_t con4; /* address offset: 0x0010 */ 52 uint32_t con5; /* address offset: 0x0014 */ 53 uint32_t con6; /* address offset: 0x0018 */ 54 uint32_t con7; /* address offset: 0x001c */ 55 uint32_t con8; /* address offset: 0x0020 */ 56 uint32_t con9; /* address offset: 0x0024 */ 57 uint32_t con10; /* address offset: 0x0028 */ 58 uint32_t con11; /* address offset: 0x002c */ 59 uint32_t con12; /* address offset: 0x0030 */ 60 uint32_t con13; /* address offset: 0x0034 */ 61 uint32_t con14; /* address offset: 0x0038 */ 62 uint32_t reserved003c[17]; /* address offset: 0x003c */ 63 uint32_t probe_ctrl; /* address offset: 0x0080 */ 64 uint32_t reserved0084[39]; /* address offset: 0x0084 */ 65 uint32_t status8; /* address offset: 0x0120 */ 66 uint32_t status9; /* address offset: 0x0124 */ 67 }; 68 69 check_member(rv1103b_ddr_grf_reg, status9, 0x0124); 70 71 /* grf_npu register structure define */ 72 struct rv1103b_npu_grf_reg { 73 uint32_t mem_con_spra; /* address offset: 0x0000 */ 74 }; 75 76 check_member(rv1103b_npu_grf_reg, mem_con_spra, 0x0000); 77 78 /* grf_pmu register structure define */ 79 struct rv1103b_pmu_grf_reg { 80 uint32_t soc_con0; /* address offset: 0x0000 */ 81 uint32_t soc_con1; /* address offset: 0x0004 */ 82 uint32_t soc_con2; /* address offset: 0x0008 */ 83 uint32_t soc_con3; /* address offset: 0x000c */ 84 uint32_t soc_con4; /* address offset: 0x0010 */ 85 uint32_t soc_con5; /* address offset: 0x0014 */ 86 uint32_t soc_con6; /* address offset: 0x0018 */ 87 uint32_t soc_con7; /* address offset: 0x001c */ 88 uint32_t soc_con8; /* address offset: 0x0020 */ 89 uint32_t soc_con9; /* address offset: 0x0024 */ 90 uint32_t soc_con10; /* address offset: 0x0028 */ 91 uint32_t reserved002c; /* address offset: 0x002c */ 92 uint32_t soc_status0; /* address offset: 0x0030 */ 93 uint32_t reserved0034[3]; /* address offset: 0x0034 */ 94 uint32_t men_con; /* address offset: 0x0040 */ 95 uint32_t reserved0044[3]; /* address offset: 0x0044 */ 96 uint32_t soc_special0; /* address offset: 0x0050 */ 97 uint32_t reserved0054[3]; /* address offset: 0x0054 */ 98 uint32_t soc_preroll_int_con; /* address offset: 0x0060 */ 99 uint32_t reserved0064[103]; /* address offset: 0x0064 */ 100 uint32_t os_reg0; /* address offset: 0x0200 */ 101 uint32_t os_reg1; /* address offset: 0x0204 */ 102 uint32_t os_reg2; /* address offset: 0x0208 */ 103 uint32_t os_reg3; /* address offset: 0x020c */ 104 uint32_t os_reg4; /* address offset: 0x0210 */ 105 uint32_t os_reg5; /* address offset: 0x0214 */ 106 uint32_t os_reg6; /* address offset: 0x0218 */ 107 uint32_t os_reg7; /* address offset: 0x021c */ 108 uint32_t os_reg8; /* address offset: 0x0220 */ 109 uint32_t os_reg9; /* address offset: 0x0224 */ 110 uint32_t os_reg10; /* address offset: 0x0228 */ 111 uint32_t os_reg11; /* address offset: 0x022c */ 112 uint32_t reset_function_status; /* address offset: 0x0230 */ 113 uint32_t reset_function_clr; /* address offset: 0x0234 */ 114 }; 115 116 check_member(rv1103b_pmu_grf_reg, reset_function_clr, 0x0234); 117 118 /* grf_sys register structure define */ 119 struct rv1103b_sys_grf_reg { 120 uint32_t peri_con0; /* address offset: 0x0000 */ 121 uint32_t peri_con1; /* address offset: 0x0004 */ 122 uint32_t peri_con2; /* address offset: 0x0008 */ 123 uint32_t peri_hprot2_con; /* address offset: 0x000c */ 124 uint32_t peri_status; /* address offset: 0x0010 */ 125 uint32_t reserved0014[3]; /* address offset: 0x0014 */ 126 uint32_t audio_con0; /* address offset: 0x0020 */ 127 uint32_t audio_con1; /* address offset: 0x0024 */ 128 uint32_t reserved0028[2]; /* address offset: 0x0028 */ 129 uint32_t usbotg_con0; /* address offset: 0x0030 */ 130 uint32_t usbotg_con1; /* address offset: 0x0034 */ 131 uint32_t reserved0038[2]; /* address offset: 0x0038 */ 132 uint32_t usbotg_status0; /* address offset: 0x0040 */ 133 uint32_t usbotg_status1; /* address offset: 0x0044 */ 134 uint32_t usbotg_status2; /* address offset: 0x0048 */ 135 uint32_t reserved004c; /* address offset: 0x004c */ 136 uint32_t usbphy_con0; /* address offset: 0x0050 */ 137 uint32_t usbphy_con1; /* address offset: 0x0054 */ 138 uint32_t usbphy_con2; /* address offset: 0x0058 */ 139 uint32_t usbphy_con3; /* address offset: 0x005c */ 140 uint32_t usbphy_status; /* address offset: 0x0060 */ 141 uint32_t reserved0064[3]; /* address offset: 0x0064 */ 142 uint32_t saradc_con; /* address offset: 0x0070 */ 143 uint32_t tsadc_con; /* address offset: 0x0074 */ 144 uint32_t otp_con; /* address offset: 0x0078 */ 145 uint32_t reserved007c; /* address offset: 0x007c */ 146 uint32_t mem_con_spra; /* address offset: 0x0080 */ 147 uint32_t mem_con_dpra; /* address offset: 0x0084 */ 148 uint32_t mem_con_rom; /* address offset: 0x0088 */ 149 uint32_t mem_con_gate; /* address offset: 0x008c */ 150 uint32_t biu_con0; /* address offset: 0x0090 */ 151 uint32_t reserved0094; /* address offset: 0x0094 */ 152 uint32_t biu_status0; /* address offset: 0x0098 */ 153 uint32_t biu_status1; /* address offset: 0x009c */ 154 uint32_t gmac_con0; /* address offset: 0x00a0 */ 155 uint32_t gmac_clk_con; /* address offset: 0x00a4 */ 156 uint32_t gmac_st; /* address offset: 0x00a8 */ 157 uint32_t reserved00ac; /* address offset: 0x00ac */ 158 uint32_t macphy_con0; /* address offset: 0x00b0 */ 159 uint32_t macphy_con1; /* address offset: 0x00b4 */ 160 uint32_t reserved00b8[18]; /* address offset: 0x00b8 */ 161 uint32_t usbotg_sig_detect_con; /* address offset: 0x0100 */ 162 uint32_t usbotg_sig_detect_status; /* address offset: 0x0104 */ 163 uint32_t usbotg_sig_detect_clr; /* address offset: 0x0108 */ 164 uint32_t reserved010c; /* address offset: 0x010c */ 165 uint32_t usbotg_linestate_detect_con; /* address offset: 0x0110 */ 166 uint32_t usbotg_disconnect_detect_con; /* address offset: 0x0114 */ 167 uint32_t usbotg_bvalid_detect_con; /* address offset: 0x0118 */ 168 uint32_t usbotg_id_detect_con; /* address offset: 0x011c */ 169 uint32_t reserved0120[56]; /* address offset: 0x0120 */ 170 uint32_t cache_peri_addr_start; /* address offset: 0x0200 */ 171 uint32_t cache_peri_addr_end; /* address offset: 0x0204 */ 172 uint32_t hpmcu_code_addr_start; /* address offset: 0x0208 */ 173 uint32_t hpmcu_sram_addr_start; /* address offset: 0x020c */ 174 uint32_t hpmcu_exsram_addr_start; /* address offset: 0x0210 */ 175 uint32_t hpmcu_cache_misc; /* address offset: 0x0214 */ 176 uint32_t hpmcu_cache_status; /* address offset: 0x0218 */ 177 uint32_t reserved021c[377]; /* address offset: 0x021c */ 178 uint32_t chip_id; /* address offset: 0x0800 */ 179 uint32_t chip_version; /* address offset: 0x0804 */ 180 }; 181 182 check_member(rv1103b_sys_grf_reg, chip_version, 0x0804); 183 184 /* grf_vepu register structure define */ 185 struct rv1103b_vepu_grf_reg { 186 uint32_t mem_con_spra; /* address offset: 0x0000 */ 187 uint32_t mem_con_dpra; /* address offset: 0x0004 */ 188 }; 189 190 check_member(rv1103b_vepu_grf_reg, mem_con_dpra, 0x0004); 191 192 /* grf_vi register structure define */ 193 struct rv1103b_vi_grf_reg { 194 uint32_t mem_con_spra; /* address offset: 0x0000 */ 195 uint32_t mem_con_dpra; /* address offset: 0x0004 */ 196 uint32_t reserved0008; /* address offset: 0x0008 */ 197 uint32_t vi_hprot2_con; /* address offset: 0x000c */ 198 uint32_t status; /* address offset: 0x0010 */ 199 uint32_t csiphy_con; /* address offset: 0x0014 */ 200 uint32_t csiphy_status; /* address offset: 0x0018 */ 201 uint32_t reserved001c; /* address offset: 0x001c */ 202 uint32_t misc_con; /* address offset: 0x0020 */ 203 uint32_t sdmmc_det_cnt; /* address offset: 0x0024 */ 204 uint32_t sdmmc_sig_detect_con; /* address offset: 0x0028 */ 205 uint32_t sdmmc_sig_detect_status; /* address offset: 0x002c */ 206 uint32_t sdmmc_status_clr; /* address offset: 0x0030 */ 207 }; 208 209 check_member(rv1103b_vi_grf_reg, sdmmc_status_clr, 0x0030); 210 211 #endif /* _ASM_ARCH_GRF_RV1103B_H */ 212