1 /* 2 * (C) Copyright 2021 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _ASM_ARCH_GRF_RK3576_H 7 #define _ASM_ARCH_GRF_RK3576_H 8 9 #include <common.h> 10 11 /* bigcore_grf register structure define */ 12 struct rk3576_bigcore_grf_reg { 13 uint32_t reserved0000[11]; /* address offset: 0x0000 */ 14 uint32_t cpu_status[1]; /* address offset: 0x002c */ 15 uint32_t reserved0030; /* address offset: 0x0030 */ 16 uint32_t cpu_con[2]; /* address offset: 0x0034 */ 17 uint32_t cpu_mem_cfg_hdsprf; /* address offset: 0x003c */ 18 uint32_t reserved0040; /* address offset: 0x0040 */ 19 uint32_t cpu_mem_cfg_hssprf; /* address offset: 0x0044 */ 20 }; 21 22 check_member(rk3576_bigcore_grf_reg, cpu_mem_cfg_hssprf, 0x0044); 23 24 /* cci_grf register structure define */ 25 struct rk3576_cci_grf_reg { 26 uint32_t cci_con[5]; /* address offset: 0x0000 */ 27 uint32_t reserved0014[8]; /* address offset: 0x0014 */ 28 uint32_t cci_status[5]; /* address offset: 0x0034 */ 29 uint32_t reserved0048[3]; /* address offset: 0x0048 */ 30 uint32_t cci_mem_cfg_hdsprf; /* address offset: 0x0054 */ 31 }; 32 33 check_member(rk3576_cci_grf_reg, cci_mem_cfg_hdsprf, 0x0054); 34 35 /* center_grf register structure define */ 36 struct rk3576_center_grf_reg { 37 uint32_t soc_con[6]; /* address offset: 0x0000 */ 38 }; 39 40 check_member(rk3576_center_grf_reg, soc_con, 0x0000); 41 42 /* combo_pipe_phy_grf register structure define */ 43 struct rk3576_combo_pipe_phy_grf_reg { 44 uint32_t pipe_con[5]; /* address offset: 0x0000 */ 45 uint32_t reserved0014[8]; /* address offset: 0x0014 */ 46 uint32_t pipe_status[1]; /* address offset: 0x0034 */ 47 uint32_t reserved0038[18]; /* address offset: 0x0038 */ 48 uint32_t lfps_det_con; /* address offset: 0x0080 */ 49 uint32_t reserved0084[7]; /* address offset: 0x0084 */ 50 uint32_t phy_int_en; /* address offset: 0x00a0 */ 51 uint32_t phy_int_status; /* address offset: 0x00a4 */ 52 }; 53 54 check_member(rk3576_combo_pipe_phy_grf_reg, phy_int_status, 0x00a4); 55 56 /* csidphy_grf register structure define */ 57 struct rk3576_csidphy_grf_reg { 58 uint32_t con[1]; /* address offset: 0x0000 */ 59 uint32_t reserved0004[31]; /* address offset: 0x0004 */ 60 uint32_t status[1]; /* address offset: 0x0080 */ 61 }; 62 63 check_member(rk3576_csidphy_grf_reg, status, 0x0080); 64 65 /* dcphy_grf register structure define */ 66 struct rk3576_dcphy_grf_reg { 67 uint32_t con[2]; /* address offset: 0x0000 */ 68 uint32_t reserved0008[30]; /* address offset: 0x0008 */ 69 uint32_t status[3]; /* address offset: 0x0080 */ 70 }; 71 72 check_member(rk3576_dcphy_grf_reg, status, 0x0080); 73 74 /* ddr_grf register structure define */ 75 struct rk3576_ddr_grf_reg { 76 uint32_t cha_con[20]; /* address offset: 0x0000 */ 77 uint32_t reserved0050[44]; /* address offset: 0x0050 */ 78 uint32_t chb_con[20]; /* address offset: 0x0100 */ 79 uint32_t reserved0150[44]; /* address offset: 0x0150 */ 80 uint32_t cha_status[12]; /* address offset: 0x0200 */ 81 uint32_t reserved0230[52]; /* address offset: 0x0230 */ 82 uint32_t chb_status[12]; /* address offset: 0x0300 */ 83 uint32_t reserved0330[128]; /* address offset: 0x0330 */ 84 uint32_t cha_phy_con[1]; /* address offset: 0x0530 */ 85 uint32_t chb_phy_con[1]; /* address offset: 0x0534 */ 86 uint32_t cha_phy_status[1]; /* address offset: 0x0538 */ 87 uint32_t chb_phy_status[1]; /* address offset: 0x053c */ 88 uint32_t common_con[6]; /* address offset: 0x0540 */ 89 uint32_t reserved0558[10]; /* address offset: 0x0558 */ 90 uint32_t status[1]; /* address offset: 0x0580 */ 91 }; 92 93 check_member(rk3576_ddr_grf_reg, status, 0x0580); 94 95 /* gpu_grf register structure define */ 96 struct rk3576_gpu_grf_reg { 97 uint32_t reserved0000[8]; /* address offset: 0x0000 */ 98 uint32_t gpu_con[1]; /* address offset: 0x0020 */ 99 uint32_t reserved0024[6]; /* address offset: 0x0024 */ 100 uint32_t gpu_mem_cfg_hdsprf; /* address offset: 0x003c */ 101 uint32_t gpu_mem_cfg_hsspra; /* address offset: 0x0040 */ 102 uint32_t reserved0044; /* address offset: 0x0044 */ 103 uint32_t gpu_mem_cfg_uhdpdprf_low; /* address offset: 0x0048 */ 104 }; 105 106 check_member(rk3576_gpu_grf_reg, gpu_mem_cfg_uhdpdprf_low, 0x0048); 107 108 /* usb2phy_grf register structure define */ 109 struct rk3576_usb2phy_grf_reg { 110 uint32_t con[6]; /* address offset: 0x0000 */ 111 uint32_t reserved0018[2]; /* address offset: 0x0018 */ 112 uint32_t ls_con; /* address offset: 0x0020 */ 113 uint32_t dis_con; /* address offset: 0x0024 */ 114 uint32_t bvalid_con; /* address offset: 0x0028 */ 115 uint32_t id_con; /* address offset: 0x002c */ 116 uint32_t vbusvalid_con; /* address offset: 0x0030 */ 117 uint32_t reserved0034[3]; /* address offset: 0x0034 */ 118 uint32_t dbg_con[1]; /* address offset: 0x0040 */ 119 uint32_t linest_timeout; /* address offset: 0x0044 */ 120 uint32_t linest_deb; /* address offset: 0x0048 */ 121 uint32_t rx_timeout; /* address offset: 0x004c */ 122 uint32_t seq_limt; /* address offset: 0x0050 */ 123 uint32_t linest_cnt_st; /* address offset: 0x0054 */ 124 uint32_t dbg_st; /* address offset: 0x0058 */ 125 uint32_t rx_cnt_st; /* address offset: 0x005c */ 126 uint32_t reserved0060[8]; /* address offset: 0x0060 */ 127 uint32_t st[1]; /* address offset: 0x0080 */ 128 uint32_t reserved0084[15]; /* address offset: 0x0084 */ 129 uint32_t int_en; /* address offset: 0x00c0 */ 130 uint32_t int_st; /* address offset: 0x00c4 */ 131 uint32_t int_st_clr; /* address offset: 0x00c8 */ 132 uint32_t reserved00cc; /* address offset: 0x00cc */ 133 uint32_t detclk_sel; /* address offset: 0x00d0 */ 134 }; 135 136 check_member(rk3576_usb2phy_grf_reg, detclk_sel, 0x00d0); 137 138 /* hdptxphy_grf register structure define */ 139 struct rk3576_hdptxphy_grf_reg { 140 uint32_t con[2]; /* address offset: 0x0000 */ 141 uint32_t reserved0008[30]; /* address offset: 0x0008 */ 142 uint32_t status[1]; /* address offset: 0x0080 */ 143 }; 144 145 check_member(rk3576_hdptxphy_grf_reg, status, 0x0080); 146 147 /* litcore_grf register structure define */ 148 struct rk3576_litcore_grf_reg { 149 uint32_t reserved0000[11]; /* address offset: 0x0000 */ 150 uint32_t cpu_status[1]; /* address offset: 0x002c */ 151 uint32_t reserved0030; /* address offset: 0x0030 */ 152 uint32_t cpu_con[2]; /* address offset: 0x0034 */ 153 uint32_t cpu_mem_cfg_hdsprf; /* address offset: 0x003c */ 154 uint32_t reserved0040; /* address offset: 0x0040 */ 155 uint32_t cpu_mem_cfg_hssprf; /* address offset: 0x0044 */ 156 }; 157 158 check_member(rk3576_litcore_grf_reg, cpu_mem_cfg_hssprf, 0x0044); 159 160 /* mphy_grf register structure define */ 161 struct rk3576_mphy_grf_reg { 162 uint32_t con[2]; /* address offset: 0x0000 */ 163 uint32_t status[1]; /* address offset: 0x0008 */ 164 }; 165 166 check_member(rk3576_mphy_grf_reg, status, 0x0008); 167 168 /* npu_grf register structure define */ 169 struct rk3576_npu_grf_reg { 170 uint32_t reserved0000[2]; /* address offset: 0x0000 */ 171 uint32_t mem_con[3]; /* address offset: 0x0008 */ 172 uint32_t memgate_con[2]; /* address offset: 0x0014 */ 173 uint32_t rknnst; /* address offset: 0x001c */ 174 uint32_t nsp_slv_addr; /* address offset: 0x0020 */ 175 uint32_t reserved0024; /* address offset: 0x0024 */ 176 uint32_t nputop_con; /* address offset: 0x0028 */ 177 uint32_t stcalib; /* address offset: 0x002c */ 178 uint32_t start_addr; /* address offset: 0x0030 */ 179 uint32_t end_addr; /* address offset: 0x0034 */ 180 uint32_t nputop_st; /* address offset: 0x0038 */ 181 uint32_t reserved003c[7]; /* address offset: 0x003c */ 182 uint32_t cache_maintain; /* address offset: 0x0058 */ 183 uint32_t rv_base_addr; /* address offset: 0x005c */ 184 uint32_t reserved0060[3]; /* address offset: 0x0060 */ 185 uint32_t urgent_con[4]; /* address offset: 0x006c */ 186 }; 187 188 check_member(rk3576_npu_grf_reg, urgent_con, 0x006c); 189 190 /* php_grf register structure define */ 191 struct rk3576_php_grf_reg { 192 uint32_t mmubp_st; /* address offset: 0x0000 */ 193 uint32_t mmubp_con[1]; /* address offset: 0x0004 */ 194 uint32_t mmu0_con; /* address offset: 0x0008 */ 195 uint32_t mmu1_con; /* address offset: 0x000c */ 196 uint32_t mem_con[3]; /* address offset: 0x0010 */ 197 uint32_t sata0_con; /* address offset: 0x001c */ 198 uint32_t sata1_con; /* address offset: 0x0020 */ 199 uint32_t usb3otg1_status_lat[2]; /* address offset: 0x0024 */ 200 uint32_t usb3otg1_status_cb; /* address offset: 0x002c */ 201 uint32_t usb3otg1_status; /* address offset: 0x0030 */ 202 uint32_t usb3otg1_con[2]; /* address offset: 0x0034 */ 203 uint32_t reserved003c[3]; /* address offset: 0x003c */ 204 uint32_t pciepipe_con[1]; /* address offset: 0x0048 */ 205 uint32_t reserved004c[2]; /* address offset: 0x004c */ 206 uint32_t pcie_clkreq_st; /* address offset: 0x0054 */ 207 uint32_t reserved0058; /* address offset: 0x0058 */ 208 uint32_t mmu0_st[5]; /* address offset: 0x005c */ 209 uint32_t mmu1_st[5]; /* address offset: 0x0070 */ 210 }; 211 212 check_member(rk3576_php_grf_reg, mmu1_st, 0x0070); 213 214 /* pmu0_grf register structure define */ 215 struct rk3576_pmu0_grf_reg { 216 uint32_t soc_con[7]; /* address offset: 0x0000 */ 217 uint32_t reserved001c; /* address offset: 0x001c */ 218 uint32_t io_ret_con[2]; /* address offset: 0x0020 */ 219 uint32_t reserved0028[2]; /* address offset: 0x0028 */ 220 uint32_t mem_con; /* address offset: 0x0030 */ 221 uint32_t reserved0034[3]; /* address offset: 0x0034 */ 222 uint32_t os_reg[8]; /* address offset: 0x0040 */ 223 }; 224 225 check_member(rk3576_pmu0_grf_reg, os_reg, 0x0040); 226 227 /* pmu0_sgrf register structure define */ 228 struct rk3576_pmu0_sgrf_reg { 229 uint32_t soc_con[3]; /* address offset: 0x0000 */ 230 uint32_t reserved000c[13]; /* address offset: 0x000c */ 231 uint32_t dcie_con[8]; /* address offset: 0x0040 */ 232 uint32_t dcie_wlock; /* address offset: 0x0060 */ 233 }; 234 235 check_member(rk3576_pmu0_sgrf_reg, dcie_wlock, 0x0060); 236 237 /* pmu1_grf register structure define */ 238 struct rk3576_pmu1_grf_reg { 239 uint32_t soc_con[8]; /* address offset: 0x0000 */ 240 uint32_t reserved0020[12]; /* address offset: 0x0020 */ 241 uint32_t biu_con; /* address offset: 0x0050 */ 242 uint32_t biu_status; /* address offset: 0x0054 */ 243 uint32_t reserved0058[2]; /* address offset: 0x0058 */ 244 uint32_t soc_status; /* address offset: 0x0060 */ 245 uint32_t reserved0064[7]; /* address offset: 0x0064 */ 246 uint32_t mem_con[2]; /* address offset: 0x0080 */ 247 uint32_t reserved0088[30]; /* address offset: 0x0088 */ 248 uint32_t func_rst_status; /* address offset: 0x0100 */ 249 uint32_t func_rst_clr; /* address offset: 0x0104 */ 250 uint32_t reserved0108[2]; /* address offset: 0x0108 */ 251 uint32_t sd_detect_con; /* address offset: 0x0110 */ 252 uint32_t sd_detect_sts; /* address offset: 0x0114 */ 253 uint32_t sd_detect_clr; /* address offset: 0x0118 */ 254 uint32_t sd_detect_cnt; /* address offset: 0x011c */ 255 uint32_t reserved0120[56]; /* address offset: 0x0120 */ 256 uint32_t os_reg[16]; /* address offset: 0x0200 */ 257 }; 258 259 check_member(rk3576_pmu1_grf_reg, os_reg, 0x0200); 260 261 /* pmu1_sgrf register structure define */ 262 struct rk3576_pmu1_sgrf_reg { 263 uint32_t soc_con[18]; /* address offset: 0x0000 */ 264 }; 265 266 check_member(rk3576_pmu1_sgrf_reg, soc_con, 0x0000); 267 268 /* sdgmac_grf register structure define */ 269 struct rk3576_sdgmac_grf_reg { 270 uint32_t mem_con[5]; /* address offset: 0x0000 */ 271 uint32_t reserved0014[2]; /* address offset: 0x0014 */ 272 uint32_t gmac_st[1]; /* address offset: 0x001c */ 273 uint32_t gmac0_con; /* address offset: 0x0020 */ 274 uint32_t gmac1_con; /* address offset: 0x0024 */ 275 uint32_t gmac0_tp[2]; /* address offset: 0x0028 */ 276 uint32_t gmac1_tp[2]; /* address offset: 0x0030 */ 277 uint32_t gmac0_cmd; /* address offset: 0x0038 */ 278 uint32_t gmac1_cmd; /* address offset: 0x003c */ 279 uint32_t reserved0040[2]; /* address offset: 0x0040 */ 280 uint32_t mem_gate_con; /* address offset: 0x0048 */ 281 }; 282 283 check_member(rk3576_sdgmac_grf_reg, mem_gate_con, 0x0048); 284 285 /* sys_grf register structure define */ 286 struct rk3576_sys_grf_reg { 287 uint32_t soc_con[13]; /* address offset: 0x0000 */ 288 uint32_t reserved0034[3]; /* address offset: 0x0034 */ 289 uint32_t biu_con[6]; /* address offset: 0x0040 */ 290 uint32_t reserved0058[2]; /* address offset: 0x0058 */ 291 uint32_t biu_status[8]; /* address offset: 0x0060 */ 292 uint32_t mem_con[19]; /* address offset: 0x0080 */ 293 uint32_t reserved00cc[29]; /* address offset: 0x00cc */ 294 uint32_t soc_status[2]; /* address offset: 0x0140 */ 295 uint32_t memfault_status[2]; /* address offset: 0x0148 */ 296 uint32_t reserved0150[12]; /* address offset: 0x0150 */ 297 uint32_t soc_code; /* address offset: 0x0180 */ 298 uint32_t reserved0184[3]; /* address offset: 0x0184 */ 299 uint32_t soc_version; /* address offset: 0x0190 */ 300 uint32_t reserved0194[3]; /* address offset: 0x0194 */ 301 uint32_t chip_id; /* address offset: 0x01a0 */ 302 uint32_t reserved01a4[3]; /* address offset: 0x01a4 */ 303 uint32_t chip_version; /* address offset: 0x01b0 */ 304 }; 305 306 check_member(rk3576_sys_grf_reg, chip_version, 0x01b0); 307 308 /* sys_sgrf register structure define */ 309 struct rk3576_sys_sgrf_reg { 310 uint32_t ddr_bank_hash_ctrl; /* address offset: 0x0000 */ 311 uint32_t ddr_bank_mask[4]; /* address offset: 0x0004 */ 312 uint32_t ddr_rank_mask[1]; /* address offset: 0x0014 */ 313 uint32_t reserved0018[2]; /* address offset: 0x0018 */ 314 uint32_t soc_con[21]; /* address offset: 0x0020 */ 315 uint32_t reserved0074[3]; /* address offset: 0x0074 */ 316 uint32_t dmac0_con[10]; /* address offset: 0x0080 */ 317 uint32_t reserved00a8[22]; /* address offset: 0x00a8 */ 318 uint32_t dmac1_con[10]; /* address offset: 0x0100 */ 319 uint32_t reserved0128[22]; /* address offset: 0x0128 */ 320 uint32_t dmac2_con[10]; /* address offset: 0x0180 */ 321 uint32_t reserved01a8[22]; /* address offset: 0x01a8 */ 322 uint32_t key_con[2]; /* address offset: 0x0200 */ 323 uint32_t key_wlock; /* address offset: 0x0208 */ 324 uint32_t reserved020c[13]; /* address offset: 0x020c */ 325 uint32_t soc_status; /* address offset: 0x0240 */ 326 uint32_t reserved0244[47]; /* address offset: 0x0244 */ 327 uint32_t ip_info_con; /* address offset: 0x0300 */ 328 }; 329 330 check_member(rk3576_sys_sgrf_reg, ip_info_con, 0x0300); 331 332 /* ufs_grf register structure define */ 333 struct rk3576_ufs_grf_reg { 334 uint32_t clk_ctrl; /* address offset: 0x0000 */ 335 uint32_t uic_src_sel; /* address offset: 0x0004 */ 336 uint32_t ufs_state_ie; /* address offset: 0x0008 */ 337 uint32_t ufs_state_is; /* address offset: 0x000c */ 338 uint32_t ufs_state; /* address offset: 0x0010 */ 339 uint32_t reserved0014[13]; /* address offset: 0x0014 */ 340 }; 341 342 check_member(rk3576_ufs_grf_reg, reserved0014, 0x0014); 343 344 /* usbdpphy_grf register structure define */ 345 struct rk3576_usbdpphy_grf_reg { 346 uint32_t reserved0000; /* address offset: 0x0000 */ 347 uint32_t con[3]; /* address offset: 0x0004 */ 348 uint32_t reserved0010[29]; /* address offset: 0x0010 */ 349 uint32_t status[1]; /* address offset: 0x0084 */ 350 uint32_t reserved0088[14]; /* address offset: 0x0088 */ 351 uint32_t lfps_det_con; /* address offset: 0x00c0 */ 352 uint32_t int_en; /* address offset: 0x00c4 */ 353 uint32_t int_status; /* address offset: 0x00c8 */ 354 }; 355 356 check_member(rk3576_usbdpphy_grf_reg, int_status, 0x00c8); 357 358 /* usb_grf register structure define */ 359 struct rk3576_usb_grf_reg { 360 uint32_t mmubp_st; /* address offset: 0x0000 */ 361 uint32_t mmubp_con; /* address offset: 0x0004 */ 362 uint32_t mmu2_con; /* address offset: 0x0008 */ 363 uint32_t mem_con0; /* address offset: 0x000c */ 364 uint32_t mem_con1; /* address offset: 0x0010 */ 365 uint32_t reserved0014[2]; /* address offset: 0x0014 */ 366 uint32_t usb3otg0_status_lat[2]; /* address offset: 0x001c */ 367 uint32_t usb3otg0_status_cb; /* address offset: 0x0024 */ 368 uint32_t usb3otg0_status; /* address offset: 0x0028 */ 369 uint32_t usb3otg0_con[2]; /* address offset: 0x002c */ 370 uint32_t reserved0034[4]; /* address offset: 0x0034 */ 371 uint32_t mmu2_st[5]; /* address offset: 0x0044 */ 372 uint32_t mem_con[1]; /* address offset: 0x0058 */ 373 }; 374 375 check_member(rk3576_usb_grf_reg, mem_con, 0x0058); 376 377 /* vo0_grf register structure define */ 378 struct rk3576_vo0_grf_reg { 379 uint32_t soc_con[34]; /* address offset: 0x0000 */ 380 uint32_t reserved0088[14]; /* address offset: 0x0088 */ 381 uint32_t soc_st[6]; /* address offset: 0x00c0 */ 382 uint32_t reserved00d8[6]; /* address offset: 0x00d8 */ 383 uint32_t hdcp0_rng_con[1]; /* address offset: 0x00f0 */ 384 uint32_t reserved00f4; /* address offset: 0x00f4 */ 385 uint32_t hdcp0_rng_st[1]; /* address offset: 0x00f8 */ 386 }; 387 388 check_member(rk3576_vo0_grf_reg, hdcp0_rng_st, 0x00f8); 389 390 /* vo1_grf register structure define */ 391 struct rk3576_vo1_grf_reg { 392 uint32_t soc_con[35]; /* address offset: 0x0000 */ 393 uint32_t reserved008c[13]; /* address offset: 0x008c */ 394 uint32_t soc_st[3]; /* address offset: 0x00c0 */ 395 uint32_t reserved00cc[9]; /* address offset: 0x00cc */ 396 uint32_t hdcp1_rng_con[1]; /* address offset: 0x00f0 */ 397 uint32_t reserved00f4; /* address offset: 0x00f4 */ 398 uint32_t hdcp1_rng_st[1]; /* address offset: 0x00f8 */ 399 }; 400 401 check_member(rk3576_vo1_grf_reg, hdcp1_rng_st, 0x00f8); 402 403 /* vop_grf register structure define */ 404 struct rk3576_vop_grf_reg { 405 uint32_t reserved0000; /* address offset: 0x0000 */ 406 uint32_t soc_con[3]; /* address offset: 0x0004 */ 407 }; 408 409 check_member(rk3576_vop_grf_reg, soc_con, 0x0004); 410 411 #endif /* _ASM_ARCH_GRF_RK3576_H */ 412