1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <drm/drm_mipi_dsi.h> 8 9 #include <config.h> 10 #include <common.h> 11 #include <errno.h> 12 #include <asm/unaligned.h> 13 #include <asm/io.h> 14 #include <asm/hardware.h> 15 #include <dm/device.h> 16 #include <dm/read.h> 17 #include <dm/of_access.h> 18 #include <syscon.h> 19 #include <asm/arch-rockchip/clock.h> 20 #include <linux/iopoll.h> 21 22 #include "rockchip_display.h" 23 #include "rockchip_crtc.h" 24 #include "rockchip_connector.h" 25 #include "rockchip_panel.h" 26 #include "rockchip_phy.h" 27 28 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l))) 29 30 #define DSI_VERSION 0x00 31 #define DSI_PWR_UP 0x04 32 #define RESET 0 33 #define POWERUP BIT(0) 34 35 #define DSI_CLKMGR_CFG 0x08 36 #define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8) 37 #define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0) 38 39 #define DSI_DPI_VCID 0x0c 40 #define DPI_VID(vid) (((vid) & 0x3) << 0) 41 42 #define DSI_DPI_COLOR_CODING 0x10 43 #define EN18_LOOSELY BIT(8) 44 #define DPI_COLOR_CODING_16BIT_1 0x0 45 #define DPI_COLOR_CODING_16BIT_2 0x1 46 #define DPI_COLOR_CODING_16BIT_3 0x2 47 #define DPI_COLOR_CODING_18BIT_1 0x3 48 #define DPI_COLOR_CODING_18BIT_2 0x4 49 #define DPI_COLOR_CODING_24BIT 0x5 50 51 #define DSI_DPI_CFG_POL 0x14 52 #define COLORM_ACTIVE_LOW BIT(4) 53 #define SHUTD_ACTIVE_LOW BIT(3) 54 #define HSYNC_ACTIVE_LOW BIT(2) 55 #define VSYNC_ACTIVE_LOW BIT(1) 56 #define DATAEN_ACTIVE_LOW BIT(0) 57 58 #define DSI_DPI_LP_CMD_TIM 0x18 59 #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) 60 #define INVACT_LPCMD_TIME(p) ((p) & 0xff) 61 62 #define DSI_DBI_VCID 0x1c 63 #define DBI_VCID(x) UPDATE(x, 1, 0) 64 #define DSI_DBI_CFG 0x20 65 #define DSI_DBI_CMDSIZE 0x28 66 67 #define DSI_PCKHDL_CFG 0x2c 68 #define CRC_RX_EN BIT(4) 69 #define ECC_RX_EN BIT(3) 70 #define BTA_EN BIT(2) 71 #define EOTP_RX_EN BIT(1) 72 #define EOTP_TX_EN BIT(0) 73 #define DSI_MODE_CFG 0x34 74 #define CMD_VIDEO_MODE BIT(0) 75 #define COMMAND_MODE BIT(0) 76 #define VIDEO_MODE 0 77 #define DSI_VID_MODE_CFG 0x38 78 #define VPG_EN BIT(16) 79 #define LP_CMD_EN BIT(15) 80 #define FRAME_BTA_ACK BIT(14) 81 #define LP_HFP_EN BIT(13) 82 #define LP_HBP_EN BIT(12) 83 #define LP_VACT_EN BIT(11) 84 #define LP_VFP_EN BIT(10) 85 #define LP_VBP_EN BIT(9) 86 #define LP_VSA_EN BIT(8) 87 #define VID_MODE_TYPE_BURST_SYNC_PULSES 0x0 88 #define VID_MODE_TYPE_BURST_SYNC_EVENTS 0x1 89 #define VID_MODE_TYPE_BURST 0x2 90 91 #define DSI_VID_PKT_SIZE 0x3c 92 #define VID_PKT_SIZE(p) (((p) & 0x3fff) << 0) 93 #define VID_PKT_MAX_SIZE 0x3fff 94 95 #define DSI_VID_NUM_CHUMKS 0x40 96 #define DSI_VID_NULL_PKT_SIZE 0x44 97 #define DSI_VID_HSA_TIME 0x48 98 #define DSI_VID_HBP_TIME 0x4c 99 #define DSI_VID_HLINE_TIME 0x50 100 #define DSI_VID_VSA_LINES 0x54 101 #define DSI_VID_VBP_LINES 0x58 102 #define DSI_VID_VFP_LINES 0x5c 103 #define DSI_VID_VACTIVE_LINES 0x60 104 #define DSI_EDPI_CMD_SIZE 0x64 105 #define DSI_CMD_MODE_CFG 0x68 106 #define MAX_RD_PKT_SIZE BIT(24) 107 #define DCS_LW_TX BIT(19) 108 #define DCS_SR_0P_TX BIT(18) 109 #define DCS_SW_1P_TX BIT(17) 110 #define DCS_SW_0P_TX BIT(16) 111 #define GEN_LW_TX BIT(14) 112 #define GEN_SR_2P_TX BIT(13) 113 #define GEN_SR_1P_TX BIT(12) 114 #define GEN_SR_0P_TX BIT(11) 115 #define GEN_SW_2P_TX BIT(10) 116 #define GEN_SW_1P_TX BIT(9) 117 #define GEN_SW_0P_TX BIT(8) 118 #define ACK_RQST_EN BIT(1) 119 #define TEAR_FX_EN BIT(0) 120 121 #define DSI_GEN_HDR 0x6c 122 #define GEN_HDATA(data) (((data) & 0xffff) << 8) 123 #define GEN_HDATA_MASK (0xffff << 8) 124 #define GEN_HTYPE(type) (((type) & 0xff) << 0) 125 #define GEN_HTYPE_MASK 0xff 126 127 #define DSI_GEN_PLD_DATA 0x70 128 129 #define DSI_CMD_PKT_STATUS 0x74 130 #define GEN_CMD_EMPTY BIT(0) 131 #define GEN_CMD_FULL BIT(1) 132 #define GEN_PLD_W_EMPTY BIT(2) 133 #define GEN_PLD_W_FULL BIT(3) 134 #define GEN_PLD_R_EMPTY BIT(4) 135 #define GEN_PLD_R_FULL BIT(5) 136 #define GEN_RD_CMD_BUSY BIT(6) 137 138 #define DSI_TO_CNT_CFG 0x78 139 #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16) 140 #define LPRX_TO_CNT(p) ((p) & 0xffff) 141 142 #define DSI_BTA_TO_CNT 0x8c 143 #define DSI_LPCLK_CTRL 0x94 144 #define AUTO_CLKLANE_CTRL BIT(1) 145 #define PHY_TXREQUESTCLKHS BIT(0) 146 147 #define DSI_PHY_TMR_LPCLK_CFG 0x98 148 #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16) 149 #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff) 150 151 #define DSI_PHY_TMR_CFG 0x9c 152 #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24) 153 #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16) 154 #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff) 155 156 #define DSI_PHY_RSTZ 0xa0 157 #define PHY_ENFORCEPLL BIT(3) 158 #define PHY_ENABLECLK BIT(2) 159 #define PHY_RSTZ BIT(1) 160 #define PHY_SHUTDOWNZ BIT(0) 161 162 #define DSI_PHY_IF_CFG 0xa4 163 #define N_LANES(n) ((((n) - 1) & 0x3) << 0) 164 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) 165 166 #define DSI_PHY_STATUS 0xb0 167 #define PHY_STOPSTATE0LANE BIT(4) 168 #define PHY_STOPSTATECLKLANE BIT(2) 169 #define PHY_LOCK BIT(0) 170 #define PHY_STOPSTATELANE (PHY_STOPSTATE0LANE | \ 171 PHY_STOPSTATECLKLANE) 172 173 #define DSI_PHY_TST_CTRL0 0xb4 174 #define PHY_TESTCLK BIT(1) 175 #define PHY_TESTCLR BIT(0) 176 177 #define DSI_PHY_TST_CTRL1 0xb8 178 #define PHY_TESTEN BIT(16) 179 #define PHY_TESTDOUT_SHIFT 8 180 #define PHY_TESTDIN_MASK GENMASK(7, 0) 181 #define PHY_TESTDIN(x) UPDATE(x, 7, 0) 182 183 #define DSI_INT_ST0 0xbc 184 #define DSI_INT_ST1 0xc0 185 #define DSI_INT_MSK0 0xc4 186 #define DSI_INT_MSK1 0xc8 187 188 #define PHY_STATUS_TIMEOUT_US 10000 189 #define CMD_PKT_STATUS_TIMEOUT_US 20000 190 191 /* Test Code: 0x44 (HS RX Control of Lane 0) */ 192 #define HSFREQRANGE(x) UPDATE(x, 6, 1) 193 /* Test Code: 0x17 (PLL Input Divider Ratio) */ 194 #define INPUT_DIV(x) UPDATE(x, 6, 0) 195 /* Test Code: 0x18 (PLL Loop Divider Ratio) */ 196 #define FEEDBACK_DIV_LO(x) UPDATE(x, 4, 0) 197 #define FEEDBACK_DIV_HI(x) (BIT(7) | UPDATE(x, 3, 0)) 198 199 #define GRF_REG_FIELD(reg, lsb, msb) (((reg) << 10) | ((lsb) << 5) | (msb)) 200 201 enum grf_reg_fields { 202 DPIUPDATECFG, 203 DPISHUTDN, 204 DPICOLORM, 205 VOPSEL, 206 TURNREQUEST, 207 TURNDISABLE, 208 FORCETXSTOPMODE, 209 FORCERXMODE, 210 ENABLE_N, 211 MASTERSLAVEZ, 212 ENABLECLK, 213 BASEDIR, 214 MAX_FIELDS, 215 }; 216 217 struct dw_mipi_dsi_plat_data { 218 const u32 *dsi0_grf_reg_fields; 219 const u32 *dsi1_grf_reg_fields; 220 unsigned long max_bit_rate_per_lane; 221 }; 222 223 struct mipi_dphy { 224 /* Non-SNPS PHY */ 225 struct rockchip_phy *phy; 226 227 u16 input_div; 228 u16 feedback_div; 229 }; 230 231 struct dw_mipi_dsi { 232 struct udevice *dev; 233 void *base; 234 void *grf; 235 int id; 236 struct dw_mipi_dsi *master; 237 struct dw_mipi_dsi *slave; 238 bool prepared; 239 240 unsigned int lane_mbps; /* per lane */ 241 u32 channel; 242 u32 lanes; 243 u32 format; 244 u32 mode_flags; 245 struct mipi_dphy dphy; 246 struct drm_display_mode mode; 247 248 const struct dw_mipi_dsi_plat_data *pdata; 249 }; 250 251 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val) 252 { 253 writel(val, dsi->base + reg); 254 } 255 256 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) 257 { 258 return readl(dsi->base + reg); 259 } 260 261 static inline void dsi_update_bits(struct dw_mipi_dsi *dsi, 262 u32 reg, u32 mask, u32 val) 263 { 264 u32 orig, tmp; 265 266 orig = dsi_read(dsi, reg); 267 tmp = orig & ~mask; 268 tmp |= val & mask; 269 dsi_write(dsi, reg, tmp); 270 } 271 272 static void grf_field_write(struct dw_mipi_dsi *dsi, enum grf_reg_fields index, 273 unsigned int val) 274 { 275 const u32 field = dsi->id ? dsi->pdata->dsi1_grf_reg_fields[index] : 276 dsi->pdata->dsi0_grf_reg_fields[index]; 277 u16 reg; 278 u8 msb, lsb; 279 280 if (!field) 281 return; 282 283 reg = (field >> 10) & 0x3ffff; 284 lsb = (field >> 5) & 0x1f; 285 msb = (field >> 0) & 0x1f; 286 287 rk_clrsetreg(dsi->grf + reg, GENMASK(msb, lsb), val << lsb); 288 } 289 290 static inline void dpishutdn_assert(struct dw_mipi_dsi *dsi) 291 { 292 grf_field_write(dsi, DPISHUTDN, 1); 293 } 294 295 static inline void dpishutdn_deassert(struct dw_mipi_dsi *dsi) 296 { 297 grf_field_write(dsi, DPISHUTDN, 0); 298 } 299 300 static int genif_wait_w_pld_fifo_not_full(struct dw_mipi_dsi *dsi) 301 { 302 u32 sts; 303 int ret; 304 305 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 306 sts, !(sts & GEN_PLD_W_FULL), 307 CMD_PKT_STATUS_TIMEOUT_US); 308 if (ret < 0) { 309 printf("generic write payload fifo is full\n"); 310 return ret; 311 } 312 313 return 0; 314 } 315 316 static int genif_wait_cmd_fifo_not_full(struct dw_mipi_dsi *dsi) 317 { 318 u32 sts; 319 int ret; 320 321 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 322 sts, !(sts & GEN_CMD_FULL), 323 CMD_PKT_STATUS_TIMEOUT_US); 324 if (ret < 0) { 325 printf("generic write cmd fifo is full\n"); 326 return ret; 327 } 328 329 return 0; 330 } 331 332 static int genif_wait_write_fifo_empty(struct dw_mipi_dsi *dsi) 333 { 334 u32 sts; 335 u32 mask; 336 int ret; 337 338 mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY; 339 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 340 sts, (sts & mask) == mask, 341 CMD_PKT_STATUS_TIMEOUT_US); 342 if (ret < 0) { 343 printf("generic write fifo is full\n"); 344 return ret; 345 } 346 347 return 0; 348 } 349 350 static inline void mipi_dphy_enableclk_assert(struct dw_mipi_dsi *dsi) 351 { 352 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, PHY_ENABLECLK); 353 udelay(1); 354 } 355 356 static inline void mipi_dphy_enableclk_deassert(struct dw_mipi_dsi *dsi) 357 { 358 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, 0); 359 udelay(1); 360 } 361 362 static inline void mipi_dphy_shutdownz_assert(struct dw_mipi_dsi *dsi) 363 { 364 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, 0); 365 udelay(1); 366 } 367 368 static inline void mipi_dphy_shutdownz_deassert(struct dw_mipi_dsi *dsi) 369 { 370 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, PHY_SHUTDOWNZ); 371 udelay(1); 372 } 373 374 static inline void mipi_dphy_rstz_assert(struct dw_mipi_dsi *dsi) 375 { 376 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_RSTZ, 0); 377 udelay(1); 378 } 379 380 static inline void mipi_dphy_rstz_deassert(struct dw_mipi_dsi *dsi) 381 { 382 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_RSTZ, PHY_RSTZ); 383 udelay(1); 384 } 385 386 static inline void testif_testclk_assert(struct dw_mipi_dsi *dsi) 387 { 388 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK, PHY_TESTCLK); 389 udelay(1); 390 } 391 392 static inline void testif_testclk_deassert(struct dw_mipi_dsi *dsi) 393 { 394 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK, 0); 395 udelay(1); 396 } 397 398 static inline void testif_testclr_assert(struct dw_mipi_dsi *dsi) 399 { 400 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR, PHY_TESTCLR); 401 udelay(1); 402 } 403 404 static inline void testif_testclr_deassert(struct dw_mipi_dsi *dsi) 405 { 406 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR, 0); 407 udelay(1); 408 } 409 410 static inline void testif_testen_assert(struct dw_mipi_dsi *dsi) 411 { 412 dsi_update_bits(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN, PHY_TESTEN); 413 udelay(1); 414 } 415 416 static inline void testif_testen_deassert(struct dw_mipi_dsi *dsi) 417 { 418 dsi_update_bits(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN, 0); 419 udelay(1); 420 } 421 422 static inline void testif_set_data(struct dw_mipi_dsi *dsi, u8 data) 423 { 424 dsi_update_bits(dsi, DSI_PHY_TST_CTRL1, 425 PHY_TESTDIN_MASK, PHY_TESTDIN(data)); 426 udelay(1); 427 } 428 429 static inline u8 testif_get_data(struct dw_mipi_dsi *dsi) 430 { 431 return dsi_read(dsi, DSI_PHY_TST_CTRL1) >> PHY_TESTDOUT_SHIFT; 432 } 433 434 static void testif_test_code_write(struct dw_mipi_dsi *dsi, u8 test_code) 435 { 436 testif_testclk_assert(dsi); 437 testif_set_data(dsi, test_code); 438 testif_testen_assert(dsi); 439 testif_testclk_deassert(dsi); 440 testif_testen_deassert(dsi); 441 } 442 443 static void testif_test_data_write(struct dw_mipi_dsi *dsi, u8 test_data) 444 { 445 testif_testclk_deassert(dsi); 446 testif_set_data(dsi, test_data); 447 testif_testclk_assert(dsi); 448 } 449 450 static void testif_write(struct dw_mipi_dsi *dsi, u8 test_code, u8 test_data) 451 { 452 testif_test_code_write(dsi, test_code); 453 testif_test_data_write(dsi, test_data); 454 455 dev_dbg(dsi->dev, 456 "test_code=0x%02x, test_data=0x%02x, monitor_data=0x%02x\n", 457 test_code, test_data, testif_get_data(dsi)); 458 } 459 460 static int mipi_dphy_power_on(struct dw_mipi_dsi *dsi) 461 { 462 u32 mask, val; 463 int ret; 464 465 mipi_dphy_shutdownz_deassert(dsi); 466 mipi_dphy_rstz_deassert(dsi); 467 mdelay(2); 468 469 if (dsi->dphy.phy) { 470 rockchip_phy_set_mode(dsi->dphy.phy, PHY_MODE_VIDEO_MIPI); 471 rockchip_phy_power_on(dsi->dphy.phy); 472 } 473 474 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, 475 val, val & PHY_LOCK, PHY_STATUS_TIMEOUT_US); 476 if (ret < 0) { 477 dev_err(dsi->dev, "PHY is not locked\n"); 478 return ret; 479 } 480 481 udelay(200); 482 483 mask = PHY_STOPSTATELANE; 484 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, 485 val, (val & mask) == mask, 486 PHY_STATUS_TIMEOUT_US); 487 if (ret < 0) { 488 dev_err(dsi->dev, "lane module is not in stop state\n"); 489 return ret; 490 } 491 492 udelay(10); 493 494 return 0; 495 } 496 497 static void dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) 498 { 499 /* Table 5-1 Frequency Ranges */ 500 const struct { 501 unsigned long max_lane_mbps; 502 u8 hsfreqrange; 503 } hsfreqrange_table[] = { 504 { 90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01}, 505 { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12}, 506 { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23}, 507 { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15}, 508 { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07}, 509 { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09}, 510 { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a}, 511 {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b}, 512 {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c}, 513 {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c} 514 }; 515 u8 hsfreqrange, counter; 516 unsigned int index, txbyteclkhs; 517 u16 n, m; 518 519 for (index = 0; index < ARRAY_SIZE(hsfreqrange_table); index++) 520 if (dsi->lane_mbps <= hsfreqrange_table[index].max_lane_mbps) 521 break; 522 523 if (index == ARRAY_SIZE(hsfreqrange_table)) 524 --index; 525 526 hsfreqrange = hsfreqrange_table[index].hsfreqrange; 527 testif_write(dsi, 0x44, HSFREQRANGE(hsfreqrange)); 528 529 txbyteclkhs = dsi->lane_mbps >> 3; 530 counter = txbyteclkhs * 60 / 1000; 531 testif_write(dsi, 0x60, 0x80 | counter); 532 testif_write(dsi, 0x70, 0x80 | counter); 533 534 n = dsi->dphy.input_div - 1; 535 m = dsi->dphy.feedback_div - 1; 536 testif_write(dsi, 0x19, 0x30); 537 testif_write(dsi, 0x17, INPUT_DIV(n)); 538 testif_write(dsi, 0x18, FEEDBACK_DIV_LO(m)); 539 testif_write(dsi, 0x18, FEEDBACK_DIV_HI(m >> 5)); 540 } 541 542 static unsigned long dw_mipi_dsi_get_lane_rate(struct dw_mipi_dsi *dsi) 543 { 544 const struct drm_display_mode *mode = &dsi->mode; 545 unsigned long max_lane_rate = dsi->pdata->max_bit_rate_per_lane; 546 unsigned long lane_rate; 547 unsigned int value; 548 int bpp, lanes; 549 u64 tmp; 550 551 /* optional override of the desired bandwidth */ 552 value = dev_read_u32_default(dsi->dev, "rockchip,lane-rate", 0); 553 if (value > 0) 554 return value * 1000 * 1000; 555 556 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 557 if (bpp < 0) 558 bpp = 24; 559 560 lanes = dsi->slave ? dsi->lanes * 2 : dsi->lanes; 561 tmp = (u64)mode->clock * 1000 * bpp; 562 do_div(tmp, lanes); 563 564 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */ 565 tmp *= 10; 566 do_div(tmp, 9); 567 568 if (tmp > max_lane_rate) 569 lane_rate = max_lane_rate; 570 else 571 lane_rate = tmp; 572 573 return lane_rate; 574 } 575 576 static void dw_mipi_dsi_set_pll(struct dw_mipi_dsi *dsi, unsigned long rate) 577 { 578 unsigned long fin, fout; 579 unsigned long fvco_min, fvco_max, best_freq = 984000000; 580 u8 min_prediv, max_prediv; 581 u8 _prediv, best_prediv = 2; 582 u16 _fbdiv, best_fbdiv = 82; 583 u32 min_delta = ~0U; 584 585 fin = 24000000; 586 fout = rate; 587 588 /* 5Mhz < Fref / N < 40MHz, 80MHz < Fvco < 1500Mhz */ 589 min_prediv = DIV_ROUND_UP(fin, 40000000); 590 max_prediv = fin / 5000000; 591 fvco_min = 80000000; 592 fvco_max = 1500000000; 593 594 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) { 595 u64 tmp, _fout; 596 u32 delta; 597 598 /* Fvco = Fref * M / N */ 599 tmp = (u64)fout * _prediv; 600 do_div(tmp, fin); 601 _fbdiv = tmp; 602 603 /* 604 * Due to the use of a "by 2 pre-scaler," the range of the 605 * feedback multiplication value M is limited to even division 606 * numbers, and m must be greater than 12, less than 1000. 607 */ 608 if (_fbdiv <= 12 || _fbdiv >= 1000) 609 continue; 610 611 if (_fbdiv % 2) 612 ++_fbdiv; 613 614 _fout = (u64)_fbdiv * fin; 615 do_div(_fout, _prediv); 616 617 if (_fout < fvco_min || _fout > fvco_max) 618 continue; 619 620 delta = abs(fout - _fout); 621 if (!delta) { 622 best_prediv = _prediv; 623 best_fbdiv = _fbdiv; 624 best_freq = _fout; 625 break; 626 } else if (delta < min_delta) { 627 best_prediv = _prediv; 628 best_fbdiv = _fbdiv; 629 best_freq = _fout; 630 min_delta = delta; 631 } 632 } 633 634 dsi->lane_mbps = best_freq / 1000 / 1000; 635 dsi->dphy.input_div = best_prediv; 636 dsi->dphy.feedback_div = best_fbdiv; 637 if (dsi->slave) { 638 dsi->slave->lane_mbps = dsi->lane_mbps; 639 dsi->slave->dphy.input_div = dsi->dphy.input_div; 640 dsi->slave->dphy.feedback_div = dsi->dphy.feedback_div; 641 } 642 if (dsi->master) { 643 dsi->master->lane_mbps = dsi->lane_mbps; 644 dsi->master->dphy.input_div = dsi->dphy.input_div; 645 dsi->master->dphy.feedback_div = dsi->dphy.feedback_div; 646 } 647 } 648 649 static int dw_mipi_dsi_read_from_fifo(struct dw_mipi_dsi *dsi, 650 const struct mipi_dsi_msg *msg) 651 { 652 u8 *payload = msg->rx_buf; 653 u16 length; 654 u32 val; 655 int ret; 656 657 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 658 val, !(val & GEN_RD_CMD_BUSY), 5000); 659 if (ret) { 660 printf("entire response isn't stored in the FIFO\n"); 661 return ret; 662 } 663 664 /* Receive payload */ 665 for (length = msg->rx_len; length; length -= 4) { 666 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 667 val, !(val & GEN_PLD_R_EMPTY), 5000); 668 if (ret) { 669 printf("Read payload FIFO is empty\n"); 670 return ret; 671 } 672 673 val = dsi_read(dsi, DSI_GEN_PLD_DATA); 674 675 switch (length) { 676 case 3: 677 payload[2] = (val >> 16) & 0xff; 678 /* Fall through */ 679 case 2: 680 payload[1] = (val >> 8) & 0xff; 681 /* Fall through */ 682 case 1: 683 payload[0] = val & 0xff; 684 return 0; 685 } 686 687 payload[0] = (val >> 0) & 0xff; 688 payload[1] = (val >> 8) & 0xff; 689 payload[2] = (val >> 16) & 0xff; 690 payload[3] = (val >> 24) & 0xff; 691 payload += 4; 692 } 693 694 return 0; 695 } 696 697 static int dw_mipi_dsi_turn_on_peripheral(struct dw_mipi_dsi *dsi) 698 { 699 dpishutdn_assert(dsi); 700 udelay(20); 701 dpishutdn_deassert(dsi); 702 703 return 0; 704 } 705 706 static int dw_mipi_dsi_shutdown_peripheral(struct dw_mipi_dsi *dsi) 707 { 708 dpishutdn_deassert(dsi); 709 udelay(20); 710 dpishutdn_assert(dsi); 711 712 return 0; 713 } 714 715 static ssize_t dw_mipi_dsi_transfer(struct dw_mipi_dsi *dsi, 716 const struct mipi_dsi_msg *msg) 717 { 718 struct mipi_dsi_packet packet; 719 int ret; 720 int val; 721 722 if (msg->flags & MIPI_DSI_MSG_USE_LPM) { 723 dsi_update_bits(dsi, DSI_VID_MODE_CFG, LP_CMD_EN, LP_CMD_EN); 724 dsi_update_bits(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS, 0); 725 } else { 726 dsi_update_bits(dsi, DSI_VID_MODE_CFG, LP_CMD_EN, 0); 727 dsi_update_bits(dsi, DSI_LPCLK_CTRL, 728 PHY_TXREQUESTCLKHS, PHY_TXREQUESTCLKHS); 729 } 730 731 switch (msg->type) { 732 case MIPI_DSI_SHUTDOWN_PERIPHERAL: 733 return dw_mipi_dsi_shutdown_peripheral(dsi); 734 case MIPI_DSI_TURN_ON_PERIPHERAL: 735 return dw_mipi_dsi_turn_on_peripheral(dsi); 736 case MIPI_DSI_DCS_SHORT_WRITE: 737 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SW_0P_TX, 738 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 739 DCS_SW_0P_TX : 0); 740 break; 741 case MIPI_DSI_DCS_SHORT_WRITE_PARAM: 742 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SW_1P_TX, 743 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 744 DCS_SW_1P_TX : 0); 745 break; 746 case MIPI_DSI_DCS_LONG_WRITE: 747 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_LW_TX, 748 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 749 DCS_LW_TX : 0); 750 break; 751 case MIPI_DSI_DCS_READ: 752 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SR_0P_TX, 753 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 754 DCS_SR_0P_TX : 0); 755 break; 756 case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE: 757 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, MAX_RD_PKT_SIZE, 758 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 759 MAX_RD_PKT_SIZE : 0); 760 break; 761 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: 762 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_0P_TX, 763 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 764 GEN_SW_0P_TX : 0); 765 break; 766 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: 767 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_1P_TX, 768 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 769 GEN_SW_1P_TX : 0); 770 break; 771 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: 772 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_2P_TX, 773 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 774 GEN_SW_2P_TX : 0); 775 break; 776 case MIPI_DSI_GENERIC_LONG_WRITE: 777 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_LW_TX, 778 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 779 GEN_LW_TX : 0); 780 break; 781 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: 782 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_0P_TX, 783 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 784 GEN_SR_0P_TX : 0); 785 break; 786 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: 787 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_1P_TX, 788 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 789 GEN_SR_1P_TX : 0); 790 break; 791 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: 792 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_2P_TX, 793 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 794 GEN_SR_2P_TX : 0); 795 break; 796 default: 797 return -EINVAL; 798 } 799 800 if (msg->flags & MIPI_DSI_MSG_REQ_ACK) 801 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, 802 ACK_RQST_EN, ACK_RQST_EN); 803 804 /* create a packet to the DSI protocol */ 805 ret = mipi_dsi_create_packet(&packet, msg); 806 if (ret) { 807 printf("failed to create packet: %d\n", ret); 808 return ret; 809 } 810 811 /* Send payload */ 812 while (DIV_ROUND_UP(packet.payload_length, 4)) { 813 /* 814 * Alternatively, you can always keep the FIFO 815 * nearly full by monitoring the FIFO state until 816 * it is not full, and then writea single word of data. 817 * This solution is more resource consuming 818 * but it simultaneously avoids FIFO starvation, 819 * making it possible to use FIFO sizes smaller than 820 * the amount of data of the longest packet to be written. 821 */ 822 ret = genif_wait_w_pld_fifo_not_full(dsi); 823 if (ret) 824 return ret; 825 826 if (packet.payload_length < 4) { 827 /* send residu payload */ 828 val = 0; 829 memcpy(&val, packet.payload, packet.payload_length); 830 dsi_write(dsi, DSI_GEN_PLD_DATA, val); 831 packet.payload_length = 0; 832 } else { 833 val = get_unaligned_le32(packet.payload); 834 dsi_write(dsi, DSI_GEN_PLD_DATA, val); 835 packet.payload += 4; 836 packet.payload_length -= 4; 837 } 838 } 839 840 ret = genif_wait_cmd_fifo_not_full(dsi); 841 if (ret) 842 return ret; 843 844 /* Send packet header */ 845 val = get_unaligned_le32(packet.header); 846 dsi_write(dsi, DSI_GEN_HDR, val); 847 848 ret = genif_wait_write_fifo_empty(dsi); 849 if (ret) 850 return ret; 851 852 if (msg->rx_len) { 853 ret = dw_mipi_dsi_read_from_fifo(dsi, msg); 854 if (ret < 0) 855 return ret; 856 } 857 858 if (dsi->slave) { 859 ret = dw_mipi_dsi_transfer(dsi->slave, msg); 860 if (ret < 0) 861 return ret; 862 } 863 864 return msg->rx_len ? msg->rx_len : msg->tx_len; 865 } 866 867 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi) 868 { 869 u32 val = LP_VACT_EN | LP_VFP_EN | LP_VBP_EN | LP_VSA_EN | 870 LP_HFP_EN | LP_HBP_EN; 871 872 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP) 873 val &= ~LP_HFP_EN; 874 875 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP) 876 val &= ~LP_HBP_EN; 877 878 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 879 val |= VID_MODE_TYPE_BURST; 880 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 881 val |= VID_MODE_TYPE_BURST_SYNC_PULSES; 882 else 883 val |= VID_MODE_TYPE_BURST_SYNC_EVENTS; 884 885 dsi_write(dsi, DSI_VID_MODE_CFG, val); 886 887 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 888 dsi_update_bits(dsi, DSI_LPCLK_CTRL, 889 AUTO_CLKLANE_CTRL, AUTO_CLKLANE_CTRL); 890 } 891 892 static void dw_mipi_dsi_enable(struct dw_mipi_dsi *dsi) 893 { 894 const struct drm_display_mode *mode = &dsi->mode; 895 896 dsi_update_bits(dsi, DSI_LPCLK_CTRL, 897 PHY_TXREQUESTCLKHS, PHY_TXREQUESTCLKHS); 898 899 dsi_write(dsi, DSI_PWR_UP, RESET); 900 901 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 902 dsi_update_bits(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE, VIDEO_MODE); 903 } else { 904 dsi_write(dsi, DSI_DBI_VCID, DBI_VCID(dsi->channel)); 905 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_LW_TX, 0); 906 dsi_write(dsi, DSI_EDPI_CMD_SIZE, mode->hdisplay); 907 dsi_update_bits(dsi, DSI_MODE_CFG, 908 CMD_VIDEO_MODE, COMMAND_MODE); 909 } 910 911 dsi_write(dsi, DSI_PWR_UP, POWERUP); 912 913 if (dsi->slave) 914 dw_mipi_dsi_enable(dsi->slave); 915 } 916 917 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi) 918 { 919 dsi_write(dsi, DSI_PWR_UP, RESET); 920 dsi_write(dsi, DSI_LPCLK_CTRL, 0); 921 dsi_write(dsi, DSI_EDPI_CMD_SIZE, 0); 922 dsi_update_bits(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE, COMMAND_MODE); 923 dsi_write(dsi, DSI_PWR_UP, POWERUP); 924 925 if (dsi->slave) 926 dw_mipi_dsi_disable(dsi->slave); 927 } 928 929 static void dw_mipi_dsi_post_disable(struct dw_mipi_dsi *dsi) 930 { 931 if (!dsi->prepared) 932 return; 933 934 if (dsi->master) 935 dw_mipi_dsi_post_disable(dsi->master); 936 937 dsi_write(dsi, DSI_PWR_UP, RESET); 938 dsi_write(dsi, DSI_PHY_RSTZ, 0); 939 940 dsi->prepared = false; 941 942 if (dsi->slave) 943 dw_mipi_dsi_post_disable(dsi->slave); 944 } 945 946 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) 947 { 948 u32 esc_clk_div; 949 950 dsi_write(dsi, DSI_PWR_UP, RESET); 951 952 /* The maximum value of the escape clock frequency is 20MHz */ 953 esc_clk_div = DIV_ROUND_UP(dsi->lane_mbps >> 3, 20); 954 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) | 955 TX_ESC_CLK_DIVIDSION(esc_clk_div)); 956 } 957 958 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi, 959 struct drm_display_mode *mode) 960 { 961 u32 val = 0, color = 0; 962 963 switch (dsi->format) { 964 case MIPI_DSI_FMT_RGB888: 965 color = DPI_COLOR_CODING_24BIT; 966 break; 967 case MIPI_DSI_FMT_RGB666: 968 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY; 969 break; 970 case MIPI_DSI_FMT_RGB666_PACKED: 971 color = DPI_COLOR_CODING_18BIT_1; 972 break; 973 case MIPI_DSI_FMT_RGB565: 974 color = DPI_COLOR_CODING_16BIT_1; 975 break; 976 } 977 978 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 979 val |= VSYNC_ACTIVE_LOW; 980 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 981 val |= HSYNC_ACTIVE_LOW; 982 983 dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel)); 984 dsi_write(dsi, DSI_DPI_COLOR_CODING, color); 985 dsi_write(dsi, DSI_DPI_CFG_POL, val); 986 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4) 987 | INVACT_LPCMD_TIME(4)); 988 } 989 990 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi) 991 { 992 u32 val = CRC_RX_EN | ECC_RX_EN | BTA_EN | EOTP_TX_EN; 993 994 if (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) 995 val &= ~EOTP_TX_EN; 996 997 dsi_write(dsi, DSI_PCKHDL_CFG, val); 998 } 999 1000 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi, 1001 struct drm_display_mode *mode) 1002 { 1003 dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay)); 1004 } 1005 1006 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) 1007 { 1008 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000)); 1009 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00); 1010 } 1011 1012 /* Get lane byte clock cycles. */ 1013 static int dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi, 1014 u32 hcomponent) 1015 { 1016 u32 lbcc; 1017 1018 lbcc = hcomponent * dsi->lane_mbps * 1000 / 8; 1019 1020 if (!dsi->mode.clock) 1021 return 0; 1022 1023 return DIV_ROUND_CLOSEST(lbcc, dsi->mode.clock); 1024 } 1025 1026 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi) 1027 { 1028 int htotal, hsa, hbp, lbcc; 1029 struct drm_display_mode *mode = &dsi->mode; 1030 1031 htotal = mode->htotal; 1032 hsa = mode->hsync_end - mode->hsync_start; 1033 hbp = mode->htotal - mode->hsync_end; 1034 1035 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal); 1036 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc); 1037 1038 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa); 1039 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc); 1040 1041 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp); 1042 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc); 1043 } 1044 1045 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi) 1046 { 1047 u32 vactive, vsa, vfp, vbp; 1048 struct drm_display_mode *mode = &dsi->mode; 1049 1050 vactive = mode->vdisplay; 1051 vsa = mode->vsync_end - mode->vsync_start; 1052 vfp = mode->vsync_start - mode->vdisplay; 1053 vbp = mode->vtotal - mode->vsync_end; 1054 1055 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive); 1056 dsi_write(dsi, DSI_VID_VSA_LINES, vsa); 1057 dsi_write(dsi, DSI_VID_VFP_LINES, vfp); 1058 dsi_write(dsi, DSI_VID_VBP_LINES, vbp); 1059 } 1060 1061 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi) 1062 { 1063 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x14) 1064 | PHY_LP2HS_TIME(0x10) | MAX_RD_TIME(10000)); 1065 1066 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40) 1067 | PHY_CLKLP2HS_TIME(0x40)); 1068 } 1069 1070 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi) 1071 { 1072 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) | 1073 N_LANES(dsi->lanes)); 1074 } 1075 1076 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi) 1077 { 1078 dsi_read(dsi, DSI_INT_ST0); 1079 dsi_read(dsi, DSI_INT_ST1); 1080 dsi_write(dsi, DSI_INT_MSK0, 0); 1081 dsi_write(dsi, DSI_INT_MSK1, 0); 1082 } 1083 1084 static int dw_mipi_dsi_connector_init(struct display_state *state) 1085 { 1086 struct connector_state *conn_state = &state->conn_state; 1087 struct dw_mipi_dsi *dsi = dev_get_priv(conn_state->dev); 1088 1089 dsi->dphy.phy = conn_state->phy; 1090 1091 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 1092 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 1093 conn_state->type = DRM_MODE_CONNECTOR_DSI; 1094 1095 if (dsi->id) { 1096 struct udevice *dev; 1097 int ret; 1098 1099 ret = uclass_get_device_by_name(UCLASS_DISPLAY, "dsi@ff960000", 1100 &dev); 1101 if (ret) 1102 return ret; 1103 1104 dsi->master = dev_get_priv(dev); 1105 if (!dsi->master) 1106 return -ENODEV; 1107 1108 conn_state->output_type = ROCKCHIP_OUTPUT_DSI_DUAL_LINK; 1109 } 1110 1111 if (dsi->lanes > 4) { 1112 struct udevice *dev; 1113 int ret; 1114 1115 ret = uclass_get_device_by_name(UCLASS_DISPLAY, 1116 #if defined(CONFIG_ROCKCHIP_RK3288) 1117 "dsi@ff964000", 1118 #else 1119 "dsi@ff968000", 1120 #endif 1121 &dev); 1122 if (ret) 1123 return ret; 1124 1125 dsi->slave = dev_get_priv(dev); 1126 if (!dsi->slave) 1127 return -ENODEV; 1128 1129 dsi->lanes /= 2; 1130 dsi->slave->lanes = dsi->lanes; 1131 dsi->slave->format = dsi->format; 1132 dsi->slave->mode_flags = dsi->mode_flags; 1133 dsi->slave->channel = dsi->channel; 1134 conn_state->output_type = ROCKCHIP_OUTPUT_DSI_DUAL_CHANNEL; 1135 } 1136 1137 return 0; 1138 } 1139 1140 static void dw_mipi_dsi_set_hs_clk(struct dw_mipi_dsi *dsi, unsigned long rate) 1141 { 1142 rate = rockchip_phy_set_pll(dsi->dphy.phy, rate); 1143 dsi->lane_mbps = rate / 1000 / 1000; 1144 } 1145 1146 static void dw_mipi_dsi_host_init(struct dw_mipi_dsi *dsi) 1147 { 1148 dw_mipi_dsi_init(dsi); 1149 dw_mipi_dsi_dpi_config(dsi, &dsi->mode); 1150 dw_mipi_dsi_packet_handler_config(dsi); 1151 dw_mipi_dsi_video_mode_config(dsi); 1152 dw_mipi_dsi_video_packet_config(dsi, &dsi->mode); 1153 dw_mipi_dsi_command_mode_config(dsi); 1154 dsi_update_bits(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE, COMMAND_MODE); 1155 dw_mipi_dsi_line_timer_config(dsi); 1156 dw_mipi_dsi_vertical_timing_config(dsi); 1157 dw_mipi_dsi_dphy_timing_config(dsi); 1158 dw_mipi_dsi_dphy_interface_config(dsi); 1159 dw_mipi_dsi_clear_err(dsi); 1160 } 1161 1162 static void dw_mipi_dsi_vop_routing(struct dw_mipi_dsi *dsi, int vop_id) 1163 { 1164 grf_field_write(dsi, VOPSEL, vop_id); 1165 1166 if (dsi->slave) 1167 grf_field_write(dsi->slave, VOPSEL, vop_id); 1168 } 1169 1170 static void mipi_dphy_init(struct dw_mipi_dsi *dsi) 1171 { 1172 u32 map[] = {0x0, 0x1, 0x3, 0x7, 0xf}; 1173 1174 mipi_dphy_enableclk_deassert(dsi); 1175 mipi_dphy_shutdownz_assert(dsi); 1176 mipi_dphy_rstz_assert(dsi); 1177 testif_testclr_assert(dsi); 1178 1179 /* Configures DPHY to work as a Master */ 1180 grf_field_write(dsi, MASTERSLAVEZ, 1); 1181 1182 /* Configures lane as TX */ 1183 grf_field_write(dsi, BASEDIR, 0); 1184 1185 /* Set all REQUEST inputs to zero */ 1186 grf_field_write(dsi, TURNREQUEST, 0); 1187 grf_field_write(dsi, TURNDISABLE, 0); 1188 grf_field_write(dsi, FORCETXSTOPMODE, 0); 1189 grf_field_write(dsi, FORCERXMODE, 0); 1190 udelay(1); 1191 1192 testif_testclr_deassert(dsi); 1193 1194 if (!dsi->dphy.phy) 1195 dw_mipi_dsi_phy_init(dsi); 1196 1197 /* Enable Data Lane Module */ 1198 grf_field_write(dsi, ENABLE_N, map[dsi->lanes]); 1199 1200 /* Enable Clock Lane Module */ 1201 grf_field_write(dsi, ENABLECLK, 1); 1202 1203 mipi_dphy_enableclk_assert(dsi); 1204 } 1205 1206 static void dw_mipi_dsi_pre_enable(struct dw_mipi_dsi *dsi) 1207 { 1208 if (dsi->prepared) 1209 return; 1210 1211 if (dsi->master) 1212 dw_mipi_dsi_pre_enable(dsi->master); 1213 1214 dw_mipi_dsi_host_init(dsi); 1215 mipi_dphy_init(dsi); 1216 mipi_dphy_power_on(dsi); 1217 dsi_write(dsi, DSI_PWR_UP, POWERUP); 1218 1219 dsi->prepared = true; 1220 1221 if (dsi->slave) 1222 dw_mipi_dsi_pre_enable(dsi->slave); 1223 } 1224 1225 static int dw_mipi_dsi_connector_prepare(struct display_state *state) 1226 { 1227 struct connector_state *conn_state = &state->conn_state; 1228 struct crtc_state *crtc_state = &state->crtc_state; 1229 struct dw_mipi_dsi *dsi = dev_get_priv(conn_state->dev); 1230 unsigned long lane_rate; 1231 1232 memcpy(&dsi->mode, &conn_state->mode, sizeof(struct drm_display_mode)); 1233 if (dsi->slave) { 1234 dsi->mode.hdisplay /= 2; 1235 memcpy(&dsi->slave->mode, &dsi->mode, 1236 sizeof(struct drm_display_mode)); 1237 } 1238 1239 lane_rate = dw_mipi_dsi_get_lane_rate(dsi); 1240 if (dsi->dphy.phy) 1241 dw_mipi_dsi_set_hs_clk(dsi, lane_rate); 1242 else 1243 dw_mipi_dsi_set_pll(dsi, lane_rate); 1244 1245 printf("final DSI-Link bandwidth: %u Mbps x %d\n", 1246 dsi->lane_mbps, dsi->slave ? dsi->lanes * 2 : dsi->lanes); 1247 1248 dw_mipi_dsi_vop_routing(dsi, crtc_state->crtc_id); 1249 dw_mipi_dsi_pre_enable(dsi); 1250 1251 return 0; 1252 } 1253 1254 static void dw_mipi_dsi_connector_unprepare(struct display_state *state) 1255 { 1256 struct connector_state *conn_state = &state->conn_state; 1257 struct dw_mipi_dsi *dsi = dev_get_priv(conn_state->dev); 1258 1259 dw_mipi_dsi_post_disable(dsi); 1260 } 1261 1262 static int dw_mipi_dsi_connector_enable(struct display_state *state) 1263 { 1264 struct connector_state *conn_state = &state->conn_state; 1265 struct dw_mipi_dsi *dsi = dev_get_priv(conn_state->dev); 1266 1267 dw_mipi_dsi_enable(dsi); 1268 1269 return 0; 1270 } 1271 1272 static int dw_mipi_dsi_connector_disable(struct display_state *state) 1273 { 1274 struct connector_state *conn_state = &state->conn_state; 1275 struct dw_mipi_dsi *dsi = dev_get_priv(conn_state->dev); 1276 1277 dw_mipi_dsi_disable(dsi); 1278 1279 return 0; 1280 } 1281 1282 static const struct rockchip_connector_funcs dw_mipi_dsi_connector_funcs = { 1283 .init = dw_mipi_dsi_connector_init, 1284 .prepare = dw_mipi_dsi_connector_prepare, 1285 .unprepare = dw_mipi_dsi_connector_unprepare, 1286 .enable = dw_mipi_dsi_connector_enable, 1287 .disable = dw_mipi_dsi_connector_disable, 1288 }; 1289 1290 static int dw_mipi_dsi_probe(struct udevice *dev) 1291 { 1292 struct dw_mipi_dsi *dsi = dev_get_priv(dev); 1293 const struct rockchip_connector *connector = 1294 (const struct rockchip_connector *)dev_get_driver_data(dev); 1295 const struct dw_mipi_dsi_plat_data *pdata = connector->data; 1296 int id; 1297 1298 dsi->base = dev_read_addr_ptr(dev); 1299 dsi->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1300 if (IS_ERR(dsi->grf)) 1301 return PTR_ERR(dsi->grf); 1302 1303 id = of_alias_get_id(ofnode_to_np(dev->node), "dsi"); 1304 if (id < 0) 1305 id = 0; 1306 1307 dsi->dev = dev; 1308 dsi->pdata = pdata; 1309 dsi->id = id; 1310 1311 return 0; 1312 } 1313 1314 static const u32 px30_dsi_grf_reg_fields[MAX_FIELDS] = { 1315 [DPIUPDATECFG] = GRF_REG_FIELD(0x0434, 7, 7), 1316 [DPICOLORM] = GRF_REG_FIELD(0x0434, 3, 3), 1317 [DPISHUTDN] = GRF_REG_FIELD(0x0434, 2, 2), 1318 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0438, 7, 10), 1319 [TURNDISABLE] = GRF_REG_FIELD(0x0438, 5, 5), 1320 [VOPSEL] = GRF_REG_FIELD(0x0438, 0, 0), 1321 }; 1322 1323 static const struct dw_mipi_dsi_plat_data px30_mipi_dsi_plat_data = { 1324 .dsi0_grf_reg_fields = px30_dsi_grf_reg_fields, 1325 .max_bit_rate_per_lane = 1000000000UL, 1326 }; 1327 1328 static const struct rockchip_connector px30_mipi_dsi_driver_data = { 1329 .funcs = &dw_mipi_dsi_connector_funcs, 1330 .data = &px30_mipi_dsi_plat_data, 1331 }; 1332 1333 static const u32 rk1808_dsi_grf_reg_fields[MAX_FIELDS] = { 1334 [MASTERSLAVEZ] = GRF_REG_FIELD(0x0440, 8, 8), 1335 [DPIUPDATECFG] = GRF_REG_FIELD(0x0440, 7, 7), 1336 [DPICOLORM] = GRF_REG_FIELD(0x0440, 3, 3), 1337 [DPISHUTDN] = GRF_REG_FIELD(0x0440, 2, 2), 1338 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0444, 7, 10), 1339 [FORCERXMODE] = GRF_REG_FIELD(0x0444, 6, 6), 1340 [TURNDISABLE] = GRF_REG_FIELD(0x0444, 5, 5), 1341 }; 1342 1343 static const struct dw_mipi_dsi_plat_data rk1808_mipi_dsi_plat_data = { 1344 .dsi0_grf_reg_fields = rk1808_dsi_grf_reg_fields, 1345 .max_bit_rate_per_lane = 2000000000UL, 1346 }; 1347 1348 static const struct rockchip_connector rk1808_mipi_dsi_driver_data = { 1349 .funcs = &dw_mipi_dsi_connector_funcs, 1350 .data = &rk1808_mipi_dsi_plat_data, 1351 }; 1352 1353 static const u32 rk3128_dsi_grf_reg_fields[MAX_FIELDS] = { 1354 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0150, 10, 13), 1355 [FORCERXMODE] = GRF_REG_FIELD(0x0150, 9, 9), 1356 [TURNDISABLE] = GRF_REG_FIELD(0x0150, 8, 8), 1357 [DPICOLORM] = GRF_REG_FIELD(0x0150, 5, 5), 1358 [DPISHUTDN] = GRF_REG_FIELD(0x0150, 4, 4), 1359 }; 1360 1361 static const struct dw_mipi_dsi_plat_data rk3128_mipi_dsi_plat_data = { 1362 .dsi0_grf_reg_fields = rk3128_dsi_grf_reg_fields, 1363 .max_bit_rate_per_lane = 1000000000UL, 1364 }; 1365 1366 static const struct rockchip_connector rk3128_mipi_dsi_driver_data = { 1367 .funcs = &dw_mipi_dsi_connector_funcs, 1368 .data = &rk3128_mipi_dsi_plat_data, 1369 }; 1370 1371 static const u32 rk3288_dsi0_grf_reg_fields[MAX_FIELDS] = { 1372 [DPICOLORM] = GRF_REG_FIELD(0x025c, 8, 8), 1373 [DPISHUTDN] = GRF_REG_FIELD(0x025c, 7, 7), 1374 [VOPSEL] = GRF_REG_FIELD(0x025c, 6, 6), 1375 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0264, 8, 11), 1376 [FORCERXMODE] = GRF_REG_FIELD(0x0264, 4, 7), 1377 [TURNDISABLE] = GRF_REG_FIELD(0x0264, 0, 3), 1378 [TURNREQUEST] = GRF_REG_FIELD(0x03a4, 8, 10), 1379 [DPIUPDATECFG] = GRF_REG_FIELD(0x03a8, 0, 0), 1380 }; 1381 1382 static const u32 rk3288_dsi1_grf_reg_fields[MAX_FIELDS] = { 1383 [DPICOLORM] = GRF_REG_FIELD(0x025c, 11, 11), 1384 [DPISHUTDN] = GRF_REG_FIELD(0x025c, 10, 10), 1385 [VOPSEL] = GRF_REG_FIELD(0x025c, 9, 9), 1386 [ENABLE_N] = GRF_REG_FIELD(0x0268, 12, 15), 1387 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0268, 8, 11), 1388 [FORCERXMODE] = GRF_REG_FIELD(0x0268, 4, 7), 1389 [TURNDISABLE] = GRF_REG_FIELD(0x0268, 0, 3), 1390 [BASEDIR] = GRF_REG_FIELD(0x027c, 15, 15), 1391 [MASTERSLAVEZ] = GRF_REG_FIELD(0x027c, 14, 14), 1392 [ENABLECLK] = GRF_REG_FIELD(0x027c, 12, 12), 1393 [TURNREQUEST] = GRF_REG_FIELD(0x03a4, 4, 7), 1394 [DPIUPDATECFG] = GRF_REG_FIELD(0x03a8, 1, 1), 1395 }; 1396 1397 static const struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_plat_data = { 1398 .dsi0_grf_reg_fields = rk3288_dsi0_grf_reg_fields, 1399 .dsi1_grf_reg_fields = rk3288_dsi1_grf_reg_fields, 1400 .max_bit_rate_per_lane = 1500000000UL, 1401 }; 1402 1403 static const struct rockchip_connector rk3288_mipi_dsi_driver_data = { 1404 .funcs = &dw_mipi_dsi_connector_funcs, 1405 .data = &rk3288_mipi_dsi_plat_data, 1406 }; 1407 1408 static const u32 rk3366_dsi_grf_reg_fields[MAX_FIELDS] = { 1409 [VOPSEL] = GRF_REG_FIELD(0x0400, 2, 2), 1410 [DPIUPDATECFG] = GRF_REG_FIELD(0x0410, 9, 9), 1411 [DPICOLORM] = GRF_REG_FIELD(0x0410, 3, 3), 1412 [DPISHUTDN] = GRF_REG_FIELD(0x0410, 2, 2), 1413 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0414, 7, 10), 1414 [FORCERXMODE] = GRF_REG_FIELD(0x0414, 6, 6), 1415 [TURNDISABLE] = GRF_REG_FIELD(0x0414, 5, 5), 1416 }; 1417 1418 static const struct dw_mipi_dsi_plat_data rk3366_mipi_dsi_plat_data = { 1419 .dsi0_grf_reg_fields = rk3366_dsi_grf_reg_fields, 1420 .max_bit_rate_per_lane = 1000000000UL, 1421 }; 1422 1423 static const struct rockchip_connector rk3366_mipi_dsi_driver_data = { 1424 .funcs = &dw_mipi_dsi_connector_funcs, 1425 .data = &rk3366_mipi_dsi_plat_data, 1426 }; 1427 1428 static const u32 rk3368_dsi_grf_reg_fields[MAX_FIELDS] = { 1429 [DPIUPDATECFG] = GRF_REG_FIELD(0x0418, 7, 7), 1430 [DPICOLORM] = GRF_REG_FIELD(0x0418, 3, 3), 1431 [DPISHUTDN] = GRF_REG_FIELD(0x0418, 2, 2), 1432 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x041c, 7, 10), 1433 [FORCERXMODE] = GRF_REG_FIELD(0x041c, 6, 6), 1434 [TURNDISABLE] = GRF_REG_FIELD(0x041c, 5, 5), 1435 }; 1436 1437 static const struct dw_mipi_dsi_plat_data rk3368_mipi_dsi_plat_data = { 1438 .dsi0_grf_reg_fields = rk3368_dsi_grf_reg_fields, 1439 .max_bit_rate_per_lane = 1000000000UL, 1440 }; 1441 1442 static const struct rockchip_connector rk3368_mipi_dsi_driver_data = { 1443 .funcs = &dw_mipi_dsi_connector_funcs, 1444 .data = &rk3368_mipi_dsi_plat_data, 1445 }; 1446 1447 static const u32 rk3399_dsi0_grf_reg_fields[MAX_FIELDS] = { 1448 [DPIUPDATECFG] = GRF_REG_FIELD(0x6224, 15, 15), 1449 [DPISHUTDN] = GRF_REG_FIELD(0x6224, 14, 14), 1450 [DPICOLORM] = GRF_REG_FIELD(0x6224, 13, 13), 1451 [VOPSEL] = GRF_REG_FIELD(0x6250, 0, 0), 1452 [TURNREQUEST] = GRF_REG_FIELD(0x6258, 12, 15), 1453 [TURNDISABLE] = GRF_REG_FIELD(0x6258, 8, 11), 1454 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x6258, 4, 7), 1455 [FORCERXMODE] = GRF_REG_FIELD(0x6258, 0, 3), 1456 }; 1457 1458 static const u32 rk3399_dsi1_grf_reg_fields[MAX_FIELDS] = { 1459 [VOPSEL] = GRF_REG_FIELD(0x6250, 4, 4), 1460 [DPIUPDATECFG] = GRF_REG_FIELD(0x6250, 3, 3), 1461 [DPISHUTDN] = GRF_REG_FIELD(0x6250, 2, 2), 1462 [DPICOLORM] = GRF_REG_FIELD(0x6250, 1, 1), 1463 [TURNDISABLE] = GRF_REG_FIELD(0x625c, 12, 15), 1464 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x625c, 8, 11), 1465 [FORCERXMODE] = GRF_REG_FIELD(0x625c, 4, 7), 1466 [ENABLE_N] = GRF_REG_FIELD(0x625c, 0, 3), 1467 [MASTERSLAVEZ] = GRF_REG_FIELD(0x6260, 7, 7), 1468 [ENABLECLK] = GRF_REG_FIELD(0x6260, 6, 6), 1469 [BASEDIR] = GRF_REG_FIELD(0x6260, 5, 5), 1470 [TURNREQUEST] = GRF_REG_FIELD(0x6260, 0, 3), 1471 }; 1472 1473 static const struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_plat_data = { 1474 .dsi0_grf_reg_fields = rk3399_dsi0_grf_reg_fields, 1475 .dsi1_grf_reg_fields = rk3399_dsi1_grf_reg_fields, 1476 .max_bit_rate_per_lane = 1500000000UL, 1477 }; 1478 1479 static const struct rockchip_connector rk3399_mipi_dsi_driver_data = { 1480 .funcs = &dw_mipi_dsi_connector_funcs, 1481 .data = &rk3399_mipi_dsi_plat_data, 1482 }; 1483 1484 static const u32 rv1108_dsi_grf_reg_fields[MAX_FIELDS] = { 1485 [DPICOLORM] = GRF_REG_FIELD(0x0410, 7, 7), 1486 [DPISHUTDN] = GRF_REG_FIELD(0x0410, 6, 6), 1487 [DPIUPDATECFG] = GRF_REG_FIELD(0x0410, 8, 8), 1488 [FORCERXMODE] = GRF_REG_FIELD(0x0414, 5, 5), 1489 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0414, 6, 9), 1490 [TURNDISABLE] = GRF_REG_FIELD(0x0414, 4, 4), 1491 }; 1492 1493 static const struct dw_mipi_dsi_plat_data rv1108_mipi_dsi_plat_data = { 1494 .dsi0_grf_reg_fields = rv1108_dsi_grf_reg_fields, 1495 .max_bit_rate_per_lane = 1000000000UL, 1496 }; 1497 1498 static const struct rockchip_connector rv1108_mipi_dsi_driver_data = { 1499 .funcs = &dw_mipi_dsi_connector_funcs, 1500 .data = &rv1108_mipi_dsi_plat_data, 1501 }; 1502 1503 static const u32 rv1126_dsi_grf_reg_fields[MAX_FIELDS] = { 1504 [DPIUPDATECFG] = GRF_REG_FIELD(0x0008, 5, 5), 1505 [DPISHUTDN] = GRF_REG_FIELD(0x0008, 4, 4), 1506 [DPICOLORM] = GRF_REG_FIELD(0x0008, 3, 3), 1507 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x10220, 4, 7), 1508 [TURNDISABLE] = GRF_REG_FIELD(0x10220, 2, 2), 1509 [FORCERXMODE] = GRF_REG_FIELD(0x10220, 0, 0), 1510 }; 1511 1512 static const struct dw_mipi_dsi_plat_data rv1126_mipi_dsi_plat_data = { 1513 .dsi0_grf_reg_fields = rv1126_dsi_grf_reg_fields, 1514 .max_bit_rate_per_lane = 1000000000UL, 1515 }; 1516 1517 static const struct rockchip_connector rv1126_mipi_dsi_driver_data = { 1518 .funcs = &dw_mipi_dsi_connector_funcs, 1519 .data = &rv1126_mipi_dsi_plat_data, 1520 }; 1521 1522 static const struct udevice_id dw_mipi_dsi_ids[] = { 1523 { 1524 .compatible = "rockchip,px30-mipi-dsi", 1525 .data = (ulong)&px30_mipi_dsi_driver_data, 1526 }, 1527 { 1528 .compatible = "rockchip,rk1808-mipi-dsi", 1529 .data = (ulong)&rk1808_mipi_dsi_driver_data, 1530 }, 1531 { 1532 .compatible = "rockchip,rk3128-mipi-dsi", 1533 .data = (ulong)&rk3128_mipi_dsi_driver_data, 1534 }, 1535 { 1536 .compatible = "rockchip,rk3288-mipi-dsi", 1537 .data = (ulong)&rk3288_mipi_dsi_driver_data, 1538 }, 1539 { 1540 .compatible = "rockchip,rk3366-mipi-dsi", 1541 .data = (ulong)&rk3366_mipi_dsi_driver_data, 1542 }, 1543 { 1544 .compatible = "rockchip,rk3368-mipi-dsi", 1545 .data = (ulong)&rk3368_mipi_dsi_driver_data, 1546 }, 1547 { 1548 .compatible = "rockchip,rk3399-mipi-dsi", 1549 .data = (ulong)&rk3399_mipi_dsi_driver_data, 1550 }, 1551 { 1552 .compatible = "rockchip,rv1108-mipi-dsi", 1553 .data = (ulong)&rv1108_mipi_dsi_driver_data, 1554 }, 1555 { 1556 .compatible = "rockchip,rv1126-mipi-dsi", 1557 .data = (ulong)&rv1126_mipi_dsi_driver_data, 1558 }, 1559 {} 1560 }; 1561 1562 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host, 1563 const struct mipi_dsi_msg *msg) 1564 { 1565 struct dw_mipi_dsi *dsi = dev_get_priv(host->dev); 1566 1567 return dw_mipi_dsi_transfer(dsi, msg); 1568 } 1569 1570 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host, 1571 struct mipi_dsi_device *device) 1572 { 1573 struct dw_mipi_dsi *dsi = dev_get_priv(host->dev); 1574 1575 if (device->lanes < 1 || device->lanes > 8) 1576 return -EINVAL; 1577 1578 dsi->lanes = device->lanes; 1579 dsi->channel = device->channel; 1580 dsi->format = device->format; 1581 dsi->mode_flags = device->mode_flags; 1582 1583 return 0; 1584 } 1585 1586 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = { 1587 .attach = dw_mipi_dsi_host_attach, 1588 .transfer = dw_mipi_dsi_host_transfer, 1589 }; 1590 1591 static int dw_mipi_dsi_bind(struct udevice *dev) 1592 { 1593 struct mipi_dsi_host *host = dev_get_platdata(dev); 1594 1595 host->dev = dev; 1596 host->ops = &dw_mipi_dsi_host_ops; 1597 1598 return dm_scan_fdt_dev(dev); 1599 } 1600 1601 static int dw_mipi_dsi_child_post_bind(struct udevice *dev) 1602 { 1603 struct mipi_dsi_host *host = dev_get_platdata(dev->parent); 1604 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1605 char name[20]; 1606 1607 sprintf(name, "%s.%d", host->dev->name, device->channel); 1608 device_set_name(dev, name); 1609 1610 device->dev = dev; 1611 device->host = host; 1612 device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4); 1613 device->format = dev_read_u32_default(dev, "dsi,format", 1614 MIPI_DSI_FMT_RGB888); 1615 device->mode_flags = dev_read_u32_default(dev, "dsi,flags", 1616 MIPI_DSI_MODE_VIDEO | 1617 MIPI_DSI_MODE_VIDEO_BURST | 1618 MIPI_DSI_MODE_VIDEO_HBP | 1619 MIPI_DSI_MODE_LPM | 1620 MIPI_DSI_MODE_EOT_PACKET); 1621 device->channel = dev_read_u32_default(dev, "reg", 0); 1622 1623 return 0; 1624 } 1625 1626 static int dw_mipi_dsi_child_pre_probe(struct udevice *dev) 1627 { 1628 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1629 int ret; 1630 1631 ret = mipi_dsi_attach(device); 1632 if (ret) { 1633 dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret); 1634 return ret; 1635 } 1636 1637 return 0; 1638 } 1639 1640 U_BOOT_DRIVER(dw_mipi_dsi) = { 1641 .name = "dw_mipi_dsi", 1642 .id = UCLASS_DISPLAY, 1643 .of_match = dw_mipi_dsi_ids, 1644 .probe = dw_mipi_dsi_probe, 1645 .bind = dw_mipi_dsi_bind, 1646 .priv_auto_alloc_size = sizeof(struct dw_mipi_dsi), 1647 .per_child_platdata_auto_alloc_size = sizeof(struct mipi_dsi_device), 1648 .platdata_auto_alloc_size = sizeof(struct mipi_dsi_host), 1649 .child_post_bind = dw_mipi_dsi_child_post_bind, 1650 .child_pre_probe = dw_mipi_dsi_child_pre_probe, 1651 }; 1652