xref: /rk3399_rockchip-uboot/drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-loader_params.inc (revision 2a3fb7bb049d69d96f3bc7dae8caa756fdc8a613) 
10x12345678,
22,/* version */
3(0 << 0) | (1 << 8) | (8 << 16) | (8 << 24),/* cpu_gen,global index */
4(0 << 0) | (9 << 8) | (16 << 16) | (9 << 24),/* d2,d3 index */
5(25 << 0) | (9 << 8) | (0 << 16) | (0 << 24),/* d4,d5 index */
6(0 << 0) | (9 << 8) | (34 << 16) | (9 << 24),/* lp2,lp3 index */
7(43 << 0) | (13 << 8) | (0 << 16) | (0 << 24),/* lp4,lp5 index */
8(0 << 0) | (0 << 8) | (56 << 16) | (8 << 24),/* skew index, dq_map index */
9/* global info */
100,
11(93 << 16) | 13,/* sr_idle << 16 | pd_idle */
120,/* channel info */
131,/* 2t info */
140, 0, 0, 0,/* reserved */
15
16/* ddr3 */
17(924 << DDR_FREQ_F0_SHIFT) | (328 << DDR_FREQ_F1_SHIFT),
18(528 << DDR_FREQ_F2_SHIFT) | (784 << DDR_FREQ_F3_SHIFT),
19(0 << DDR_FREQ_F4_SHIFT) | (0 << DDR_FREQ_F5_SHIFT),
20/* drv when odt on */
21(30 << PHY_DQ_DRV_SHIFT) | (41 << PHY_CA_DRV_SHIFT) |
22	(38 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT),
23/* drv when odt off */
24(30 << PHY_DQ_DRV_SHIFT) | (30 << PHY_CA_DRV_SHIFT) |
25	(38 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT),
26/* odt info */
27(120 << DRAM_ODT_SHIFT) | (141 << PHY_ODT_SHIFT) |
28	(1 << PHY_ODT_PUUP_EN_SHIFT) |
29	(0 << PHY_ODT_PUDN_EN_SHIFT),
30/* odt enable freq */
31(333 << DRAM_ODT_EN_FREQ_SHIFT) | (333 << PHY_ODT_EN_FREQ_SHIFT),
32/* slew rate when odt enable */
33(0x1f << PHY_DQ_SR_SHIFT) | (0x1f << PHY_CA_SR_SHIFT) |
34	(0x1f << PHY_CLK_SR_SHIFT),
35/* slew  ratee when odt disable */
36(0x1f << PHY_DQ_SR_SHIFT) | (0x1f << PHY_CA_SR_SHIFT) |
37	(0x1f << PHY_CLK_SR_SHIFT),
38
39/* ddr4 */
40(924 << DDR_FREQ_F0_SHIFT) | (328 << DDR_FREQ_F1_SHIFT),
41(528 << DDR_FREQ_F2_SHIFT) | (784 << DDR_FREQ_F3_SHIFT),
42(0 << DDR_FREQ_F4_SHIFT) | (0 << DDR_FREQ_F5_SHIFT),
43/* drv when odt on */
44(37 << PHY_DQ_DRV_SHIFT) | (44 << PHY_CA_DRV_SHIFT) |
45	(37 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT),
46/* drv when odt off */
47(37 << PHY_DQ_DRV_SHIFT) | (44 << PHY_CA_DRV_SHIFT) |
48	(37 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT),
49/* odt info */
50(120 << DRAM_ODT_SHIFT) | (148 << PHY_ODT_SHIFT) |
51	(1 << PHY_ODT_PUUP_EN_SHIFT) | (1 << PHY_ODT_PUDN_EN_SHIFT),
52/* odt enable freq */
53(625 << DRAM_ODT_EN_FREQ_SHIFT) | (625 << PHY_ODT_EN_FREQ_SHIFT),
54/* slew rate when odt enable */
55(0xe << PHY_DQ_SR_SHIFT) | (0x3 << PHY_CA_SR_SHIFT) |
56	(0x3 << PHY_CLK_SR_SHIFT),
57/* slew  ratee when odt disable */
58(0xe << PHY_DQ_SR_SHIFT) | (0x3 << PHY_CA_SR_SHIFT) |
59	(0x3 << PHY_CLK_SR_SHIFT),
60
61/* lpddr3 */
62(924 << DDR_FREQ_F0_SHIFT) | (328 << DDR_FREQ_F1_SHIFT),
63(528 << DDR_FREQ_F2_SHIFT) | (784 << DDR_FREQ_F3_SHIFT),
64(0 << DDR_FREQ_F4_SHIFT) | (0 << DDR_FREQ_F5_SHIFT),
65/* drv when odt on */
66(28 << PHY_DQ_DRV_SHIFT) | (37 << PHY_CA_DRV_SHIFT) |
67	(34 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT),
68/* drv when odt off */
69(28 << PHY_DQ_DRV_SHIFT) | (37 << PHY_CA_DRV_SHIFT) |
70	(34 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT),
71/* odt info */
72(120 << DRAM_ODT_SHIFT) | (148 << PHY_ODT_SHIFT) |
73	(1 << PHY_ODT_PUUP_EN_SHIFT) | (1 << PHY_ODT_PUDN_EN_SHIFT),
74/* odt enable freq */
75(333 << DRAM_ODT_EN_FREQ_SHIFT) | (333 << PHY_ODT_EN_FREQ_SHIFT),
76
77/* slew rate when odt enable */
78(0xe << PHY_DQ_SR_SHIFT) | (0x0 << PHY_CA_SR_SHIFT) |
79	(0x0 << PHY_CLK_SR_SHIFT),
80/* slew  ratee when odt disable */
81(0xe << PHY_DQ_SR_SHIFT) | (0x0 << PHY_CA_SR_SHIFT) |
82	(0x0 << PHY_CLK_SR_SHIFT),
83
84/* lpddr4 */
85(924 << DDR_FREQ_F0_SHIFT) | (328 << DDR_FREQ_F1_SHIFT),
86(528 << DDR_FREQ_F2_SHIFT) | (784 << DDR_FREQ_F3_SHIFT),
87(0 << DDR_FREQ_F4_SHIFT) | (0 << DDR_FREQ_F5_SHIFT),
88
89/* drv when odt on */
90(38 << PHY_DQ_DRV_SHIFT) | (46 << PHY_CA_DRV_SHIFT) |
91	(38 << PHY_CLK_DRV_SHIFT) | (40 << DRAM_DQ_DRV_SHIFT),
92/* drv when odt off */
93(38 << PHY_DQ_DRV_SHIFT) | (46 << PHY_CA_DRV_SHIFT) |
94	(38 << PHY_CLK_DRV_SHIFT) | (40 << DRAM_DQ_DRV_SHIFT),
95/* odt info and PU-cal info */
96(240 << DRAM_ODT_SHIFT) | (60 << PHY_ODT_SHIFT) |
97	(0 << LP4_CA_ODT_SHIFT) |
98	(LPDDR4_VDDQ_2_5 << LP4_DRV_PU_CAL_ODTEN_SHIFT) |
99	(LPDDR4_VDDQ_2_5 << LP4_DRV_PU_CAL_ODTOFF_SHIFT) |
100	(0 << PHY_LP4_DRV_PULLDOWN_EN_ODTEN_SHIFT) |
101	(0 << PHY_LP4_DRV_PULLDOWN_EN_ODTOFF_SHIFT),
102/* odt enable freq */
103(333 << PHY_LP4_ODT_EN_FREQ_SHIFT) | (333 << LP4_DQ_ODT_EN_FREQ_SHIFT),
104/* slew rate when odt enable */
105(0xf << PHY_DQ_SR_SHIFT) | (0xf << PHY_CA_SR_SHIFT) |
106	(0xf << PHY_CLK_SR_SHIFT),
107/* slew  ratee when odt disable */
108(0xf << PHY_DQ_SR_SHIFT) | (0xf << PHY_CA_SR_SHIFT) |
109	(0xf << PHY_CLK_SR_SHIFT),
110/* ca odt en freq */
111(333 << LP4_CA_ODT_EN_FREQ_SHIFT),
112/* cs drv info and ca odt info */
113(0 << PHY_LP4_CS_DRV_ODTEN_SHIFT) |
114	(0 << PHY_LP4_CS_DRV_ODTOFF_SHIFT) |
115	(0 << LP4_ODTE_CK_SHIFT) | (0 << LP4_ODTE_CS_EN_SHIFT) |
116	(0 << LP4_ODTD_CA_EN_SHIFT),
117/* vref info when odt enable */
118(200 << PHY_LP4_DQ_VREF_SHIFT) | (420 << LP4_DQ_VREF_SHIFT) |
119	(420 << LP4_CA_VREF_SHIFT),
120/* vref info when odt disable */
121(420 << PHY_LP4_DQ_VREF_SHIFT) | (420 << LP4_DQ_VREF_SHIFT) |
122	(420 << LP4_CA_VREF_SHIFT),
123/* ddr4 map << 0 | ddr3 map << 24 */
124((0x2 << 6) | (0x1 << 4) | (0x3 << 2) | (0x0 << 0)) |
125	(0 << 8) | (0 << 16) |
126	(((0x2 << 6) | (0x1 << 4) | (0x3 << 2) | (0x0 << 0)) << 24),
127/* lp3 map << 16 | lp4 map << 24 */
128/* lp4 should equal to 0xc9 */
129(((0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0)) << 16) |
130	(((0x3 << 6) | (0x0 << 4) | (0x2 << 2) | (0x1 << 0)) << 24),
131/* lp3 dq0-7 map */
132(2 << 0) | (6 << 4) | (4 << 8) | (0 << 12) | (3 << 16) | (7 << 20) |
133	( 5 << 24) | (1 << 28),
134/* lp2 dq0-7 map */
1350,
136/* ddr4 dq map */
137/* cs0 dq0-15 */
138	((2 << 0 | 0 << 2 | 3 << 4 | 1 << 6) << 0) |
139	((0 << 0 | 2 << 2 | 3 << 4 | 1 << 6) << 8) |
140	((2 << 0 | 2 << 2 | 1 << 4 | 3 << 6) << 16) |
141	((1 << 0 | 3 << 2 | 0 << 4 | 0 << 6) << 24),
142/* cs0 dq16-31 */
143	((2 << 0 | 0 << 2 | 2 << 4 | 0 << 6) << 0) |
144	((1 << 0 | 3 << 2 | 3 << 4 | 1 << 6) << 8) |
145	((0 << 0 | 0 << 2 | 1 << 4 | 3 << 6) << 16) |
146	((1 << 0 | 3 << 2 | 2 << 4 | 2 << 6) << 24),
147/* cs1 dq0-15 */
148	((2 << 0 | 0 << 2 | 3 << 4 | 1 << 6) << 0) |
149	((0 << 0 | 2 << 2 | 3 << 4 | 1 << 6) << 8) |
150	((2 << 0 | 2 << 2 | 1 << 4 | 3 << 6) << 16) |
151	((1 << 0 | 3 << 2 | 0 << 4 | 0 << 6) << 24),
152/* cs1 dq16-31 */
153	((2 << 0 | 0 << 2 | 2 << 4 | 0 << 6) << 0) |
154	((1 << 0 | 3 << 2 | 3 << 4 | 1 << 6) << 8) |
155	((0 << 0 | 0 << 2 | 1 << 4 | 3 << 6) << 16) |
156	((1 << 0 | 3 << 2 | 2 << 4 | 2 << 6) << 24)
157