1 /* 2 * Copyright (C) 2017 NXP Semiconductors 3 * Copyright (C) 2017 Bin Meng <bmeng.cn@gmail.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __DRIVER_NVME_H__ 9 #define __DRIVER_NVME_H__ 10 11 #include <asm/io.h> 12 13 struct nvme_id_power_state { 14 __le16 max_power; /* centiwatts */ 15 __u8 rsvd2; 16 __u8 flags; 17 __le32 entry_lat; /* microseconds */ 18 __le32 exit_lat; /* microseconds */ 19 __u8 read_tput; 20 __u8 read_lat; 21 __u8 write_tput; 22 __u8 write_lat; 23 __le16 idle_power; 24 __u8 idle_scale; 25 __u8 rsvd19; 26 __le16 active_power; 27 __u8 active_work_scale; 28 __u8 rsvd23[9]; 29 }; 30 31 enum { 32 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0, 33 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1, 34 }; 35 36 struct nvme_id_ctrl { 37 __le16 vid; 38 __le16 ssvid; 39 char sn[20]; 40 char mn[40]; 41 char fr[8]; 42 __u8 rab; 43 __u8 ieee[3]; 44 __u8 mic; 45 __u8 mdts; 46 __u16 cntlid; 47 __u32 ver; 48 __u8 rsvd84[172]; 49 __le16 oacs; 50 __u8 acl; 51 __u8 aerl; 52 __u8 frmw; 53 __u8 lpa; 54 __u8 elpe; 55 __u8 npss; 56 __u8 avscc; 57 __u8 apsta; 58 __le16 wctemp; 59 __le16 cctemp; 60 __u8 rsvd270[242]; 61 __u8 sqes; 62 __u8 cqes; 63 __u8 rsvd514[2]; 64 __le32 nn; 65 __le16 oncs; 66 __le16 fuses; 67 __u8 fna; 68 __u8 vwc; 69 __le16 awun; 70 __le16 awupf; 71 __u8 nvscc; 72 __u8 rsvd531; 73 __le16 acwu; 74 __u8 rsvd534[2]; 75 __le32 sgls; 76 __u8 rsvd540[1508]; 77 struct nvme_id_power_state psd[32]; 78 __u8 vs[1024]; 79 }; 80 81 enum { 82 NVME_CTRL_ONCS_COMPARE = 1 << 0, 83 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1, 84 NVME_CTRL_ONCS_DSM = 1 << 2, 85 NVME_CTRL_VWC_PRESENT = 1 << 0, 86 }; 87 88 struct nvme_lbaf { 89 __le16 ms; 90 __u8 ds; 91 __u8 rp; 92 }; 93 94 struct nvme_id_ns { 95 __le64 nsze; 96 __le64 ncap; 97 __le64 nuse; 98 __u8 nsfeat; 99 __u8 nlbaf; 100 __u8 flbas; 101 __u8 mc; 102 __u8 dpc; 103 __u8 dps; 104 __u8 nmic; 105 __u8 rescap; 106 __u8 fpi; 107 __u8 rsvd33; 108 __le16 nawun; 109 __le16 nawupf; 110 __le16 nacwu; 111 __le16 nabsn; 112 __le16 nabo; 113 __le16 nabspf; 114 __u16 rsvd46; 115 __le64 nvmcap[2]; 116 __u8 rsvd64[40]; 117 __u8 nguid[16]; 118 __u8 eui64[8]; 119 struct nvme_lbaf lbaf[16]; 120 __u8 rsvd192[192]; 121 __u8 vs[3712]; 122 }; 123 124 enum { 125 NVME_NS_FEAT_THIN = 1 << 0, 126 NVME_NS_FLBAS_LBA_MASK = 0xf, 127 NVME_NS_FLBAS_META_EXT = 0x10, 128 NVME_LBAF_RP_BEST = 0, 129 NVME_LBAF_RP_BETTER = 1, 130 NVME_LBAF_RP_GOOD = 2, 131 NVME_LBAF_RP_DEGRADED = 3, 132 NVME_NS_DPC_PI_LAST = 1 << 4, 133 NVME_NS_DPC_PI_FIRST = 1 << 3, 134 NVME_NS_DPC_PI_TYPE3 = 1 << 2, 135 NVME_NS_DPC_PI_TYPE2 = 1 << 1, 136 NVME_NS_DPC_PI_TYPE1 = 1 << 0, 137 NVME_NS_DPS_PI_FIRST = 1 << 3, 138 NVME_NS_DPS_PI_MASK = 0x7, 139 NVME_NS_DPS_PI_TYPE1 = 1, 140 NVME_NS_DPS_PI_TYPE2 = 2, 141 NVME_NS_DPS_PI_TYPE3 = 3, 142 }; 143 144 struct nvme_smart_log { 145 __u8 critical_warning; 146 __u8 temperature[2]; 147 __u8 avail_spare; 148 __u8 spare_thresh; 149 __u8 percent_used; 150 __u8 rsvd6[26]; 151 __u8 data_units_read[16]; 152 __u8 data_units_written[16]; 153 __u8 host_reads[16]; 154 __u8 host_writes[16]; 155 __u8 ctrl_busy_time[16]; 156 __u8 power_cycles[16]; 157 __u8 power_on_hours[16]; 158 __u8 unsafe_shutdowns[16]; 159 __u8 media_errors[16]; 160 __u8 num_err_log_entries[16]; 161 __le32 warning_temp_time; 162 __le32 critical_comp_time; 163 __le16 temp_sensor[8]; 164 __u8 rsvd216[296]; 165 }; 166 167 enum { 168 NVME_SMART_CRIT_SPARE = 1 << 0, 169 NVME_SMART_CRIT_TEMPERATURE = 1 << 1, 170 NVME_SMART_CRIT_RELIABILITY = 1 << 2, 171 NVME_SMART_CRIT_MEDIA = 1 << 3, 172 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4, 173 }; 174 175 struct nvme_lba_range_type { 176 __u8 type; 177 __u8 attributes; 178 __u8 rsvd2[14]; 179 __u64 slba; 180 __u64 nlb; 181 __u8 guid[16]; 182 __u8 rsvd48[16]; 183 }; 184 185 enum { 186 NVME_LBART_TYPE_FS = 0x01, 187 NVME_LBART_TYPE_RAID = 0x02, 188 NVME_LBART_TYPE_CACHE = 0x03, 189 NVME_LBART_TYPE_SWAP = 0x04, 190 191 NVME_LBART_ATTRIB_TEMP = 1 << 0, 192 NVME_LBART_ATTRIB_HIDE = 1 << 1, 193 }; 194 195 struct nvme_reservation_status { 196 __le32 gen; 197 __u8 rtype; 198 __u8 regctl[2]; 199 __u8 resv5[2]; 200 __u8 ptpls; 201 __u8 resv10[13]; 202 struct { 203 __le16 cntlid; 204 __u8 rcsts; 205 __u8 resv3[5]; 206 __le64 hostid; 207 __le64 rkey; 208 } regctl_ds[]; 209 }; 210 211 /* I/O commands */ 212 213 enum nvme_opcode { 214 nvme_cmd_flush = 0x00, 215 nvme_cmd_write = 0x01, 216 nvme_cmd_read = 0x02, 217 nvme_cmd_write_uncor = 0x04, 218 nvme_cmd_compare = 0x05, 219 nvme_cmd_write_zeroes = 0x08, 220 nvme_cmd_dsm = 0x09, 221 nvme_cmd_resv_register = 0x0d, 222 nvme_cmd_resv_report = 0x0e, 223 nvme_cmd_resv_acquire = 0x11, 224 nvme_cmd_resv_release = 0x15, 225 }; 226 227 struct nvme_common_command { 228 __u8 opcode; 229 __u8 flags; 230 __u16 command_id; 231 __le32 nsid; 232 __le32 cdw2[2]; 233 __le64 metadata; 234 __le64 prp1; 235 __le64 prp2; 236 __le32 cdw10[6]; 237 }; 238 239 struct nvme_rw_command { 240 __u8 opcode; 241 __u8 flags; 242 __u16 command_id; 243 __le32 nsid; 244 __u64 rsvd2; 245 __le64 metadata; 246 __le64 prp1; 247 __le64 prp2; 248 __le64 slba; 249 __le16 length; 250 __le16 control; 251 __le32 dsmgmt; 252 __le32 reftag; 253 __le16 apptag; 254 __le16 appmask; 255 }; 256 257 enum { 258 NVME_RW_LR = 1 << 15, 259 NVME_RW_FUA = 1 << 14, 260 NVME_RW_DSM_FREQ_UNSPEC = 0, 261 NVME_RW_DSM_FREQ_TYPICAL = 1, 262 NVME_RW_DSM_FREQ_RARE = 2, 263 NVME_RW_DSM_FREQ_READS = 3, 264 NVME_RW_DSM_FREQ_WRITES = 4, 265 NVME_RW_DSM_FREQ_RW = 5, 266 NVME_RW_DSM_FREQ_ONCE = 6, 267 NVME_RW_DSM_FREQ_PREFETCH = 7, 268 NVME_RW_DSM_FREQ_TEMP = 8, 269 NVME_RW_DSM_LATENCY_NONE = 0 << 4, 270 NVME_RW_DSM_LATENCY_IDLE = 1 << 4, 271 NVME_RW_DSM_LATENCY_NORM = 2 << 4, 272 NVME_RW_DSM_LATENCY_LOW = 3 << 4, 273 NVME_RW_DSM_SEQ_REQ = 1 << 6, 274 NVME_RW_DSM_COMPRESSED = 1 << 7, 275 NVME_RW_PRINFO_PRCHK_REF = 1 << 10, 276 NVME_RW_PRINFO_PRCHK_APP = 1 << 11, 277 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, 278 NVME_RW_PRINFO_PRACT = 1 << 13, 279 }; 280 281 #define NVME_DSM_MAX_RANGES 256 282 283 struct nvme_dsm_cmd { 284 __u8 opcode; 285 __u8 flags; 286 __u16 command_id; 287 __le32 nsid; 288 __u64 rsvd2[2]; 289 __le64 prp1; 290 __le64 prp2; 291 __le32 nr; 292 __le32 attributes; 293 __u32 rsvd12[4]; 294 }; 295 296 enum { 297 NVME_DSMGMT_IDR = 1 << 0, 298 NVME_DSMGMT_IDW = 1 << 1, 299 NVME_DSMGMT_AD = 1 << 2, 300 }; 301 302 struct nvme_dsm_range { 303 __le32 cattr; 304 __le32 nlb; 305 __le64 slba; 306 }; 307 308 /* Admin commands */ 309 310 enum nvme_admin_opcode { 311 nvme_admin_delete_sq = 0x00, 312 nvme_admin_create_sq = 0x01, 313 nvme_admin_get_log_page = 0x02, 314 nvme_admin_delete_cq = 0x04, 315 nvme_admin_create_cq = 0x05, 316 nvme_admin_identify = 0x06, 317 nvme_admin_abort_cmd = 0x08, 318 nvme_admin_set_features = 0x09, 319 nvme_admin_get_features = 0x0a, 320 nvme_admin_async_event = 0x0c, 321 nvme_admin_activate_fw = 0x10, 322 nvme_admin_download_fw = 0x11, 323 nvme_admin_format_nvm = 0x80, 324 nvme_admin_security_send = 0x81, 325 nvme_admin_security_recv = 0x82, 326 }; 327 328 enum { 329 NVME_QUEUE_PHYS_CONTIG = (1 << 0), 330 NVME_CQ_IRQ_ENABLED = (1 << 1), 331 NVME_SQ_PRIO_URGENT = (0 << 1), 332 NVME_SQ_PRIO_HIGH = (1 << 1), 333 NVME_SQ_PRIO_MEDIUM = (2 << 1), 334 NVME_SQ_PRIO_LOW = (3 << 1), 335 NVME_FEAT_ARBITRATION = 0x01, 336 NVME_FEAT_POWER_MGMT = 0x02, 337 NVME_FEAT_LBA_RANGE = 0x03, 338 NVME_FEAT_TEMP_THRESH = 0x04, 339 NVME_FEAT_ERR_RECOVERY = 0x05, 340 NVME_FEAT_VOLATILE_WC = 0x06, 341 NVME_FEAT_NUM_QUEUES = 0x07, 342 NVME_FEAT_IRQ_COALESCE = 0x08, 343 NVME_FEAT_IRQ_CONFIG = 0x09, 344 NVME_FEAT_WRITE_ATOMIC = 0x0a, 345 NVME_FEAT_ASYNC_EVENT = 0x0b, 346 NVME_FEAT_AUTO_PST = 0x0c, 347 NVME_FEAT_SW_PROGRESS = 0x80, 348 NVME_FEAT_HOST_ID = 0x81, 349 NVME_FEAT_RESV_MASK = 0x82, 350 NVME_FEAT_RESV_PERSIST = 0x83, 351 NVME_LOG_ERROR = 0x01, 352 NVME_LOG_SMART = 0x02, 353 NVME_LOG_FW_SLOT = 0x03, 354 NVME_LOG_RESERVATION = 0x80, 355 NVME_FWACT_REPL = (0 << 3), 356 NVME_FWACT_REPL_ACTV = (1 << 3), 357 NVME_FWACT_ACTV = (2 << 3), 358 }; 359 360 struct nvme_identify { 361 __u8 opcode; 362 __u8 flags; 363 __u16 command_id; 364 __le32 nsid; 365 __u64 rsvd2[2]; 366 __le64 prp1; 367 __le64 prp2; 368 __le32 cns; 369 __u32 rsvd11[5]; 370 }; 371 372 struct nvme_features { 373 __u8 opcode; 374 __u8 flags; 375 __u16 command_id; 376 __le32 nsid; 377 __u64 rsvd2[2]; 378 __le64 prp1; 379 __le64 prp2; 380 __le32 fid; 381 __le32 dword11; 382 __u32 rsvd12[4]; 383 }; 384 385 struct nvme_create_cq { 386 __u8 opcode; 387 __u8 flags; 388 __u16 command_id; 389 __u32 rsvd1[5]; 390 __le64 prp1; 391 __u64 rsvd8; 392 __le16 cqid; 393 __le16 qsize; 394 __le16 cq_flags; 395 __le16 irq_vector; 396 __u32 rsvd12[4]; 397 }; 398 399 struct nvme_create_sq { 400 __u8 opcode; 401 __u8 flags; 402 __u16 command_id; 403 __u32 rsvd1[5]; 404 __le64 prp1; 405 __u64 rsvd8; 406 __le16 sqid; 407 __le16 qsize; 408 __le16 sq_flags; 409 __le16 cqid; 410 __u32 rsvd12[4]; 411 }; 412 413 struct nvme_delete_queue { 414 __u8 opcode; 415 __u8 flags; 416 __u16 command_id; 417 __u32 rsvd1[9]; 418 __le16 qid; 419 __u16 rsvd10; 420 __u32 rsvd11[5]; 421 }; 422 423 struct nvme_abort_cmd { 424 __u8 opcode; 425 __u8 flags; 426 __u16 command_id; 427 __u32 rsvd1[9]; 428 __le16 sqid; 429 __u16 cid; 430 __u32 rsvd11[5]; 431 }; 432 433 struct nvme_download_firmware { 434 __u8 opcode; 435 __u8 flags; 436 __u16 command_id; 437 __u32 rsvd1[5]; 438 __le64 prp1; 439 __le64 prp2; 440 __le32 numd; 441 __le32 offset; 442 __u32 rsvd12[4]; 443 }; 444 445 struct nvme_format_cmd { 446 __u8 opcode; 447 __u8 flags; 448 __u16 command_id; 449 __le32 nsid; 450 __u64 rsvd2[4]; 451 __le32 cdw10; 452 __u32 rsvd11[5]; 453 }; 454 455 struct nvme_command { 456 union { 457 struct nvme_common_command common; 458 struct nvme_rw_command rw; 459 struct nvme_identify identify; 460 struct nvme_features features; 461 struct nvme_create_cq create_cq; 462 struct nvme_create_sq create_sq; 463 struct nvme_delete_queue delete_queue; 464 struct nvme_download_firmware dlfw; 465 struct nvme_format_cmd format; 466 struct nvme_dsm_cmd dsm; 467 struct nvme_abort_cmd abort; 468 }; 469 }; 470 471 enum { 472 NVME_SC_SUCCESS = 0x0, 473 NVME_SC_INVALID_OPCODE = 0x1, 474 NVME_SC_INVALID_FIELD = 0x2, 475 NVME_SC_CMDID_CONFLICT = 0x3, 476 NVME_SC_DATA_XFER_ERROR = 0x4, 477 NVME_SC_POWER_LOSS = 0x5, 478 NVME_SC_INTERNAL = 0x6, 479 NVME_SC_ABORT_REQ = 0x7, 480 NVME_SC_ABORT_QUEUE = 0x8, 481 NVME_SC_FUSED_FAIL = 0x9, 482 NVME_SC_FUSED_MISSING = 0xa, 483 NVME_SC_INVALID_NS = 0xb, 484 NVME_SC_CMD_SEQ_ERROR = 0xc, 485 NVME_SC_SGL_INVALID_LAST = 0xd, 486 NVME_SC_SGL_INVALID_COUNT = 0xe, 487 NVME_SC_SGL_INVALID_DATA = 0xf, 488 NVME_SC_SGL_INVALID_METADATA = 0x10, 489 NVME_SC_SGL_INVALID_TYPE = 0x11, 490 NVME_SC_LBA_RANGE = 0x80, 491 NVME_SC_CAP_EXCEEDED = 0x81, 492 NVME_SC_NS_NOT_READY = 0x82, 493 NVME_SC_RESERVATION_CONFLICT = 0x83, 494 NVME_SC_CQ_INVALID = 0x100, 495 NVME_SC_QID_INVALID = 0x101, 496 NVME_SC_QUEUE_SIZE = 0x102, 497 NVME_SC_ABORT_LIMIT = 0x103, 498 NVME_SC_ABORT_MISSING = 0x104, 499 NVME_SC_ASYNC_LIMIT = 0x105, 500 NVME_SC_FIRMWARE_SLOT = 0x106, 501 NVME_SC_FIRMWARE_IMAGE = 0x107, 502 NVME_SC_INVALID_VECTOR = 0x108, 503 NVME_SC_INVALID_LOG_PAGE = 0x109, 504 NVME_SC_INVALID_FORMAT = 0x10a, 505 NVME_SC_FIRMWARE_NEEDS_RESET = 0x10b, 506 NVME_SC_INVALID_QUEUE = 0x10c, 507 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d, 508 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e, 509 NVME_SC_FEATURE_NOT_PER_NS = 0x10f, 510 NVME_SC_FW_NEEDS_RESET_SUBSYS = 0x110, 511 NVME_SC_BAD_ATTRIBUTES = 0x180, 512 NVME_SC_INVALID_PI = 0x181, 513 NVME_SC_READ_ONLY = 0x182, 514 NVME_SC_WRITE_FAULT = 0x280, 515 NVME_SC_READ_ERROR = 0x281, 516 NVME_SC_GUARD_CHECK = 0x282, 517 NVME_SC_APPTAG_CHECK = 0x283, 518 NVME_SC_REFTAG_CHECK = 0x284, 519 NVME_SC_COMPARE_FAILED = 0x285, 520 NVME_SC_ACCESS_DENIED = 0x286, 521 NVME_SC_DNR = 0x4000, 522 }; 523 524 struct nvme_completion { 525 __le32 result; /* Used by admin commands to return data */ 526 __u32 rsvd; 527 __le16 sq_head; /* how much of this queue may be reclaimed */ 528 __le16 sq_id; /* submission queue that generated this entry */ 529 __u16 command_id; /* of the command which completed */ 530 __le16 status; /* did the command fail, and if so, why? */ 531 }; 532 533 /* 534 * Registers should always be accessed with double word or quad word 535 * accesses. Registers with 64-bit address pointers should be written 536 * to with dword accesses by writing the low dword first (ptr[0]), 537 * then the high dword (ptr[1]) second. 538 */ 539 static inline u64 nvme_readq(__le64 volatile *regs) 540 { 541 #if BITS_PER_LONG == 64 542 return readq(regs); 543 #else 544 __u32 *ptr = (__u32 *)regs; 545 u64 val_lo = readl(ptr); 546 u64 val_hi = readl(ptr + 1); 547 548 return val_lo + (val_hi << 32); 549 #endif 550 } 551 552 static inline void nvme_writeq(const u64 val, __le64 volatile *regs) 553 { 554 #if BITS_PER_LONG == 64 555 writeq(val, regs); 556 #else 557 __u32 *ptr = (__u32 *)regs; 558 u32 val_lo = lower_32_bits(val); 559 u32 val_hi = upper_32_bits(val); 560 writel(val_lo, ptr); 561 writel(val_hi, ptr + 1); 562 #endif 563 } 564 565 struct nvme_bar { 566 __u64 cap; /* Controller Capabilities */ 567 __u32 vs; /* Version */ 568 __u32 intms; /* Interrupt Mask Set */ 569 __u32 intmc; /* Interrupt Mask Clear */ 570 __u32 cc; /* Controller Configuration */ 571 __u32 rsvd1; /* Reserved */ 572 __u32 csts; /* Controller Status */ 573 __u32 rsvd2; /* Reserved */ 574 __u32 aqa; /* Admin Queue Attributes */ 575 __u64 asq; /* Admin SQ Base Address */ 576 __u64 acq; /* Admin CQ Base Address */ 577 }; 578 579 #define NVME_CAP_MQES(cap) ((cap) & 0xffff) 580 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff) 581 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf) 582 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf) 583 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf) 584 585 #define NVME_VS(major, minor) (((major) << 16) | ((minor) << 8)) 586 587 enum { 588 NVME_CC_ENABLE = 1 << 0, 589 NVME_CC_CSS_NVM = 0 << 4, 590 NVME_CC_MPS_SHIFT = 7, 591 NVME_CC_ARB_RR = 0 << 11, 592 NVME_CC_ARB_WRRU = 1 << 11, 593 NVME_CC_ARB_VS = 7 << 11, 594 NVME_CC_SHN_NONE = 0 << 14, 595 NVME_CC_SHN_NORMAL = 1 << 14, 596 NVME_CC_SHN_ABRUPT = 2 << 14, 597 NVME_CC_SHN_MASK = 3 << 14, 598 NVME_CC_IOSQES = 6 << 16, 599 NVME_CC_IOCQES = 4 << 20, 600 NVME_CSTS_RDY = 1 << 0, 601 NVME_CSTS_CFS = 1 << 1, 602 NVME_CSTS_SHST_NORMAL = 0 << 2, 603 NVME_CSTS_SHST_OCCUR = 1 << 2, 604 NVME_CSTS_SHST_CMPLT = 2 << 2, 605 NVME_CSTS_SHST_MASK = 3 << 2, 606 }; 607 608 /* Represents an NVM Express device. Each nvme_dev is a PCI function. */ 609 struct nvme_dev { 610 struct list_head node; 611 struct nvme_queue **queues; 612 u32 __iomem *dbs; 613 int instance; 614 unsigned queue_count; 615 unsigned online_queues; 616 unsigned max_qid; 617 int q_depth; 618 u32 db_stride; 619 u32 ctrl_config; 620 struct nvme_bar __iomem *bar; 621 struct list_head namespaces; 622 char serial[20]; 623 char model[40]; 624 char firmware_rev[8]; 625 u32 max_transfer_shift; 626 u64 cap; 627 u32 stripe_size; 628 u32 page_size; 629 u8 vwc; 630 u64 *prp_pool; 631 u32 prp_entry_num; 632 u32 nn; 633 }; 634 635 /* 636 * An NVM Express namespace is equivalent to a SCSI LUN. 637 * Each namespace is operated as an independent "device". 638 */ 639 struct nvme_ns { 640 struct list_head list; 641 struct nvme_dev *dev; 642 unsigned ns_id; 643 u8 eui64[8]; 644 int devnum; 645 int lba_shift; 646 u8 flbas; 647 }; 648 649 #endif /* __DRIVER_NVME_H__ */ 650