1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * (C) Copyright 2018 Rockchip Electronics Co., Ltd. 4 */ 5 6 #include <common.h> 7 #include <ram.h> 8 #include <asm/io.h> 9 #include <asm/arch/sdram.h> 10 #include <asm/arch/sdram_pctl_px30.h> 11 12 /* 13 * rank = 1: cs0 14 * rank = 2: cs1 15 */ 16 void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num) 17 { 18 writel((rank << 4) | (1 << 0), pctl_base + DDR_PCTL2_MRCTRL0); 19 writel((mr_num << 8), pctl_base + DDR_PCTL2_MRCTRL1); 20 setbits_le32(pctl_base + DDR_PCTL2_MRCTRL0, 1u << 31); 21 while (readl(pctl_base + DDR_PCTL2_MRCTRL0) & (1u << 31)) 22 continue; 23 while (readl(pctl_base + DDR_PCTL2_MRSTAT) & PCTL2_MR_WR_BUSY) 24 continue; 25 } 26 27 /* rank = 1: cs0 28 * rank = 2: cs1 29 * rank = 3: cs0 & cs1 30 * note: be careful of keep mr original val 31 */ 32 int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg, 33 u32 dramtype) 34 { 35 while (readl(pctl_base + DDR_PCTL2_MRSTAT) & PCTL2_MR_WR_BUSY) 36 continue; 37 if (dramtype == DDR3 || dramtype == DDR4) { 38 writel((mr_num << 12) | (rank << 4) | (0 << 0), 39 pctl_base + DDR_PCTL2_MRCTRL0); 40 writel(arg, pctl_base + DDR_PCTL2_MRCTRL1); 41 } else { 42 writel((rank << 4) | (0 << 0), 43 pctl_base + DDR_PCTL2_MRCTRL0); 44 writel((mr_num << 8) | (arg & 0xff), 45 pctl_base + DDR_PCTL2_MRCTRL1); 46 } 47 48 setbits_le32(pctl_base + DDR_PCTL2_MRCTRL0, 1u << 31); 49 while (readl(pctl_base + DDR_PCTL2_MRCTRL0) & (1u << 31)) 50 continue; 51 while (readl(pctl_base + DDR_PCTL2_MRSTAT) & PCTL2_MR_WR_BUSY) 52 continue; 53 54 return 0; 55 } 56 57 /* 58 * rank : 1:cs0, 2:cs1, 3:cs0&cs1 59 * vrefrate: 4500: 45%, 60 */ 61 int pctl_write_vrefdq(void __iomem *pctl_base, u32 rank, u32 vrefrate, 62 u32 dramtype) 63 { 64 u32 tccd_l, value; 65 u32 dis_auto_zq = 0; 66 67 if (dramtype != DDR4 || vrefrate < 4500 || vrefrate > 9250) 68 return (-1); 69 70 tccd_l = (readl(pctl_base + DDR_PCTL2_DRAMTMG4) >> 16) & 0xf; 71 tccd_l = (tccd_l - 4) << 10; 72 73 if (vrefrate > 7500) { 74 /* range 1 */ 75 value = ((vrefrate - 6000) / 65) | tccd_l; 76 } else { 77 /* range 2 */ 78 value = ((vrefrate - 4500) / 65) | tccd_l | (1 << 6); 79 } 80 81 dis_auto_zq = pctl_dis_zqcs_aref(pctl_base); 82 83 /* enable vrefdq calibratin */ 84 pctl_write_mr(pctl_base, rank, 6, value | (1 << 7), dramtype); 85 udelay(1);/* tvrefdqe */ 86 /* write vrefdq value */ 87 pctl_write_mr(pctl_base, rank, 6, value | (1 << 7), dramtype); 88 udelay(1);/* tvref_time */ 89 pctl_write_mr(pctl_base, rank, 6, value | (0 << 7), dramtype); 90 udelay(1);/* tvrefdqx */ 91 92 pctl_rest_zqcs_aref(pctl_base, dis_auto_zq); 93 94 return 0; 95 } 96 97 static int upctl2_update_ref_reg(void __iomem *pctl_base) 98 { 99 u32 ret; 100 101 ret = readl(pctl_base + DDR_PCTL2_RFSHCTL3) ^ (1 << 1); 102 writel(ret, pctl_base + DDR_PCTL2_RFSHCTL3); 103 104 return 0; 105 } 106 107 u32 pctl_dis_zqcs_aref(void __iomem *pctl_base) 108 { 109 u32 dis_auto_zq = 0; 110 111 /* disable zqcs */ 112 if (!(readl(pctl_base + DDR_PCTL2_ZQCTL0) & 113 (1ul << 31))) { 114 dis_auto_zq = 1; 115 setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31); 116 } 117 118 /* disable auto refresh */ 119 setbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1); 120 121 upctl2_update_ref_reg(pctl_base); 122 123 return dis_auto_zq; 124 } 125 126 void pctl_rest_zqcs_aref(void __iomem *pctl_base, u32 dis_auto_zq) 127 { 128 /* restore zqcs */ 129 if (dis_auto_zq) 130 clrbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31); 131 132 /* restore auto refresh */ 133 clrbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1); 134 135 upctl2_update_ref_reg(pctl_base); 136 } 137 138 /* 139 * before call this function autorefresh should be disabled. 140 * rank : bit0:cs0, bit1:cs1, ... 141 */ 142 void send_a_refresh(void __iomem *pctl_base, u32 rank) 143 { 144 while (readl(pctl_base + DDR_PCTL2_DBGSTAT) & rank) 145 continue; 146 writel(rank, pctl_base + DDR_PCTL2_DBGCMD); 147 148 while (readl(pctl_base + DDR_PCTL2_DBGSTAT) & rank) 149 continue; 150 } 151 152 u32 pctl_remodify_sdram_params(struct ddr_pctl_regs *pctl_regs, 153 struct sdram_cap_info *cap_info, 154 u32 dram_type) 155 { 156 u32 tmp = 0, tmp_adr = 0, i; 157 158 for (i = 0; pctl_regs->pctl[i][0] != 0xFFFFFFFF; i++) { 159 if (pctl_regs->pctl[i][0] == 0) { 160 tmp = pctl_regs->pctl[i][1];/* MSTR */ 161 tmp_adr = i; 162 } 163 } 164 165 tmp &= ~((3ul << 30) | (3ul << 24) | (3ul << 12)); 166 167 switch (cap_info->dbw) { 168 case 2: 169 tmp |= (3ul << 30); 170 break; 171 case 1: 172 tmp |= (2ul << 30); 173 break; 174 case 0: 175 default: 176 tmp |= (1ul << 30); 177 break; 178 } 179 180 /* active_ranks always keep 2 rank for dfi monitor */ 181 tmp |= 3 << 24; 182 183 tmp |= (2 - cap_info->bw) << 12; 184 185 pctl_regs->pctl[tmp_adr][1] = tmp; 186 187 return 0; 188 } 189 190 int pctl_cfg(void __iomem *pctl_base, struct ddr_pctl_regs *pctl_regs, 191 u32 sr_idle, u32 pd_idle) 192 { 193 u32 i; 194 195 for (i = 0; pctl_regs->pctl[i][0] != 0xFFFFFFFF; i++) { 196 writel(pctl_regs->pctl[i][1], 197 pctl_base + pctl_regs->pctl[i][0]); 198 } 199 clrsetbits_le32(pctl_base + DDR_PCTL2_PWRTMG, 200 (0xff << 16) | 0x1f, 201 ((sr_idle & 0xff) << 16) | (pd_idle & 0x1f)); 202 203 clrsetbits_le32(pctl_base + DDR_PCTL2_HWLPCTL, 204 0xfff << 16, 205 5 << 16); 206 /* disable zqcs */ 207 setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1u << 31); 208 209 return 0; 210 } 211 212