1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _ASM_ARCH_CRU_RK3308_H 7 #define _ASM_ARCH_CRU_RK3308_H 8 9 #include <common.h> 10 11 #define MHz 1000000 12 #define OSC_HZ (24 * MHz) 13 14 #define APLL_HZ (816 * MHz) 15 16 #define CORE_ACLK_HZ 408000000 17 #define CORE_DBG_HZ 204000000 18 19 #define BUS_ACLK_HZ 200000000 20 #define BUS_HCLK_HZ 100000000 21 #define BUS_PCLK_HZ 100000000 22 23 #define PERI_ACLK_HZ 200000000 24 #define PERI_HCLK_HZ 100000000 25 #define PERI_PCLK_HZ 100000000 26 27 #define AUDIO_HCLK_HZ 100000000 28 #define AUDIO_PCLK_HZ 100000000 29 30 #define RK3308_PLL_CON(x) ((x) * 0x4) 31 #define RK3308_MODE_CON 0xa0 32 33 /* RK3308 pll id */ 34 enum rk3308_pll_id { 35 APLL, 36 DPLL, 37 VPLL0, 38 VPLL1, 39 PLL_COUNT, 40 }; 41 42 struct rk3308_clk_info { 43 unsigned long id; 44 char *name; 45 }; 46 47 /* Private data for the clock driver - used by rockchip_get_cru() */ 48 struct rk3308_clk_priv { 49 struct rk3308_cru *cru; 50 ulong armclk_hz; 51 ulong dpll_hz; 52 ulong vpll0_hz; 53 ulong vpll1_hz; 54 ulong armclk_enter_hz; 55 ulong armclk_init_hz; 56 bool sync_kernel; 57 bool set_armclk_rate; 58 }; 59 60 struct rk3308_cru { 61 struct rk3308_pll { 62 unsigned int con0; 63 unsigned int con1; 64 unsigned int con2; 65 unsigned int con3; 66 unsigned int con4; 67 unsigned int reserved0[3]; 68 } pll[4]; 69 unsigned int reserved1[8]; 70 unsigned int mode; 71 unsigned int misc; 72 unsigned int reserved2[2]; 73 unsigned int glb_cnt_th; 74 unsigned int glb_rst_st; 75 unsigned int glb_srst_fst; 76 unsigned int glb_srst_snd; 77 unsigned int glb_rst_con; 78 unsigned int pll_lock; 79 unsigned int reserved3[6]; 80 unsigned int hwffc_con0; 81 unsigned int reserved4; 82 unsigned int hwffc_th; 83 unsigned int hwffc_intst; 84 unsigned int apll_con0_s; 85 unsigned int apll_con1_s; 86 unsigned int clksel_con0_s; 87 unsigned int reserved5; 88 unsigned int clksel_con[74]; 89 unsigned int reserved6[54]; 90 unsigned int clkgate_con[15]; 91 unsigned int reserved7[(0x380 - 0x338) / 4 - 1]; 92 unsigned int ssgtbl[32]; 93 unsigned int softrst_con[10]; 94 unsigned int reserved8[(0x480 - 0x424) / 4 - 1]; 95 unsigned int sdmmc_con[2]; 96 unsigned int sdio_con[2]; 97 unsigned int emmc_con[2]; 98 }; 99 100 enum { 101 /* PLLCON0*/ 102 PLL_BP_SHIFT = 15, 103 PLL_POSTDIV1_SHIFT = 12, 104 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, 105 PLL_FBDIV_SHIFT = 0, 106 PLL_FBDIV_MASK = 0xfff, 107 108 /* PLLCON1 */ 109 PLL_PDSEL_SHIFT = 15, 110 PLL_PD1_SHIFT = 14, 111 PLL_PD_SHIFT = 13, 112 PLL_PD_MASK = 1 << PLL_PD_SHIFT, 113 PLL_DSMPD_SHIFT = 12, 114 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 115 PLL_LOCK_STATUS_SHIFT = 10, 116 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 117 PLL_POSTDIV2_SHIFT = 6, 118 PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, 119 PLL_REFDIV_SHIFT = 0, 120 PLL_REFDIV_MASK = 0x3f, 121 122 /* PLLCON2 */ 123 PLL_FOUT4PHASEPD_SHIFT = 27, 124 PLL_FOUTVCOPD_SHIFT = 26, 125 PLL_FOUTPOSTDIVPD_SHIFT = 25, 126 PLL_DACPD_SHIFT = 24, 127 PLL_FRAC_DIV = 0xffffff, 128 129 /* CRU_MODE */ 130 PLLMUX_FROM_XIN24M = 0, 131 PLLMUX_FROM_PLL, 132 PLLMUX_FROM_RTC32K, 133 USBPHY480M_MODE_SHIFT = 8, 134 USBPHY480M_MODE_MASK = 3 << USBPHY480M_MODE_SHIFT, 135 VPLL1_MODE_SHIFT = 6, 136 VPLL1_MODE_MASK = 3 << VPLL1_MODE_SHIFT, 137 VPLL0_MODE_SHIFT = 4, 138 VPLL0_MODE_MASK = 3 << VPLL0_MODE_SHIFT, 139 DPLL_MODE_SHIFT = 2, 140 DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT, 141 APLL_MODE_SHIFT = 0, 142 APLL_MODE_MASK = 3 << APLL_MODE_SHIFT, 143 144 /* CRU_CLK_SEL0_CON */ 145 CORE_ACLK_DIV_SHIFT = 12, 146 CORE_ACLK_DIV_MASK = 0x7 << CORE_ACLK_DIV_SHIFT, 147 CORE_DBG_DIV_SHIFT = 8, 148 CORE_DBG_DIV_MASK = 0xf << CORE_DBG_DIV_SHIFT, 149 CORE_CLK_PLL_SEL_SHIFT = 6, 150 CORE_CLK_PLL_SEL_MASK = 0x3 << CORE_CLK_PLL_SEL_SHIFT, 151 CORE_CLK_PLL_SEL_APLL = 0, 152 CORE_CLK_PLL_SEL_VPLL0, 153 CORE_CLK_PLL_SEL_VPLL1, 154 CORE_DIV_CON_SHIFT = 0, 155 CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT, 156 157 /* CRU_CLK_SEL2_CON */ 158 CLK_RTC32K_SEL_SHIFT = 8, 159 CLK_RTC32K_SEL_MASK = 3 << CLK_RTC32K_SEL_SHIFT, 160 CLK_RTC32K_IO = 0, 161 CLK_RTC32K_PVTM, 162 CLK_RTC32K_FRAC_DIV, 163 CLK_RTC32K_DIV, 164 165 /* CRU_CLK_SEL3_CON */ 166 CLK_RTC32K_FRAC_NUMERATOR_SHIFT = 16, 167 CLK_RTC32K_FRAC_NUMERATOR_MASK = 0xffff << 16, 168 CLK_RTC32K_FRAC_DENOMINATOR_SHIFT = 0, 169 CLK_RTC32K_FRAC_DENOMINATOR_MASK = 0xffff, 170 171 /* CRU_CLK_SEL5_CON */ 172 BUS_PLL_SEL_SHIFT = 6, 173 BUS_PLL_SEL_MASK = 0x3 << BUS_PLL_SEL_SHIFT, 174 BUS_PLL_SEL_DPLL = 0, 175 BUS_PLL_SEL_VPLL0, 176 BUS_PLL_SEL_VPLL1, 177 BUS_ACLK_DIV_SHIFT = 0, 178 BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, 179 180 /* CRU_CLK_SEL6_CON */ 181 BUS_PCLK_DIV_SHIFT = 8, 182 BUS_PCLK_DIV_MASK = 0x1f << BUS_PCLK_DIV_SHIFT, 183 BUS_HCLK_DIV_SHIFT = 0, 184 BUS_HCLK_DIV_MASK = 0x1f << BUS_HCLK_DIV_SHIFT, 185 186 /* CRU_CLK_SEL7_CON */ 187 CRYPTO_APK_SEL_SHIFT = 14, 188 CRYPTO_APK_PLL_SEL_MASK = 3 << CRYPTO_APK_SEL_SHIFT, 189 CRYPTO_PLL_SEL_DPLL = 0, 190 CRYPTO_PLL_SEL_VPLL0, 191 CRYPTO_PLL_SEL_VPLL1 = 0, 192 CRYPTO_APK_DIV_SHIFT = 8, 193 CRYPTO_APK_DIV_MASK = 0x1f << CRYPTO_APK_DIV_SHIFT, 194 CRYPTO_PLL_SEL_SHIFT = 6, 195 CRYPTO_PLL_SEL_MASK = 3 << CRYPTO_PLL_SEL_SHIFT, 196 CRYPTO_DIV_SHIFT = 0, 197 CRYPTO_DIV_MASK = 0x1f << CRYPTO_DIV_SHIFT, 198 199 /* CRU_CLK_SEL8_CON */ 200 DCLK_VOP_SEL_SHIFT = 14, 201 DCLK_VOP_SEL_MASK = 0x3 << DCLK_VOP_SEL_SHIFT, 202 DCLK_VOP_SEL_DIVOUT = 0, 203 DCLK_VOP_SEL_FRACOUT, 204 DCLK_VOP_SEL_24M, 205 DCLK_VOP_PLL_SEL_SHIFT = 10, 206 DCLK_VOP_PLL_SEL_MASK = 0x3 << DCLK_VOP_PLL_SEL_SHIFT, 207 DCLK_VOP_PLL_SEL_DPLL = 0, 208 DCLK_VOP_PLL_SEL_VPLL0, 209 DCLK_VOP_PLL_SEL_VPLL1, 210 DCLK_VOP_DIV_SHIFT = 0, 211 DCLK_VOP_DIV_MASK = 0xff, 212 213 /* CRU_CLK_SEL25_CON */ 214 /* CRU_CLK_SEL26_CON */ 215 /* CRU_CLK_SEL27_CON */ 216 /* CRU_CLK_SEL28_CON */ 217 CLK_I2C_PLL_SEL_SHIFT = 14, 218 CLK_I2C_PLL_SEL_MASK = 0x3 << CLK_I2C_PLL_SEL_SHIFT, 219 CLK_I2C_PLL_SEL_DPLL = 0, 220 CLK_I2C_PLL_SEL_VPLL0, 221 CLK_I2C_PLL_SEL_24M, 222 CLK_I2C_DIV_CON_SHIFT = 0, 223 CLK_I2C_DIV_CON_MASK = 0x7f << CLK_I2C_DIV_CON_SHIFT, 224 225 /* CRU_CLK_SEL29_CON */ 226 CLK_PWM_PLL_SEL_SHIFT = 14, 227 CLK_PWM_PLL_SEL_MASK = 0x3 << CLK_PWM_PLL_SEL_SHIFT, 228 CLK_PWM_PLL_SEL_DPLL = 0, 229 CLK_PWM_PLL_SEL_VPLL0, 230 CLK_PWM_PLL_SEL_24M, 231 CLK_PWM_DIV_CON_SHIFT = 0, 232 CLK_PWM_DIV_CON_MASK = 0x7f << CLK_PWM_DIV_CON_SHIFT, 233 234 /* CRU_CLK_SEL30_CON */ 235 /* CRU_CLK_SEL31_CON */ 236 /* CRU_CLK_SEL32_CON */ 237 CLK_SPI_PLL_SEL_SHIFT = 14, 238 CLK_SPI_PLL_SEL_MASK = 0x3 << CLK_SPI_PLL_SEL_SHIFT, 239 CLK_SPI_PLL_SEL_DPLL = 0, 240 CLK_SPI_PLL_SEL_VPLL0, 241 CLK_SPI_PLL_SEL_24M, 242 CLK_SPI_DIV_CON_SHIFT = 0, 243 CLK_SPI_DIV_CON_MASK = 0x7f << CLK_SPI_DIV_CON_SHIFT, 244 245 /* CRU_CLK_SEL34_CON */ 246 CLK_SARADC_DIV_CON_SHIFT = 0, 247 CLK_SARADC_DIV_CON_MASK = 0x7ff << CLK_SARADC_DIV_CON_SHIFT, 248 249 /* CRU_CLK_SEL36_CON */ 250 PERI_PLL_SEL_SHIFT = 6, 251 PERI_PLL_SEL_MASK = 0x3 << PERI_PLL_SEL_SHIFT, 252 PERI_PLL_DPLL = 0, 253 PERI_PLL_VPLL0, 254 PERI_PLL_VPLL1, 255 PERI_ACLK_DIV_SHIFT = 0, 256 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, 257 258 /* CRU_CLK_SEL37_CON */ 259 PERI_PCLK_DIV_SHIFT = 8, 260 PERI_PCLK_DIV_MASK = 0x1f << PERI_PCLK_DIV_SHIFT, 261 PERI_HCLK_DIV_SHIFT = 0, 262 PERI_HCLK_DIV_MASK = 0x1f << PERI_HCLK_DIV_SHIFT, 263 264 /* CRU_CLKSEL41_CON */ 265 EMMC_CLK_SEL_SHIFT = 15, 266 EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT, 267 EMMC_CLK_SEL_EMMC = 0, 268 EMMC_CLK_SEL_EMMC_DIV50, 269 EMMC_PLL_SHIFT = 8, 270 EMMC_PLL_MASK = 0x3 << EMMC_PLL_SHIFT, 271 EMMC_SEL_DPLL = 0, 272 EMMC_SEL_VPLL0, 273 EMMC_SEL_VPLL1, 274 EMMC_SEL_24M, 275 EMMC_DIV_SHIFT = 0, 276 EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT, 277 278 /* CRU_CLKSEL42_CON */ 279 SCLK_SFC_SEL_SHIFT = 14, 280 SCLK_SFC_SEL_MASK = 0x3 << SCLK_SFC_SEL_SHIFT, 281 SCLK_SFC_SEL_DPLL = 0, 282 SCLK_SFC_SEL_VPLL0, 283 SCLK_SFC_SEL_VPLL1, 284 SCLK_SFC_DIV_SHIFT = 0, 285 SCLK_SFC_DIV_MASK = 0x7f << SCLK_SFC_DIV_SHIFT, 286 287 /* CRU_CLKSEL43_CON */ 288 MAC_CLK_SPEED_SEL_SHIFT = 15, 289 MAC_CLK_SPEED_SEL_MASK = 1 << MAC_CLK_SPEED_SEL_SHIFT, 290 MAC_CLK_SPEED_SEL_10M = 0, 291 MAC_CLK_SPEED_SEL_100M, 292 MAC_CLK_SOURCE_SEL_SHIFT = 14, 293 MAC_CLK_SOURCE_SEL_MASK = 1 << MAC_CLK_SOURCE_SEL_SHIFT, 294 MAC_CLK_SOURCE_SEL_INTERNAL = 0, 295 MAC_CLK_SOURCE_SEL_EXTERNAL, 296 MAC_PLL_SHIFT = 6, 297 MAC_PLL_MASK = 0x3 << MAC_PLL_SHIFT, 298 MAC_SEL_DPLL = 0, 299 MAC_SEL_VPLL0, 300 MAC_SEL_VPLL1, 301 MAC_DIV_SHIFT = 0, 302 MAC_DIV_MASK = 0x1f << MAC_DIV_SHIFT, 303 304 /* CRU_CLK_SEL45_CON */ 305 AUDIO_PCLK_DIV_SHIFT = 8, 306 AUDIO_PCLK_DIV_MASK = 0x1f << AUDIO_PCLK_DIV_SHIFT, 307 AUDIO_PLL_SEL_SHIFT = 6, 308 AUDIO_PLL_SEL_MASK = 0x3 << AUDIO_PLL_SEL_SHIFT, 309 AUDIO_PLL_VPLL0 = 0, 310 AUDIO_PLL_VPLL1, 311 AUDIO_PLL_24M, 312 AUDIO_HCLK_DIV_SHIFT = 0, 313 AUDIO_HCLK_DIV_MASK = 0x1f << AUDIO_HCLK_DIV_SHIFT, 314 }; 315 316 check_member(rk3308_cru, emmc_con[1], 0x494); 317 318 #endif 319