1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2020 Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <dm.h> 8 #include <dm/pinctrl.h> 9 #include <regmap.h> 10 #include <syscon.h> 11 #include <asm/arch/cpu.h> 12 13 #include "pinctrl-rockchip.h" 14 15 static struct rockchip_mux_route_data rk3308_mux_route_data[] = { 16 { 17 /* rtc_clk */ 18 .bank_num = 0, 19 .pin = 19, 20 .func = 1, 21 .route_offset = 0x314, 22 .route_val = BIT(16 + 0) | BIT(0), 23 }, { 24 /* uart2_rxm0 */ 25 .bank_num = 1, 26 .pin = 22, 27 .func = 2, 28 .route_offset = 0x314, 29 .route_val = BIT(16 + 2) | BIT(16 + 3), 30 }, { 31 /* uart2_rxm1 */ 32 .bank_num = 4, 33 .pin = 26, 34 .func = 2, 35 .route_offset = 0x314, 36 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), 37 }, { 38 /* i2c3_sdam0 */ 39 .bank_num = 0, 40 .pin = 23, 41 .func = 2, 42 .route_offset = 0x314, 43 .route_val = BIT(16 + 4), 44 }, { 45 /* i2c3_sdam1 */ 46 .bank_num = 3, 47 .pin = 12, 48 .func = 2, 49 .route_offset = 0x314, 50 .route_val = BIT(16 + 4) | BIT(4), 51 }, { 52 /* i2s-8ch-1-sclktxm0 */ 53 .bank_num = 1, 54 .pin = 3, 55 .func = 2, 56 .route_offset = 0x308, 57 .route_val = BIT(16 + 3), 58 }, { 59 /* i2s-8ch-1-sclkrxm0 */ 60 .bank_num = 1, 61 .pin = 4, 62 .func = 2, 63 .route_offset = 0x308, 64 .route_val = BIT(16 + 3), 65 }, { 66 /* i2s-8ch-1-sclktxm1 */ 67 .bank_num = 1, 68 .pin = 13, 69 .func = 2, 70 .route_offset = 0x308, 71 .route_val = BIT(16 + 3) | BIT(3), 72 }, { 73 /* i2s-8ch-1-sclkrxm1 */ 74 .bank_num = 1, 75 .pin = 14, 76 .func = 2, 77 .route_offset = 0x308, 78 .route_val = BIT(16 + 3) | BIT(3), 79 }, { 80 /* pdm-clkm0 */ 81 .bank_num = 1, 82 .pin = 4, 83 .func = 3, 84 .route_offset = 0x308, 85 .route_val = BIT(16 + 12) | BIT(16 + 13), 86 }, { 87 /* pdm-clkm1 */ 88 .bank_num = 1, 89 .pin = 14, 90 .func = 4, 91 .route_offset = 0x308, 92 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 93 }, { 94 /* pdm-clkm2 */ 95 .bank_num = 2, 96 .pin = 6, 97 .func = 2, 98 .route_offset = 0x308, 99 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 100 }, { 101 /* pdm-clkm-m2 */ 102 .bank_num = 2, 103 .pin = 4, 104 .func = 3, 105 .route_offset = 0x600, 106 .route_val = BIT(16 + 2) | BIT(2), 107 }, 108 }; 109 110 static struct rockchip_mux_route_data rk3308b_mux_route_data[] = { 111 { 112 /* rtc_clk */ 113 .bank_num = 0, 114 .pin = 19, 115 .func = 1, 116 .route_offset = 0x314, 117 .route_val = BIT(16 + 0) | BIT(0), 118 }, { 119 /* uart2_rxm0 */ 120 .bank_num = 1, 121 .pin = 22, 122 .func = 2, 123 .route_offset = 0x314, 124 .route_val = BIT(16 + 2) | BIT(16 + 3), 125 }, { 126 /* uart2_rxm1 */ 127 .bank_num = 4, 128 .pin = 26, 129 .func = 2, 130 .route_offset = 0x314, 131 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), 132 }, { 133 /* i2c3_sdam0 */ 134 .bank_num = 0, 135 .pin = 15, 136 .func = 2, 137 .route_offset = 0x608, 138 .route_val = BIT(16 + 8) | BIT(16 + 9), 139 }, { 140 /* i2c3_sdam1 */ 141 .bank_num = 3, 142 .pin = 12, 143 .func = 2, 144 .route_offset = 0x608, 145 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8), 146 }, { 147 /* i2c3_sdam2 */ 148 .bank_num = 2, 149 .pin = 0, 150 .func = 3, 151 .route_offset = 0x608, 152 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9), 153 }, { 154 /* i2s-8ch-1-sclktxm0 */ 155 .bank_num = 1, 156 .pin = 3, 157 .func = 2, 158 .route_offset = 0x308, 159 .route_val = BIT(16 + 3), 160 }, { 161 /* i2s-8ch-1-sclkrxm0 */ 162 .bank_num = 1, 163 .pin = 4, 164 .func = 2, 165 .route_offset = 0x308, 166 .route_val = BIT(16 + 3), 167 }, { 168 /* i2s-8ch-1-sclktxm1 */ 169 .bank_num = 1, 170 .pin = 13, 171 .func = 2, 172 .route_offset = 0x308, 173 .route_val = BIT(16 + 3) | BIT(3), 174 }, { 175 /* i2s-8ch-1-sclkrxm1 */ 176 .bank_num = 1, 177 .pin = 14, 178 .func = 2, 179 .route_offset = 0x308, 180 .route_val = BIT(16 + 3) | BIT(3), 181 }, { 182 /* pdm-clkm0 */ 183 .bank_num = 1, 184 .pin = 4, 185 .func = 3, 186 .route_offset = 0x308, 187 .route_val = BIT(16 + 12) | BIT(16 + 13), 188 }, { 189 /* pdm-clkm1 */ 190 .bank_num = 1, 191 .pin = 14, 192 .func = 4, 193 .route_offset = 0x308, 194 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 195 }, { 196 /* pdm-clkm2 */ 197 .bank_num = 2, 198 .pin = 6, 199 .func = 2, 200 .route_offset = 0x308, 201 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 202 }, { 203 /* pdm-clkm-m2 */ 204 .bank_num = 2, 205 .pin = 4, 206 .func = 3, 207 .route_offset = 0x600, 208 .route_val = BIT(16 + 2) | BIT(2), 209 }, { 210 /* spi1_miso */ 211 .bank_num = 3, 212 .pin = 10, 213 .func = 3, 214 .route_offset = 0x314, 215 .route_val = BIT(16 + 9), 216 }, { 217 /* spi1_miso_m1 */ 218 .bank_num = 2, 219 .pin = 4, 220 .func = 2, 221 .route_offset = 0x314, 222 .route_val = BIT(16 + 9) | BIT(9), 223 }, { 224 /* owire_m0 */ 225 .bank_num = 0, 226 .pin = 11, 227 .func = 3, 228 .route_offset = 0x314, 229 .route_val = BIT(16 + 10) | BIT(16 + 11), 230 }, { 231 /* owire_m1 */ 232 .bank_num = 1, 233 .pin = 22, 234 .func = 7, 235 .route_offset = 0x314, 236 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 237 }, { 238 /* owire_m2 */ 239 .bank_num = 2, 240 .pin = 2, 241 .func = 5, 242 .route_offset = 0x314, 243 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 244 }, { 245 /* can_rxd_m0 */ 246 .bank_num = 0, 247 .pin = 11, 248 .func = 2, 249 .route_offset = 0x314, 250 .route_val = BIT(16 + 12) | BIT(16 + 13), 251 }, { 252 /* can_rxd_m1 */ 253 .bank_num = 1, 254 .pin = 22, 255 .func = 5, 256 .route_offset = 0x314, 257 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 258 }, { 259 /* can_rxd_m2 */ 260 .bank_num = 2, 261 .pin = 2, 262 .func = 4, 263 .route_offset = 0x314, 264 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 265 }, { 266 /* mac_rxd0_m0 */ 267 .bank_num = 1, 268 .pin = 20, 269 .func = 3, 270 .route_offset = 0x314, 271 .route_val = BIT(16 + 14), 272 }, { 273 /* mac_rxd0_m1 */ 274 .bank_num = 4, 275 .pin = 2, 276 .func = 2, 277 .route_offset = 0x314, 278 .route_val = BIT(16 + 14) | BIT(14), 279 }, { 280 /* uart3_rx */ 281 .bank_num = 3, 282 .pin = 12, 283 .func = 4, 284 .route_offset = 0x314, 285 .route_val = BIT(16 + 15), 286 }, { 287 /* uart3_rx_m1 */ 288 .bank_num = 0, 289 .pin = 17, 290 .func = 3, 291 .route_offset = 0x314, 292 .route_val = BIT(16 + 15) | BIT(15), 293 }, 294 }; 295 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { 296 { 297 .num = 1, 298 .pin = 14, 299 .reg = 0x28, 300 .bit = 12, 301 .mask = 0x7 302 }, { 303 .num = 1, 304 .pin = 15, 305 .reg = 0x2c, 306 .bit = 0, 307 .mask = 0x3 308 }, { 309 .num = 1, 310 .pin = 18, 311 .reg = 0x30, 312 .bit = 4, 313 .mask = 0x7 314 }, { 315 .num = 1, 316 .pin = 19, 317 .reg = 0x30, 318 .bit = 8, 319 .mask = 0x7 320 }, { 321 .num = 1, 322 .pin = 20, 323 .reg = 0x30, 324 .bit = 12, 325 .mask = 0x7 326 }, { 327 .num = 1, 328 .pin = 21, 329 .reg = 0x34, 330 .bit = 0, 331 .mask = 0x7 332 }, { 333 .num = 1, 334 .pin = 22, 335 .reg = 0x34, 336 .bit = 4, 337 .mask = 0x7 338 }, { 339 .num = 1, 340 .pin = 23, 341 .reg = 0x34, 342 .bit = 8, 343 .mask = 0x7 344 }, { 345 .num = 3, 346 .pin = 12, 347 .reg = 0x68, 348 .bit = 8, 349 .mask = 0x7 350 }, { 351 .num = 3, 352 .pin = 13, 353 .reg = 0x68, 354 .bit = 12, 355 .mask = 0x7 356 }, 357 }; 358 359 static struct rockchip_mux_recalced_data rk3308b_mux_recalced_data[] = { 360 { 361 .num = 1, 362 .pin = 14, 363 .reg = 0x28, 364 .bit = 12, 365 .mask = 0xf 366 }, { 367 .num = 1, 368 .pin = 15, 369 .reg = 0x2c, 370 .bit = 0, 371 .mask = 0x3 372 }, { 373 .num = 1, 374 .pin = 18, 375 .reg = 0x30, 376 .bit = 4, 377 .mask = 0xf 378 }, { 379 .num = 1, 380 .pin = 19, 381 .reg = 0x30, 382 .bit = 8, 383 .mask = 0xf 384 }, { 385 .num = 1, 386 .pin = 20, 387 .reg = 0x30, 388 .bit = 12, 389 .mask = 0xf 390 }, { 391 .num = 1, 392 .pin = 21, 393 .reg = 0x34, 394 .bit = 0, 395 .mask = 0xf 396 }, { 397 .num = 1, 398 .pin = 22, 399 .reg = 0x34, 400 .bit = 4, 401 .mask = 0xf 402 }, { 403 .num = 1, 404 .pin = 23, 405 .reg = 0x34, 406 .bit = 8, 407 .mask = 0xf 408 }, { 409 .num = 3, 410 .pin = 12, 411 .reg = 0x68, 412 .bit = 8, 413 .mask = 0xf 414 }, { 415 .num = 3, 416 .pin = 13, 417 .reg = 0x68, 418 .bit = 12, 419 .mask = 0xf 420 }, { 421 .num = 2, 422 .pin = 2, 423 .reg = 0x608, 424 .bit = 0, 425 .mask = 0x7 426 }, { 427 .num = 2, 428 .pin = 3, 429 .reg = 0x608, 430 .bit = 4, 431 .mask = 0x7 432 }, { 433 .num = 2, 434 .pin = 16, 435 .reg = 0x610, 436 .bit = 8, 437 .mask = 0x7 438 }, { 439 .num = 3, 440 .pin = 10, 441 .reg = 0x610, 442 .bit = 0, 443 .mask = 0x7 444 }, { 445 .num = 3, 446 .pin = 11, 447 .reg = 0x610, 448 .bit = 4, 449 .mask = 0x7 450 }, 451 }; 452 453 static int rk3308_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 454 { 455 struct rockchip_pinctrl_priv *priv = bank->priv; 456 int iomux_num = (pin / 8); 457 struct regmap *regmap; 458 int reg, ret, mask, mux_type; 459 u8 bit; 460 u32 data; 461 462 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 463 464 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 465 regmap = priv->regmap_pmu; 466 else 467 regmap = priv->regmap_base; 468 469 /* get basic quadrupel of mux registers and the correct reg inside */ 470 mux_type = bank->iomux[iomux_num].type; 471 reg = bank->iomux[iomux_num].offset; 472 if (mux_type & IOMUX_WIDTH_4BIT) { 473 if ((pin % 8) >= 4) 474 reg += 0x4; 475 bit = (pin % 4) * 4; 476 mask = 0xf; 477 } else { 478 bit = (pin % 8) * 2; 479 mask = 0x3; 480 } 481 482 if (bank->recalced_mask & BIT(pin)) 483 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 484 485 data = (mask << (bit + 16)); 486 data |= (mux & mask) << bit; 487 ret = regmap_write(regmap, reg, data); 488 489 return ret; 490 } 491 492 #define RK3308_PULL_OFFSET 0xa0 493 #define RK3308_PULL_BITS_PER_PIN 2 494 #define RK3308_PULL_PINS_PER_REG 8 495 #define RK3308_PULL_BANK_STRIDE 16 496 497 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 498 int pin_num, struct regmap **regmap, 499 int *reg, u8 *bit) 500 { 501 struct rockchip_pinctrl_priv *priv = bank->priv; 502 503 *regmap = priv->regmap_base; 504 *reg = RK3308_PULL_OFFSET; 505 *reg += bank->bank_num * RK3308_PULL_BANK_STRIDE; 506 *reg += ((pin_num / RK3308_PULL_PINS_PER_REG) * 4); 507 508 *bit = (pin_num % RK3308_PULL_PINS_PER_REG); 509 *bit *= RK3308_PULL_BITS_PER_PIN; 510 } 511 512 #define RK3308_DRV_GRF_OFFSET 0x100 513 #define RK3308_DRV_BITS_PER_PIN 2 514 #define RK3308_DRV_PINS_PER_REG 8 515 #define RK3308_DRV_BANK_STRIDE 16 516 517 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 518 int pin_num, struct regmap **regmap, 519 int *reg, u8 *bit) 520 { 521 struct rockchip_pinctrl_priv *priv = bank->priv; 522 523 *regmap = priv->regmap_base; 524 *reg = RK3308_DRV_GRF_OFFSET; 525 *reg += bank->bank_num * RK3308_DRV_BANK_STRIDE; 526 *reg += ((pin_num / RK3308_DRV_PINS_PER_REG) * 4); 527 528 *bit = (pin_num % RK3308_DRV_PINS_PER_REG); 529 *bit *= RK3308_DRV_BITS_PER_PIN; 530 } 531 532 #define RK3308_SCHMITT_PINS_PER_REG 8 533 #define RK3308_SCHMITT_BANK_STRIDE 16 534 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0 535 536 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 537 int pin_num, 538 struct regmap **regmap, 539 int *reg, u8 *bit) 540 { 541 struct rockchip_pinctrl_priv *priv = bank->priv; 542 543 *regmap = priv->regmap_base; 544 *reg = RK3308_SCHMITT_GRF_OFFSET; 545 546 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; 547 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4); 548 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG; 549 550 return 0; 551 } 552 553 static int rk3308_set_pull(struct rockchip_pin_bank *bank, 554 int pin_num, int pull) 555 { 556 struct regmap *regmap; 557 int reg, ret; 558 u8 bit, type; 559 u32 data; 560 561 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) 562 return -ENOTSUPP; 563 564 rk3308_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); 565 type = bank->pull_type[pin_num / 8]; 566 ret = rockchip_translate_pull_value(type, pull); 567 if (ret < 0) { 568 debug("unsupported pull setting %d\n", pull); 569 return ret; 570 } 571 572 /* enable the write to the equivalent lower bits */ 573 data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); 574 575 data |= (ret << bit); 576 ret = regmap_write(regmap, reg, data); 577 578 return ret; 579 } 580 581 static int rk3308_set_drive(struct rockchip_pin_bank *bank, 582 int pin_num, int strength) 583 { 584 struct regmap *regmap; 585 int reg; 586 u32 data; 587 u8 bit; 588 589 rk3308_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); 590 591 /* enable the write to the equivalent lower bits */ 592 data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16); 593 data |= (strength << bit); 594 595 return regmap_write(regmap, reg, data); 596 } 597 598 static int rk3308_set_schmitt(struct rockchip_pin_bank *bank, 599 int pin_num, int enable) 600 { 601 struct regmap *regmap; 602 int reg; 603 u8 bit; 604 u32 data; 605 606 rk3308_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit); 607 /* enable the write to the equivalent lower bits */ 608 data = BIT(bit + 16) | (enable << bit); 609 610 return regmap_write(regmap, reg, data); 611 } 612 613 static struct rockchip_pin_bank rk3308_pin_banks[] = { 614 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_8WIDTH_2BIT, 615 IOMUX_8WIDTH_2BIT, 616 IOMUX_8WIDTH_2BIT, 617 IOMUX_8WIDTH_2BIT), 618 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_8WIDTH_2BIT, 619 IOMUX_8WIDTH_2BIT, 620 IOMUX_8WIDTH_2BIT, 621 IOMUX_8WIDTH_2BIT), 622 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_8WIDTH_2BIT, 623 IOMUX_8WIDTH_2BIT, 624 IOMUX_8WIDTH_2BIT, 625 IOMUX_8WIDTH_2BIT), 626 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_8WIDTH_2BIT, 627 IOMUX_8WIDTH_2BIT, 628 IOMUX_8WIDTH_2BIT, 629 IOMUX_8WIDTH_2BIT), 630 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_8WIDTH_2BIT, 631 IOMUX_8WIDTH_2BIT, 632 IOMUX_8WIDTH_2BIT, 633 IOMUX_8WIDTH_2BIT), 634 }; 635 636 static struct rockchip_pin_ctrl rk3308_pin_ctrl = { 637 .pin_banks = rk3308_pin_banks, 638 .nr_banks = ARRAY_SIZE(rk3308_pin_banks), 639 .nr_pins = 160, 640 .grf_mux_offset = 0x0, 641 .iomux_recalced = rk3308_mux_recalced_data, 642 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data), 643 .iomux_routes = rk3308_mux_route_data, 644 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data), 645 .set_mux = rk3308_set_mux, 646 .set_pull = rk3308_set_pull, 647 .set_drive = rk3308_set_drive, 648 .set_schmitt = rk3308_set_schmitt, 649 }; 650 651 static const struct rockchip_pin_ctrl rk3308b_pin_ctrl = { 652 .pin_banks = rk3308_pin_banks, 653 .nr_banks = ARRAY_SIZE(rk3308_pin_banks), 654 .nr_pins = 160, 655 .grf_mux_offset = 0x0, 656 .iomux_recalced = rk3308b_mux_recalced_data, 657 .niomux_recalced = ARRAY_SIZE(rk3308b_mux_recalced_data), 658 .iomux_routes = rk3308b_mux_route_data, 659 .niomux_routes = ARRAY_SIZE(rk3308b_mux_route_data), 660 .set_mux = rk3308_set_mux, 661 .set_pull = rk3308_set_pull, 662 .set_drive = rk3308_set_drive, 663 .set_schmitt = rk3308_set_schmitt, 664 }; 665 666 static const struct udevice_id rk3308_pinctrl_ids[] = { 667 { 668 .compatible = "rockchip,rk3308-pinctrl", 669 .data = (ulong)&rk3308_pin_ctrl 670 }, 671 { } 672 }; 673 674 /* rk3308b SoC data initialize */ 675 #define RK3308B_GRF_SOC_CON13 0x608 676 #define RK3308B_GRF_SOC_CON15 0x610 677 678 /* RK3308B_GRF_SOC_CON13 */ 679 #define RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL (BIT(16 + 10) | BIT(10)) 680 #define RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) 681 #define RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) 682 683 /* RK3308B_GRF_SOC_CON15 */ 684 #define RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL (BIT(16 + 11) | BIT(11)) 685 #define RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) 686 #define RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) 687 688 static int rk3308b_soc_data_init(struct udevice *dev) 689 { 690 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 691 int ret; 692 693 /* 694 * Enable the special ctrl of selected sources. 695 */ 696 ret = regmap_write(priv->regmap_base, RK3308B_GRF_SOC_CON13, 697 RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL | 698 RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL | 699 RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL); 700 if (ret) 701 return ret; 702 703 ret = regmap_write(priv->regmap_base, RK3308B_GRF_SOC_CON15, 704 RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL | 705 RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL | 706 RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL); 707 if (ret) 708 return ret; 709 710 return 0; 711 } 712 713 static int rk3308_pinctrl_probe(struct udevice *dev) 714 { 715 int ret; 716 717 if (soc_is_rk3308b()) 718 dev->driver_data = (ulong)&rk3308b_pin_ctrl; 719 720 ret = rockchip_pinctrl_probe(dev); 721 if (ret) 722 return ret; 723 724 if (soc_is_rk3308b()) 725 ret = rk3308b_soc_data_init(dev); 726 727 return ret; 728 } 729 730 U_BOOT_DRIVER(pinctrl_rk3308) = { 731 .name = "rockchip_rk3308_pinctrl", 732 .id = UCLASS_PINCTRL, 733 .of_match = rk3308_pinctrl_ids, 734 .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), 735 .ops = &rockchip_pinctrl_ops, 736 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 737 .bind = dm_scan_fdt_dev, 738 #endif 739 .probe = rk3308_pinctrl_probe, 740 }; 741