1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <asm/unaligned.h> 12 #include <asm/io.h> 13 #include <dm/device.h> 14 #include <dm/of_access.h> 15 #include <dm/read.h> 16 #include <linux/bitfield.h> 17 #include <linux/list.h> 18 #include <syscon.h> 19 #include <asm/arch-rockchip/clock.h> 20 #include <asm/gpio.h> 21 22 #include "rockchip_display.h" 23 #include "rockchip_crtc.h" 24 #include "rockchip_connector.h" 25 #include "analogix_dp.h" 26 27 #define RK3588_GRF_VO1_CON0 0x0000 28 #define EDP_MODE BIT(0) 29 #define RK3588_GRF_VO1_CON1 0x0004 30 31 /** 32 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips 33 * @lcdsel_grf_reg: grf register offset of lcdc select 34 * @lcdsel_big: reg value of selecting vop big for eDP 35 * @lcdsel_lit: reg value of selecting vop little for eDP 36 * @chip_type: specific chip type 37 * @ssc: check if SSC is supported by source 38 */ 39 struct rockchip_dp_chip_data { 40 u32 lcdsel_grf_reg; 41 u32 lcdsel_big; 42 u32 lcdsel_lit; 43 u32 chip_type; 44 bool ssc; 45 46 u32 max_link_rate; 47 u32 max_lane_count; 48 }; 49 50 static void 51 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp, 52 bool enable) 53 { 54 u8 data; 55 56 analogix_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data); 57 58 if (enable) 59 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, 60 DP_LANE_COUNT_ENHANCED_FRAME_EN | 61 DPCD_LANE_COUNT_SET(data)); 62 else 63 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, 64 DPCD_LANE_COUNT_SET(data)); 65 } 66 67 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp) 68 { 69 u8 data; 70 int retval; 71 72 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); 73 retval = DPCD_ENHANCED_FRAME_CAP(data); 74 75 return retval; 76 } 77 78 static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp) 79 { 80 u8 data; 81 82 data = analogix_dp_is_enhanced_mode_available(dp); 83 analogix_dp_enable_rx_to_enhanced_mode(dp, data); 84 analogix_dp_enable_enhanced_mode(dp, data); 85 } 86 87 static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp) 88 { 89 analogix_dp_set_training_pattern(dp, DP_NONE); 90 91 analogix_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET, 92 DP_TRAINING_PATTERN_DISABLE); 93 } 94 95 static int analogix_dp_link_start(struct analogix_dp_device *dp) 96 { 97 u8 buf[4]; 98 int lane, lane_count, retval; 99 100 lane_count = dp->link_train.lane_count; 101 102 dp->link_train.lt_state = CLOCK_RECOVERY; 103 dp->link_train.eq_loop = 0; 104 105 for (lane = 0; lane < lane_count; lane++) 106 dp->link_train.cr_loop[lane] = 0; 107 108 /* Set link rate and count as you want to establish */ 109 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); 110 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); 111 112 if (dp->nr_link_rate_table) { 113 /* Setup DP_LINK_RATE_SET for eDP 1.4 and later */ 114 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, dp->link_train.lane_count); 115 analogix_dp_write_byte_to_dpcd(dp, DP_LINK_RATE_SET, dp->link_rate_select); 116 } else { 117 /* Setup DP_LINK_BW_SET for eDP 1.3 and earlier */ 118 buf[0] = dp->link_train.link_rate; 119 buf[1] = dp->link_train.lane_count; 120 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf); 121 if (retval) 122 return retval; 123 } 124 125 /* Spread AMP if required, enable 8b/10b coding */ 126 buf[0] = analogix_dp_ssc_supported(dp) ? DP_SPREAD_AMP_0_5 : 0; 127 buf[1] = DP_SET_ANSI_8B10B; 128 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_DOWNSPREAD_CTRL, 129 2, buf); 130 if (retval < 0) 131 return retval; 132 133 /* Set TX voltage-swing and pre-emphasis to minimum */ 134 for (lane = 0; lane < lane_count; lane++) 135 dp->link_train.training_lane[lane] = 136 DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | 137 DP_TRAIN_PRE_EMPH_LEVEL_0; 138 analogix_dp_set_lane_link_training(dp); 139 140 /* Set training pattern 1 */ 141 analogix_dp_set_training_pattern(dp, TRAINING_PTN1); 142 143 /* Set RX training pattern */ 144 retval = analogix_dp_write_byte_to_dpcd(dp, 145 DP_TRAINING_PATTERN_SET, 146 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1); 147 if (retval) 148 return retval; 149 150 for (lane = 0; lane < lane_count; lane++) 151 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | 152 DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 153 154 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, 155 lane_count, buf); 156 157 return retval; 158 } 159 160 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) 161 { 162 int shift = (lane & 1) * 4; 163 u8 link_value = link_status[lane >> 1]; 164 165 return (link_value >> shift) & 0xf; 166 } 167 168 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) 169 { 170 int lane; 171 u8 lane_status; 172 173 for (lane = 0; lane < lane_count; lane++) { 174 lane_status = analogix_dp_get_lane_status(link_status, lane); 175 if ((lane_status & DP_LANE_CR_DONE) == 0) 176 return -EINVAL; 177 } 178 return 0; 179 } 180 181 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align, 182 int lane_count) 183 { 184 int lane; 185 u8 lane_status; 186 187 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0) 188 return -EINVAL; 189 190 for (lane = 0; lane < lane_count; lane++) { 191 lane_status = analogix_dp_get_lane_status(link_status, lane); 192 lane_status &= DP_CHANNEL_EQ_BITS; 193 if (lane_status != DP_CHANNEL_EQ_BITS) 194 return -EINVAL; 195 } 196 197 return 0; 198 } 199 200 static unsigned char 201 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane) 202 { 203 int shift = (lane & 1) * 4; 204 u8 link_value = adjust_request[lane >> 1]; 205 206 return (link_value >> shift) & 0x3; 207 } 208 209 static unsigned char analogix_dp_get_adjust_request_pre_emphasis( 210 u8 adjust_request[2], 211 int lane) 212 { 213 int shift = (lane & 1) * 4; 214 u8 link_value = adjust_request[lane >> 1]; 215 216 return ((link_value >> shift) & 0xc) >> 2; 217 } 218 219 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp) 220 { 221 analogix_dp_training_pattern_dis(dp); 222 analogix_dp_set_enhanced_mode(dp); 223 224 dp->link_train.lt_state = FAILED; 225 } 226 227 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp, 228 u8 adjust_request[2]) 229 { 230 int lane, lane_count; 231 u8 voltage_swing, pre_emphasis, training_lane; 232 233 lane_count = dp->link_train.lane_count; 234 for (lane = 0; lane < lane_count; lane++) { 235 voltage_swing = analogix_dp_get_adjust_request_voltage( 236 adjust_request, lane); 237 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 238 adjust_request, lane); 239 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | 240 DPCD_PRE_EMPHASIS_SET(pre_emphasis); 241 242 if (voltage_swing == VOLTAGE_LEVEL_3) 243 training_lane |= DP_TRAIN_MAX_SWING_REACHED; 244 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) 245 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 246 247 dp->link_train.training_lane[lane] = training_lane; 248 } 249 } 250 251 static bool analogix_dp_tps3_supported(struct analogix_dp_device *dp) 252 { 253 bool source_tps3_supported, sink_tps3_supported; 254 u8 dpcd = 0; 255 256 source_tps3_supported = 257 dp->video_info.max_link_rate == DP_LINK_BW_5_4; 258 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &dpcd); 259 sink_tps3_supported = dpcd & DP_TPS3_SUPPORTED; 260 261 return source_tps3_supported && sink_tps3_supported; 262 } 263 264 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) 265 { 266 int lane, lane_count, retval; 267 u8 voltage_swing, pre_emphasis, training_lane; 268 u8 link_status[2], adjust_request[2]; 269 u8 training_pattern = TRAINING_PTN2; 270 271 drm_dp_link_train_clock_recovery_delay(dp->dpcd); 272 273 lane_count = dp->link_train.lane_count; 274 275 retval = analogix_dp_read_bytes_from_dpcd(dp, 276 DP_LANE0_1_STATUS, 2, link_status); 277 if (retval) 278 return retval; 279 280 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) { 281 if (analogix_dp_tps3_supported(dp)) 282 training_pattern = TRAINING_PTN3; 283 284 /* set training pattern for EQ */ 285 analogix_dp_set_training_pattern(dp, training_pattern); 286 287 retval = analogix_dp_write_byte_to_dpcd(dp, 288 DP_TRAINING_PATTERN_SET, 289 (training_pattern == TRAINING_PTN3 ? 290 DP_TRAINING_PATTERN_3 : DP_TRAINING_PATTERN_2)); 291 if (retval) 292 return retval; 293 294 dev_info(dp->dev, "Link Training Clock Recovery success\n"); 295 dp->link_train.lt_state = EQUALIZER_TRAINING; 296 297 return 0; 298 } else { 299 retval = analogix_dp_read_bytes_from_dpcd(dp, 300 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); 301 if (retval) 302 return retval; 303 304 for (lane = 0; lane < lane_count; lane++) { 305 training_lane = analogix_dp_get_lane_link_training( 306 dp, lane); 307 voltage_swing = analogix_dp_get_adjust_request_voltage( 308 adjust_request, lane); 309 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 310 adjust_request, lane); 311 312 if (DPCD_VOLTAGE_SWING_GET(training_lane) == 313 voltage_swing && 314 DPCD_PRE_EMPHASIS_GET(training_lane) == 315 pre_emphasis) 316 dp->link_train.cr_loop[lane]++; 317 318 /* 319 * In DP spec 1.3, Condition of CR fail are 320 * outlined in section 3.5.1.2.2.1, figure 3-20: 321 * 322 * 1. Maximum Voltage Swing reached 323 * 2. Same Voltage five times 324 */ 325 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || 326 DPCD_VOLTAGE_SWING_GET(training_lane) == VOLTAGE_LEVEL_3) { 327 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", 328 dp->link_train.cr_loop[lane], 329 voltage_swing, pre_emphasis); 330 analogix_dp_reduce_link_rate(dp); 331 return -EIO; 332 } 333 } 334 } 335 336 analogix_dp_get_adjust_training_lane(dp, adjust_request); 337 analogix_dp_set_lane_link_training(dp); 338 339 retval = analogix_dp_write_bytes_to_dpcd(dp, 340 DP_TRAINING_LANE0_SET, lane_count, 341 dp->link_train.training_lane); 342 if (retval) 343 return retval; 344 345 return retval; 346 } 347 348 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp) 349 { 350 int lane_count, retval; 351 u32 reg; 352 u8 link_align, link_status[2], adjust_request[2]; 353 354 drm_dp_link_train_channel_eq_delay(dp->dpcd); 355 356 lane_count = dp->link_train.lane_count; 357 358 retval = analogix_dp_read_bytes_from_dpcd(dp, 359 DP_LANE0_1_STATUS, 2, link_status); 360 if (retval) 361 return retval; 362 363 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) { 364 analogix_dp_reduce_link_rate(dp); 365 return -EIO; 366 } 367 368 retval = analogix_dp_read_byte_from_dpcd(dp, 369 DP_LANE_ALIGN_STATUS_UPDATED, &link_align); 370 if (retval) 371 return retval; 372 373 if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) { 374 /* traing pattern Set to Normal */ 375 analogix_dp_training_pattern_dis(dp); 376 377 printf("Link Training success!\n"); 378 379 analogix_dp_get_link_bandwidth(dp, ®); 380 dp->link_train.link_rate = reg; 381 analogix_dp_get_lane_count(dp, ®); 382 dp->link_train.lane_count = reg; 383 384 printf("final link rate = 0x%.2x, lane count = 0x%.2x\n", 385 dp->link_train.link_rate, dp->link_train.lane_count); 386 387 /* set enhanced mode if available */ 388 analogix_dp_set_enhanced_mode(dp); 389 dp->link_train.lt_state = FINISHED; 390 391 return 0; 392 } 393 394 /* not all locked */ 395 dp->link_train.eq_loop++; 396 397 if (dp->link_train.eq_loop > MAX_EQ_LOOP) { 398 dev_dbg(dp->dev, "EQ Max loop\n"); 399 analogix_dp_reduce_link_rate(dp); 400 return -EIO; 401 } 402 403 retval = analogix_dp_read_bytes_from_dpcd(dp, 404 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); 405 if (retval) 406 return retval; 407 408 analogix_dp_get_adjust_training_lane(dp, adjust_request); 409 analogix_dp_set_lane_link_training(dp); 410 411 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, 412 lane_count, dp->link_train.training_lane); 413 414 return retval; 415 } 416 417 static bool analogix_dp_bandwidth_ok(struct analogix_dp_device *dp, 418 const struct drm_display_mode *mode, 419 unsigned int rate, unsigned int lanes) 420 { 421 u32 max_bw, req_bw; 422 u32 bpp = 3 * dp->video_info.bpc; 423 424 req_bw = mode->clock * bpp / 8; 425 max_bw = lanes * rate; 426 if (req_bw > max_bw) 427 return false; 428 429 return true; 430 } 431 432 static bool analogix_dp_link_config_validate(u8 link_rate, u8 lane_count) 433 { 434 switch (link_rate) { 435 case DP_LINK_BW_1_62: 436 case DP_LINK_BW_2_7: 437 case DP_LINK_BW_5_4: 438 /* Supported link rate in eDP 1.4 */ 439 case EDP_LINK_BW_2_16: 440 case EDP_LINK_BW_2_43: 441 case EDP_LINK_BW_3_24: 442 case EDP_LINK_BW_4_32: 443 break; 444 default: 445 return false; 446 } 447 448 switch (lane_count) { 449 case LANE_COUNT1: 450 case LANE_COUNT2: 451 case LANE_COUNT4: 452 break; 453 default: 454 return false; 455 } 456 457 return true; 458 } 459 460 static int analogix_dp_select_link_rate_from_table(struct analogix_dp_device *dp) 461 { 462 int i; 463 u8 bw_code; 464 u32 max_link_rate = drm_dp_bw_code_to_link_rate(dp->video_info.max_link_rate); 465 466 for (i = 0; i < dp->nr_link_rate_table; i++) { 467 bw_code = drm_dp_link_rate_to_bw_code(dp->link_rate_table[i]); 468 469 if (!analogix_dp_bandwidth_ok(dp, &dp->video_info.mode, dp->link_rate_table[i], 470 dp->link_train.lane_count)) 471 continue; 472 473 if (dp->link_rate_table[i] <= max_link_rate && 474 analogix_dp_link_config_validate(bw_code, dp->link_train.lane_count)) { 475 dp->link_rate_select = i; 476 return bw_code; 477 } 478 } 479 480 return 0; 481 } 482 483 static int analogix_dp_select_rx_bandwidth(struct analogix_dp_device *dp) 484 { 485 if (dp->nr_link_rate_table) 486 /* 487 * Select the smallest one among link rates which meet 488 * the bandwidth requirement for eDP 1.4 and later. 489 */ 490 dp->link_train.link_rate = analogix_dp_select_link_rate_from_table(dp); 491 else 492 /* 493 * Select the smaller one between rx DP_MAX_LINK_RATE 494 * and the max link rate supported by the platform. 495 */ 496 dp->link_train.link_rate = min_t(u32, dp->link_train.link_rate, 497 dp->video_info.max_link_rate); 498 if (!dp->link_train.link_rate) 499 return -EINVAL; 500 501 return 0; 502 } 503 504 static int analogix_dp_init_link_rate_table(struct analogix_dp_device *dp) 505 { 506 u8 link_rate_table[DP_MAX_SUPPORTED_RATES * 2]; 507 int i; 508 int ret; 509 510 ret = analogix_dp_read_bytes_from_dpcd(dp, DP_SUPPORTED_LINK_RATES, 511 sizeof(link_rate_table), link_rate_table); 512 if (ret) 513 return ret; 514 515 for (i = 0; i < ARRAY_SIZE(link_rate_table) / 2; i++) { 516 int val = link_rate_table[2 * i] | link_rate_table[2 * i + 1] << 8; 517 518 if (val == 0) 519 break; 520 521 /* Convert to the link_rate as drm_dp_bw_code_to_link_rate() */ 522 dp->link_rate_table[i] = (val * 20); 523 } 524 dp->nr_link_rate_table = i; 525 526 return 0; 527 } 528 529 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, 530 u8 *bandwidth) 531 { 532 u8 data; 533 int ret; 534 535 analogix_dp_read_byte_from_dpcd(dp, DP_EDP_DPCD_REV, &data); 536 if (data >= DP_EDP_14) { 537 u32 max_link_rate; 538 539 /* As the Table 4-23 in eDP 1.4 spec, the link rate table is required */ 540 if (!dp->nr_link_rate_table) { 541 dev_info(dp->dev, "eDP version: 0x%02x supports link rate table\n", data); 542 543 if (analogix_dp_init_link_rate_table(dp)) 544 dev_err(dp->dev, "failed to read link rate table: %d\n", ret); 545 } 546 max_link_rate = dp->link_rate_table[dp->nr_link_rate_table - 1]; 547 *bandwidth = drm_dp_link_rate_to_bw_code(max_link_rate); 548 } else { 549 /* 550 * For DP rev.1.1, Maximum link rate of Main Link lanes 551 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps 552 * For DP rev.1.2, Maximum link rate of Main Link lanes 553 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps 554 */ 555 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data); 556 *bandwidth = data; 557 } 558 } 559 560 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp, 561 u8 *lane_count) 562 { 563 u8 data; 564 565 /* 566 * For DP rev.1.1, Maximum number of Main Link lanes 567 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes 568 */ 569 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); 570 *lane_count = DPCD_MAX_LANE_COUNT(data); 571 } 572 573 static int analogix_dp_init_training(struct analogix_dp_device *dp, 574 enum link_lane_count_type max_lane, 575 int max_rate) 576 { 577 u8 dpcd; 578 579 /* 580 * MACRO_RST must be applied after the PLL_LOCK to avoid 581 * the DP inter pair skew issue for at least 10 us 582 */ 583 analogix_dp_reset_macro(dp); 584 585 /* Initialize by reading RX's DPCD */ 586 analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); 587 analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); 588 589 /* Setup TX lane count */ 590 dp->link_train.lane_count = min_t(u32, dp->link_train.lane_count, max_lane); 591 592 /* Setup TX lane rate */ 593 if (analogix_dp_select_rx_bandwidth(dp)) { 594 dev_err(dp->dev, "Select rx bandwidth failed\n"); 595 return -EINVAL; 596 } 597 598 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_DOWNSPREAD, &dpcd); 599 dp->link_train.ssc = !!(dpcd & DP_MAX_DOWNSPREAD_0_5); 600 601 /* All DP analog module power up */ 602 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 603 604 return 0; 605 } 606 607 static int analogix_dp_sw_link_training(struct analogix_dp_device *dp) 608 { 609 int retval = 0, training_finished = 0; 610 611 dp->link_train.lt_state = START; 612 613 /* Process here */ 614 while (!retval && !training_finished) { 615 switch (dp->link_train.lt_state) { 616 case START: 617 retval = analogix_dp_link_start(dp); 618 if (retval) 619 dev_err(dp->dev, "LT link start failed!\n"); 620 break; 621 case CLOCK_RECOVERY: 622 retval = analogix_dp_process_clock_recovery(dp); 623 if (retval) 624 dev_err(dp->dev, "LT CR failed!\n"); 625 break; 626 case EQUALIZER_TRAINING: 627 retval = analogix_dp_process_equalizer_training(dp); 628 if (retval) 629 dev_err(dp->dev, "LT EQ failed!\n"); 630 break; 631 case FINISHED: 632 training_finished = 1; 633 break; 634 case FAILED: 635 return -EREMOTEIO; 636 } 637 } 638 639 return retval; 640 } 641 642 static int analogix_dp_set_link_train(struct analogix_dp_device *dp, 643 u32 count, u32 bwtype) 644 { 645 int i, ret; 646 647 for (i = 0; i < 5; i++) { 648 ret = analogix_dp_init_training(dp, count, bwtype); 649 if (ret < 0) { 650 dev_err(dp->dev, "failed to init training\n"); 651 return ret; 652 } 653 654 ret = analogix_dp_sw_link_training(dp); 655 if (!ret) 656 break; 657 } 658 659 return ret; 660 } 661 662 static int analogix_dp_config_video(struct analogix_dp_device *dp) 663 { 664 int timeout_loop = 0; 665 int done_count = 0; 666 667 analogix_dp_config_video_slave_mode(dp); 668 669 analogix_dp_set_video_color_format(dp); 670 671 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 672 dev_err(dp->dev, "PLL is not locked yet.\n"); 673 return -EINVAL; 674 } 675 676 for (;;) { 677 timeout_loop++; 678 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0) 679 break; 680 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 681 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 682 return -ETIMEDOUT; 683 } 684 685 udelay(2); 686 } 687 688 /* Set to use the register calculated M/N video */ 689 analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); 690 691 /* For video bist, Video timing must be generated by register */ 692 analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_REGISTER); 693 694 /* Disable video mute */ 695 analogix_dp_enable_video_mute(dp, 0); 696 697 /* Configure video slave mode */ 698 analogix_dp_enable_video_master(dp, 0); 699 700 /* Enable video input */ 701 analogix_dp_start_video(dp); 702 703 timeout_loop = 0; 704 705 for (;;) { 706 timeout_loop++; 707 if (analogix_dp_is_video_stream_on(dp) == 0) { 708 done_count++; 709 if (done_count > 10) 710 break; 711 } else if (done_count) { 712 done_count = 0; 713 } 714 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 715 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 716 return -ETIMEDOUT; 717 } 718 719 udelay(1001); 720 } 721 722 return 0; 723 } 724 725 static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, 726 bool enable) 727 { 728 u8 data; 729 730 if (enable) { 731 analogix_dp_enable_scrambling(dp); 732 733 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, 734 &data); 735 analogix_dp_write_byte_to_dpcd(dp, 736 DP_TRAINING_PATTERN_SET, 737 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE)); 738 } else { 739 analogix_dp_disable_scrambling(dp); 740 741 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, 742 &data); 743 analogix_dp_write_byte_to_dpcd(dp, 744 DP_TRAINING_PATTERN_SET, 745 (u8)(data | DP_LINK_SCRAMBLING_DISABLE)); 746 } 747 } 748 749 static void analogix_dp_init_dp(struct analogix_dp_device *dp) 750 { 751 analogix_dp_reset(dp); 752 753 analogix_dp_swreset(dp); 754 755 analogix_dp_init_analog_param(dp); 756 analogix_dp_init_interrupt(dp); 757 758 /* SW defined function Normal operation */ 759 analogix_dp_enable_sw_function(dp); 760 761 analogix_dp_config_interrupt(dp); 762 analogix_dp_init_analog_func(dp); 763 764 analogix_dp_init_hpd(dp); 765 analogix_dp_init_aux(dp); 766 } 767 768 static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data) 769 { 770 int i; 771 unsigned char sum = 0; 772 773 for (i = 0; i < EDID_BLOCK_LENGTH; i++) 774 sum = sum + edid_data[i]; 775 776 return sum; 777 } 778 779 static int analogix_dp_read_edid(struct analogix_dp_device *dp) 780 { 781 unsigned char *edid = dp->edid; 782 unsigned int extend_block = 0; 783 unsigned char test_vector; 784 int retval; 785 786 /* 787 * EDID device address is 0x50. 788 * However, if necessary, you must have set upper address 789 * into E-EDID in I2C device, 0x30. 790 */ 791 792 /* Read Extension Flag, Number of 128-byte EDID extension blocks */ 793 retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR, 794 EDID_EXTENSION_FLAG, 795 &extend_block); 796 if (retval) 797 return retval; 798 799 if (extend_block > 0) { 800 debug("EDID data includes a single extension!\n"); 801 802 /* Read EDID data */ 803 retval = analogix_dp_read_bytes_from_i2c(dp, 804 I2C_EDID_DEVICE_ADDR, 805 EDID_HEADER_PATTERN, 806 EDID_BLOCK_LENGTH, 807 &edid[EDID_HEADER_PATTERN]); 808 if (retval < 0) 809 return retval; 810 811 if (analogix_dp_calc_edid_check_sum(edid)) 812 return -EINVAL; 813 814 /* Read additional EDID data */ 815 retval = analogix_dp_read_bytes_from_i2c(dp, 816 I2C_EDID_DEVICE_ADDR, 817 EDID_BLOCK_LENGTH, 818 EDID_BLOCK_LENGTH, 819 &edid[EDID_BLOCK_LENGTH]); 820 if (retval < 0) 821 return retval; 822 823 if (analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH])) 824 return -EINVAL; 825 826 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, 827 &test_vector); 828 if (test_vector & DP_TEST_LINK_EDID_READ) { 829 analogix_dp_write_byte_to_dpcd(dp, 830 DP_TEST_EDID_CHECKSUM, 831 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); 832 analogix_dp_write_byte_to_dpcd(dp, 833 DP_TEST_RESPONSE, 834 DP_TEST_EDID_CHECKSUM_WRITE); 835 } 836 } else { 837 dev_info(dp->dev, 838 "EDID data does not include any extensions.\n"); 839 840 /* Read EDID data */ 841 retval = analogix_dp_read_bytes_from_i2c(dp, 842 I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN, 843 EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]); 844 if (retval < 0) 845 return retval; 846 847 if (analogix_dp_calc_edid_check_sum(edid)) 848 return -EINVAL; 849 850 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, 851 &test_vector); 852 if (test_vector & DP_TEST_LINK_EDID_READ) { 853 analogix_dp_write_byte_to_dpcd(dp, 854 DP_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]); 855 analogix_dp_write_byte_to_dpcd(dp, 856 DP_TEST_RESPONSE, DP_TEST_EDID_CHECKSUM_WRITE); 857 } 858 } 859 860 return 0; 861 } 862 863 static int analogix_dp_handle_edid(struct analogix_dp_device *dp) 864 { 865 u8 buf[12]; 866 int i, try = 5; 867 int retval; 868 869 retry: 870 /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */ 871 retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf); 872 873 if (retval && try--) { 874 mdelay(10); 875 goto retry; 876 } 877 878 if (retval) 879 return retval; 880 881 /* Read EDID */ 882 for (i = 0; i < 3; i++) { 883 retval = analogix_dp_read_edid(dp); 884 if (!retval) 885 break; 886 } 887 888 return retval; 889 } 890 891 static int analogix_dp_connector_init(struct rockchip_connector *conn, struct display_state *state) 892 { 893 struct connector_state *conn_state = &state->conn_state; 894 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 895 896 conn_state->output_if |= dp->id ? VOP_OUTPUT_IF_eDP1 : VOP_OUTPUT_IF_eDP0; 897 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 898 conn_state->color_encoding = DRM_COLOR_YCBCR_BT709; 899 conn_state->color_range = DRM_COLOR_YCBCR_FULL_RANGE; 900 901 reset_assert_bulk(&dp->resets); 902 udelay(1); 903 reset_deassert_bulk(&dp->resets); 904 905 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dp->id); 906 generic_phy_set_mode(&dp->phy, PHY_MODE_DP); 907 generic_phy_power_on(&dp->phy); 908 analogix_dp_init_dp(dp); 909 910 return 0; 911 } 912 913 static int analogix_dp_connector_get_edid(struct rockchip_connector *conn, 914 struct display_state *state) 915 { 916 struct connector_state *conn_state = &state->conn_state; 917 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 918 int ret; 919 920 ret = analogix_dp_handle_edid(dp); 921 if (ret) { 922 dev_err(dp->dev, "failed to get edid\n"); 923 return ret; 924 } 925 926 memcpy(&conn_state->edid, &dp->edid, sizeof(dp->edid)); 927 928 return 0; 929 } 930 931 static int analogix_dp_link_power_up(struct analogix_dp_device *dp) 932 { 933 u8 value; 934 int ret; 935 936 if (dp->dpcd[DP_DPCD_REV] < 0x11) 937 return 0; 938 939 ret = analogix_dp_read_byte_from_dpcd(dp, DP_SET_POWER, &value); 940 if (ret < 0) 941 return ret; 942 943 value &= ~DP_SET_POWER_MASK; 944 value |= DP_SET_POWER_D0; 945 946 ret = analogix_dp_write_byte_to_dpcd(dp, DP_SET_POWER, value); 947 if (ret < 0) 948 return ret; 949 950 mdelay(1); 951 952 return 0; 953 } 954 955 static int analogix_dp_link_power_down(struct analogix_dp_device *dp) 956 { 957 u8 value; 958 int ret; 959 960 if (dp->dpcd[DP_DPCD_REV] < 0x11) 961 return 0; 962 963 ret = analogix_dp_read_byte_from_dpcd(dp, DP_SET_POWER, &value); 964 if (ret < 0) 965 return ret; 966 967 value &= ~DP_SET_POWER_MASK; 968 value |= DP_SET_POWER_D3; 969 970 ret = analogix_dp_write_byte_to_dpcd(dp, DP_SET_POWER, value); 971 if (ret < 0) 972 return ret; 973 974 return 0; 975 } 976 977 static int analogix_dp_connector_enable(struct rockchip_connector *conn, 978 struct display_state *state) 979 { 980 struct connector_state *conn_state = &state->conn_state; 981 struct crtc_state *crtc_state = &state->crtc_state; 982 const struct rockchip_dp_chip_data *pdata = 983 (const struct rockchip_dp_chip_data *)dev_get_driver_data(conn->dev); 984 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 985 struct video_info *video = &dp->video_info; 986 struct drm_display_mode mode; 987 u32 val; 988 int ret; 989 990 drm_mode_copy(&video->mode, &conn_state->mode); 991 992 if (pdata->lcdsel_grf_reg) { 993 if (crtc_state->crtc_id) 994 val = pdata->lcdsel_lit; 995 else 996 val = pdata->lcdsel_big; 997 998 regmap_write(dp->grf, pdata->lcdsel_grf_reg, val); 999 } 1000 1001 if (pdata->chip_type == RK3588_EDP) 1002 regmap_write(dp->grf, dp->id ? RK3588_GRF_VO1_CON1 : RK3588_GRF_VO1_CON0, 1003 EDP_MODE << 16 | FIELD_PREP(EDP_MODE, 1)); 1004 1005 video->bpc = conn_state->bpc; 1006 switch (video->bpc) { 1007 case 12: 1008 video->color_depth = COLOR_12; 1009 break; 1010 case 10: 1011 video->color_depth = COLOR_10; 1012 break; 1013 case 6: 1014 video->color_depth = COLOR_6; 1015 break; 1016 case 8: 1017 default: 1018 video->color_depth = COLOR_8; 1019 break; 1020 } 1021 1022 ret = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 1023 DP_RECEIVER_CAP_SIZE, dp->dpcd); 1024 if (ret) { 1025 dev_err(dp->dev, "failed to read dpcd caps: %d\n", ret); 1026 return ret; 1027 } 1028 1029 ret = analogix_dp_link_power_up(dp); 1030 if (ret) { 1031 dev_err(dp->dev, "failed to power up link: %d\n", ret); 1032 return ret; 1033 } 1034 1035 ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count, 1036 dp->video_info.max_link_rate); 1037 if (ret) { 1038 dev_err(dp->dev, "unable to do link train\n"); 1039 return ret; 1040 } 1041 1042 analogix_dp_enable_scramble(dp, 1); 1043 analogix_dp_enable_rx_to_enhanced_mode(dp, 1); 1044 analogix_dp_enable_enhanced_mode(dp, 1); 1045 1046 analogix_dp_init_video(dp); 1047 1048 drm_mode_copy(&mode, &conn_state->mode); 1049 if (conn->dual_channel_mode) 1050 drm_mode_convert_to_origin_mode(&mode); 1051 analogix_dp_set_video_format(dp, &mode); 1052 1053 if (dp->video_bist_enable) 1054 analogix_dp_video_bist_enable(dp); 1055 1056 ret = analogix_dp_config_video(dp); 1057 if (ret) { 1058 dev_err(dp->dev, "unable to config video\n"); 1059 return ret; 1060 } 1061 1062 return 0; 1063 } 1064 1065 static int analogix_dp_connector_disable(struct rockchip_connector *conn, 1066 struct display_state *state) 1067 { 1068 const struct rockchip_dp_chip_data *pdata = 1069 (const struct rockchip_dp_chip_data *)dev_get_driver_data(conn->dev); 1070 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 1071 1072 if (!analogix_dp_get_plug_in_status(dp)) 1073 analogix_dp_link_power_down(dp); 1074 1075 if (pdata->chip_type == RK3588_EDP) 1076 regmap_write(dp->grf, dp->id ? RK3588_GRF_VO1_CON1 : RK3588_GRF_VO1_CON0, 1077 EDP_MODE << 16 | FIELD_PREP(EDP_MODE, 0)); 1078 1079 return 0; 1080 } 1081 1082 static int analogix_dp_connector_detect(struct rockchip_connector *conn, 1083 struct display_state *state) 1084 { 1085 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 1086 1087 return analogix_dp_detect(dp); 1088 } 1089 1090 static int analogix_dp_connector_mode_valid(struct rockchip_connector *conn, 1091 struct display_state *state) 1092 { 1093 struct connector_state *conn_state = &state->conn_state; 1094 struct videomode vm; 1095 1096 drm_display_mode_to_videomode(&conn_state->mode, &vm); 1097 1098 if (!vm.hfront_porch || !vm.hback_porch || !vm.vfront_porch || !vm.vback_porch) { 1099 dev_err(dp->dev, "front porch or back porch can not be 0\n"); 1100 return MODE_BAD; 1101 } 1102 1103 return MODE_OK; 1104 } 1105 1106 static const struct rockchip_connector_funcs analogix_dp_connector_funcs = { 1107 .init = analogix_dp_connector_init, 1108 .get_edid = analogix_dp_connector_get_edid, 1109 .enable = analogix_dp_connector_enable, 1110 .disable = analogix_dp_connector_disable, 1111 .detect = analogix_dp_connector_detect, 1112 .mode_valid = analogix_dp_connector_mode_valid, 1113 }; 1114 1115 static u32 analogix_dp_parse_link_frequencies(struct analogix_dp_device *dp) 1116 { 1117 struct udevice *dev = dp->dev; 1118 const struct device_node *endpoint; 1119 u64 frequency = 0; 1120 1121 endpoint = rockchip_of_graph_get_endpoint_by_regs(dev->node, 1, 0); 1122 if (!endpoint) 1123 return 0; 1124 1125 if (of_property_read_u64(endpoint, "link-frequencies", &frequency) < 0) 1126 return 0; 1127 1128 if (!frequency) 1129 return 0; 1130 1131 do_div(frequency, 10 * 1000); /* symbol rate kbytes */ 1132 1133 switch (frequency) { 1134 case 162000: 1135 case 270000: 1136 case 540000: 1137 break; 1138 default: 1139 dev_err(dev, "invalid link frequency value: %llu\n", frequency); 1140 return 0; 1141 } 1142 1143 return frequency; 1144 } 1145 1146 static int analogix_dp_parse_dt(struct analogix_dp_device *dp) 1147 { 1148 struct udevice *dev = dp->dev; 1149 int len; 1150 u32 num_lanes; 1151 u32 max_link_rate; 1152 int ret; 1153 1154 dp->force_hpd = dev_read_bool(dev, "force-hpd"); 1155 dp->video_bist_enable = dev_read_bool(dev, "analogix,video-bist-enable"); 1156 dp->video_info.force_stream_valid = 1157 dev_read_bool(dev, "analogix,force-stream-valid"); 1158 1159 max_link_rate = analogix_dp_parse_link_frequencies(dp); 1160 if (max_link_rate && max_link_rate < drm_dp_bw_code_to_link_rate(dp->video_info.max_link_rate)) 1161 dp->video_info.max_link_rate = drm_dp_link_rate_to_bw_code(max_link_rate); 1162 1163 if (dev_read_prop(dev, "data-lanes", &len)) { 1164 num_lanes = len / sizeof(u32); 1165 if (num_lanes < 1 || num_lanes > 4 || num_lanes == 3) { 1166 dev_err(dev, "bad number of data lanes\n"); 1167 return -EINVAL; 1168 } 1169 1170 ret = dev_read_u32_array(dev, "data-lanes", dp->lane_map, 1171 num_lanes); 1172 if (ret) 1173 return ret; 1174 1175 dp->video_info.max_lane_count = num_lanes; 1176 } else { 1177 dp->lane_map[0] = 0; 1178 dp->lane_map[1] = 1; 1179 dp->lane_map[2] = 2; 1180 dp->lane_map[3] = 3; 1181 } 1182 1183 return 0; 1184 } 1185 1186 static int analogix_dp_probe(struct udevice *dev) 1187 { 1188 struct analogix_dp_device *dp = dev_get_priv(dev); 1189 const struct rockchip_dp_chip_data *pdata = 1190 (const struct rockchip_dp_chip_data *)dev_get_driver_data(dev); 1191 struct udevice *syscon; 1192 int ret; 1193 1194 dp->reg_base = dev_read_addr_ptr(dev); 1195 1196 dp->id = of_alias_get_id(ofnode_to_np(dev->node), "edp"); 1197 if (dp->id < 0) 1198 dp->id = 0; 1199 1200 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 1201 &syscon); 1202 if (!ret) { 1203 dp->grf = syscon_get_regmap(syscon); 1204 if (!dp->grf) 1205 return -ENODEV; 1206 } 1207 1208 ret = reset_get_bulk(dev, &dp->resets); 1209 if (ret) { 1210 dev_err(dev, "failed to get reset control: %d\n", ret); 1211 return ret; 1212 } 1213 1214 ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio, 1215 GPIOD_IS_IN); 1216 if (ret && ret != -ENOENT) { 1217 dev_err(dev, "failed to get hpd GPIO: %d\n", ret); 1218 return ret; 1219 } 1220 1221 generic_phy_get_by_name(dev, "dp", &dp->phy); 1222 1223 dp->plat_data.dev_type = ROCKCHIP_DP; 1224 dp->plat_data.subdev_type = pdata->chip_type; 1225 dp->plat_data.ssc = pdata->ssc; 1226 1227 dp->video_info.max_link_rate = pdata->max_link_rate; 1228 dp->video_info.max_lane_count = pdata->max_lane_count; 1229 1230 dp->dev = dev; 1231 1232 ret = analogix_dp_parse_dt(dp); 1233 if (ret) { 1234 dev_err(dev, "failed to parse DT: %d\n", ret); 1235 return ret; 1236 } 1237 1238 rockchip_connector_bind(&dp->connector, dev, dp->id, &analogix_dp_connector_funcs, 1239 NULL, DRM_MODE_CONNECTOR_eDP); 1240 1241 return 0; 1242 } 1243 1244 static const struct rockchip_dp_chip_data rk3288_edp_platform_data = { 1245 .lcdsel_grf_reg = 0x025c, 1246 .lcdsel_big = 0 | BIT(21), 1247 .lcdsel_lit = BIT(5) | BIT(21), 1248 .chip_type = RK3288_DP, 1249 1250 .max_link_rate = DP_LINK_BW_2_7, 1251 .max_lane_count = 4, 1252 }; 1253 1254 static const struct rockchip_dp_chip_data rk3368_edp_platform_data = { 1255 .chip_type = RK3368_EDP, 1256 1257 .max_link_rate = DP_LINK_BW_2_7, 1258 .max_lane_count = 4, 1259 }; 1260 1261 static const struct rockchip_dp_chip_data rk3399_edp_platform_data = { 1262 .lcdsel_grf_reg = 0x6250, 1263 .lcdsel_big = 0 | BIT(21), 1264 .lcdsel_lit = BIT(5) | BIT(21), 1265 .chip_type = RK3399_EDP, 1266 .ssc = true, 1267 1268 .max_link_rate = DP_LINK_BW_5_4, 1269 .max_lane_count = 4, 1270 }; 1271 1272 static const struct rockchip_dp_chip_data rk3568_edp_platform_data = { 1273 .chip_type = RK3568_EDP, 1274 .ssc = true, 1275 1276 .max_link_rate = DP_LINK_BW_2_7, 1277 .max_lane_count = 4, 1278 }; 1279 1280 static const struct rockchip_dp_chip_data rk3576_edp_platform_data = { 1281 .chip_type = RK3576_EDP, 1282 .ssc = true, 1283 1284 .max_link_rate = DP_LINK_BW_5_4, 1285 .max_lane_count = 4, 1286 }; 1287 1288 static const struct rockchip_dp_chip_data rk3588_edp_platform_data = { 1289 .chip_type = RK3588_EDP, 1290 .ssc = true, 1291 1292 .max_link_rate = DP_LINK_BW_5_4, 1293 .max_lane_count = 4, 1294 }; 1295 1296 static const struct udevice_id analogix_dp_ids[] = { 1297 { 1298 .compatible = "rockchip,rk3288-dp", 1299 .data = (ulong)&rk3288_edp_platform_data, 1300 }, { 1301 .compatible = "rockchip,rk3368-edp", 1302 .data = (ulong)&rk3368_edp_platform_data, 1303 }, { 1304 .compatible = "rockchip,rk3399-edp", 1305 .data = (ulong)&rk3399_edp_platform_data, 1306 }, { 1307 .compatible = "rockchip,rk3568-edp", 1308 .data = (ulong)&rk3568_edp_platform_data, 1309 }, { 1310 .compatible = "rockchip,rk3576-edp", 1311 .data = (ulong)&rk3576_edp_platform_data, 1312 }, { 1313 .compatible = "rockchip,rk3588-edp", 1314 .data = (ulong)&rk3588_edp_platform_data, 1315 }, 1316 {} 1317 }; 1318 1319 U_BOOT_DRIVER(analogix_dp) = { 1320 .name = "analogix_dp", 1321 .id = UCLASS_DISPLAY, 1322 .of_match = analogix_dp_ids, 1323 .probe = analogix_dp_probe, 1324 .priv_auto_alloc_size = sizeof(struct analogix_dp_device), 1325 }; 1326