1 /* 2 * SPDX-License-Identifier: GPL-2.0+ 3 * 4 * (C) Copyright 2023 Rockchip Electronics Co., Ltd 5 */ 6 7 #include <common.h> 8 #include <dwc3-uboot.h> 9 #include <usb.h> 10 #include <linux/usb/phy-rockchip-usbdp.h> 11 #include <asm/io.h> 12 #include <rockusb.h> 13 14 DECLARE_GLOBAL_DATA_PTR; 15 16 #ifdef CONFIG_USB_DWC3 17 #define CRU_BASE 0x27200000 18 #define CRU_SOFTRST_CON47 0x0abc 19 20 static struct dwc3_device dwc3_device_data = { 21 .maximum_speed = USB_SPEED_SUPER, 22 .base = 0x23000000, 23 .dr_mode = USB_DR_MODE_PERIPHERAL, 24 .index = 0, 25 .dis_u2_susphy_quirk = 1, 26 .dis_u1u2_quirk = 1, 27 .usb2_phyif_utmi_width = 16, 28 }; 29 30 int usb_gadget_handle_interrupts(int index) 31 { 32 dwc3_uboot_handle_interrupt(0); 33 return 0; 34 } 35 36 bool rkusb_usb3_capable(void) 37 { 38 return true; 39 } 40 41 static void usb_reset_otg_controller(void) 42 { 43 writel(0x00200020, CRU_BASE + CRU_SOFTRST_CON47); 44 mdelay(1); 45 writel(0x00200000, CRU_BASE + CRU_SOFTRST_CON47); 46 mdelay(1); 47 } 48 49 int board_usb_init(int index, enum usb_init_type init) 50 { 51 u32 ret = 0; 52 53 usb_reset_otg_controller(); 54 55 #if defined(CONFIG_SUPPORT_USBPLUG) 56 dwc3_device_data.maximum_speed = USB_SPEED_HIGH; 57 58 if (rkusb_switch_usb3_enabled()) { 59 dwc3_device_data.maximum_speed = USB_SPEED_SUPER; 60 ret = rockchip_u3phy_uboot_init(); 61 if (ret) { 62 rkusb_force_to_usb2(true); 63 dwc3_device_data.maximum_speed = USB_SPEED_HIGH; 64 } 65 } 66 #else 67 ret = rockchip_u3phy_uboot_init(); 68 if (ret) { 69 rkusb_force_to_usb2(true); 70 dwc3_device_data.maximum_speed = USB_SPEED_HIGH; 71 } 72 #endif 73 74 return dwc3_uboot_init(&dwc3_device_data); 75 } 76 77 #if defined(CONFIG_SUPPORT_USBPLUG) 78 int board_usb_cleanup(int index, enum usb_init_type init) 79 { 80 dwc3_uboot_exit(index); 81 return 0; 82 } 83 #endif 84 85 #endif 86