1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2020 Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <dm.h> 8 #include <dm/pinctrl.h> 9 #include <regmap.h> 10 #include <syscon.h> 11 12 #include "pinctrl-rockchip.h" 13 14 static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = { 15 { 16 .num = 0, 17 .pin = 20, 18 .reg = 0x10000, 19 .bit = 0, 20 .mask = 0xf 21 }, 22 { 23 .num = 0, 24 .pin = 21, 25 .reg = 0x10000, 26 .bit = 4, 27 .mask = 0xf 28 }, 29 { 30 .num = 0, 31 .pin = 22, 32 .reg = 0x10000, 33 .bit = 8, 34 .mask = 0xf 35 }, 36 { 37 .num = 0, 38 .pin = 23, 39 .reg = 0x10000, 40 .bit = 12, 41 .mask = 0xf 42 }, 43 }; 44 45 static struct rockchip_mux_route_data rv1126_mux_route_data[] = { 46 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x10260, RK_GENMASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */ 47 MR_TOPGRF(RK_GPIO3, RK_PB0, RK_FUNC_3, 0x10260, RK_GENMASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */ 48 49 MR_TOPGRF(RK_GPIO0, RK_PD4, RK_FUNC_4, 0x10260, RK_GENMASK_VAL(2, 3, 0)), /* I2S1_MCLK_M0 */ 50 MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x10260, RK_GENMASK_VAL(2, 3, 1)), /* I2S1_MCLK_M1 */ 51 MR_TOPGRF(RK_GPIO2, RK_PC7, RK_FUNC_6, 0x10260, RK_GENMASK_VAL(2, 3, 2)), /* I2S1_MCLK_M2 */ 52 53 MR_TOPGRF(RK_GPIO1, RK_PD0, RK_FUNC_1, 0x10260, RK_GENMASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */ 54 MR_TOPGRF(RK_GPIO2, RK_PB3, RK_FUNC_2, 0x10260, RK_GENMASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */ 55 56 MR_TOPGRF(RK_GPIO3, RK_PD4, RK_FUNC_2, 0x10260, RK_GENMASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */ 57 MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_3, 0x10260, RK_GENMASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */ 58 59 MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_1, 0x10264, RK_GENMASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */ 60 MR_TOPGRF(RK_GPIO2, RK_PD1, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */ 61 62 MR_TOPGRF(RK_GPIO3, RK_PA4, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(4, 5, 0)), /* I2C3_SCL_M0 */ 63 MR_TOPGRF(RK_GPIO2, RK_PD4, RK_FUNC_7, 0x10264, RK_GENMASK_VAL(4, 5, 1)), /* I2C3_SCL_M1 */ 64 MR_TOPGRF(RK_GPIO1, RK_PD6, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(4, 5, 2)), /* I2C3_SCL_M2 */ 65 66 MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_7, 0x10264, RK_GENMASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */ 67 MR_TOPGRF(RK_GPIO4, RK_PA0, RK_FUNC_4, 0x10264, RK_GENMASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */ 68 69 MR_TOPGRF(RK_GPIO2, RK_PA5, RK_FUNC_7, 0x10264, RK_GENMASK_VAL(8, 9, 0)), /* I2C5_SCL_M0 */ 70 MR_TOPGRF(RK_GPIO3, RK_PB0, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(8, 9, 1)), /* I2C5_SCL_M1 */ 71 MR_TOPGRF(RK_GPIO1, RK_PD0, RK_FUNC_4, 0x10264, RK_GENMASK_VAL(8, 9, 2)), /* I2C5_SCL_M2 */ 72 73 MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(10, 11, 0)), /* SPI1_CLK_M0 */ 74 MR_TOPGRF(RK_GPIO1, RK_PC6, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(10, 11, 1)), /* SPI1_CLK_M1 */ 75 MR_TOPGRF(RK_GPIO2, RK_PD5, RK_FUNC_6, 0x10264, RK_GENMASK_VAL(10, 11, 2)), /* SPI1_CLK_M2 */ 76 77 MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_2, 0x10264, RK_GENMASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */ 78 MR_TOPGRF(RK_GPIO2, RK_PB7, RK_FUNC_2, 0x10264, RK_GENMASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */ 79 80 MR_TOPGRF(RK_GPIO3, RK_PA1, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */ 81 MR_TOPGRF(RK_GPIO3, RK_PA7, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */ 82 83 MR_TOPGRF(RK_GPIO3, RK_PA4, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(0, 0, 0)), /* PWM8_M0 */ 84 MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(0, 0, 1)), /* PWM8_M1 */ 85 86 MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(2, 2, 0)), /* PWM9_M0 */ 87 MR_TOPGRF(RK_GPIO2, RK_PD6, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(2, 2, 1)), /* PWM9_M1 */ 88 89 MR_TOPGRF(RK_GPIO3, RK_PA6, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(4, 4, 0)), /* PWM10_M0 */ 90 MR_TOPGRF(RK_GPIO2, RK_PD5, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(4, 4, 1)), /* PWM10_M1 */ 91 92 MR_TOPGRF(RK_GPIO3, RK_PA7, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */ 93 MR_TOPGRF(RK_GPIO3, RK_PA1, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */ 94 95 MR_TOPGRF(RK_GPIO1, RK_PA5, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(8, 8, 0)), /* UART2_TX_M0 */ 96 MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_1, 0x10268, RK_GENMASK_VAL(8, 8, 1)), /* UART2_TX_M1 */ 97 98 MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(10, 11, 0)), /* UART3_TX_M0 */ 99 MR_TOPGRF(RK_GPIO1, RK_PA7, RK_FUNC_2, 0x10268, RK_GENMASK_VAL(10, 11, 1)), /* UART3_TX_M1 */ 100 MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(10, 11, 2)), /* UART3_TX_M2 */ 101 102 MR_TOPGRF(RK_GPIO3, RK_PA4, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(12, 13, 0)), /* UART4_TX_M0 */ 103 MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(12, 13, 1)), /* UART4_TX_M1 */ 104 MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(12, 13, 2)), /* UART4_TX_M2 */ 105 106 MR_TOPGRF(RK_GPIO3, RK_PA6, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(14, 15, 0)), /* UART5_TX_M0 */ 107 MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(14, 15, 1)), /* UART5_TX_M1 */ 108 MR_TOPGRF(RK_GPIO2, RK_PA0, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(14, 15, 2)), /* UART5_TX_M2 */ 109 110 MR_PMUGRF(RK_GPIO0, RK_PB6, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(0, 0, 0)), /* PWM0_M0 */ 111 MR_PMUGRF(RK_GPIO2, RK_PB3, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(0, 0, 1)), /* PWM0_M1 */ 112 113 MR_PMUGRF(RK_GPIO0, RK_PB7, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(2, 2, 0)), /* PWM1_M0 */ 114 MR_PMUGRF(RK_GPIO2, RK_PB2, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(2, 2, 1)), /* PWM1_M1 */ 115 116 MR_PMUGRF(RK_GPIO0, RK_PC0, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(4, 4, 0)), /* PWM2_M0 */ 117 MR_PMUGRF(RK_GPIO2, RK_PB1, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(4, 4, 1)), /* PWM2_M1 */ 118 119 MR_PMUGRF(RK_GPIO0, RK_PC1, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */ 120 MR_PMUGRF(RK_GPIO2, RK_PB0, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */ 121 122 MR_PMUGRF(RK_GPIO0, RK_PC2, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(8, 8, 0)), /* PWM4_M0 */ 123 MR_PMUGRF(RK_GPIO2, RK_PA7, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(8, 8, 1)), /* PWM4_M1 */ 124 125 MR_PMUGRF(RK_GPIO0, RK_PC3, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(10, 10, 0)), /* PWM5_M0 */ 126 MR_PMUGRF(RK_GPIO2, RK_PA6, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(10, 10, 1)), /* PWM5_M1 */ 127 128 MR_PMUGRF(RK_GPIO0, RK_PB2, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(12, 12, 0)), /* PWM6_M0 */ 129 MR_PMUGRF(RK_GPIO2, RK_PD4, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(12, 12, 1)), /* PWM6_M1 */ 130 131 MR_PMUGRF(RK_GPIO0, RK_PB1, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */ 132 MR_PMUGRF(RK_GPIO3, RK_PA0, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */ 133 134 MR_PMUGRF(RK_GPIO0, RK_PB0, RK_FUNC_1, 0x0118, RK_GENMASK_VAL(0, 1, 0)), /* SPI0_CLK_M0 */ 135 MR_PMUGRF(RK_GPIO2, RK_PA1, RK_FUNC_1, 0x0118, RK_GENMASK_VAL(0, 1, 1)), /* SPI0_CLK_M1 */ 136 MR_PMUGRF(RK_GPIO2, RK_PB2, RK_FUNC_6, 0x0118, RK_GENMASK_VAL(0, 1, 2)), /* SPI0_CLK_M2 */ 137 138 MR_PMUGRF(RK_GPIO0, RK_PB6, RK_FUNC_2, 0x0118, RK_GENMASK_VAL(2, 2, 0)), /* UART1_TX_M0 */ 139 MR_PMUGRF(RK_GPIO1, RK_PD0, RK_FUNC_5, 0x0118, RK_GENMASK_VAL(2, 2, 1)), /* UART1_TX_M1 */ 140 }; 141 142 static int rv1126_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 143 { 144 struct rockchip_pinctrl_priv *priv = bank->priv; 145 int iomux_num = (pin / 8); 146 struct regmap *regmap; 147 int reg, ret, mask, mux_type; 148 u8 bit; 149 u32 data; 150 151 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 152 153 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 154 regmap = priv->regmap_pmu; 155 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) 156 regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base; 157 else 158 regmap = priv->regmap_base; 159 160 /* get basic quadrupel of mux registers and the correct reg inside */ 161 mux_type = bank->iomux[iomux_num].type; 162 reg = bank->iomux[iomux_num].offset; 163 if (mux_type & IOMUX_WIDTH_4BIT) { 164 if ((pin % 8) >= 4) 165 reg += 0x4; 166 bit = (pin % 4) * 4; 167 mask = 0xf; 168 } else { 169 bit = (pin % 8) * 2; 170 mask = 0x3; 171 } 172 173 if (bank->recalced_mask & BIT(pin)) 174 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 175 176 data = (mask << (bit + 16)); 177 data |= (mux & mask) << bit; 178 ret = regmap_write(regmap, reg, data); 179 180 return ret; 181 } 182 183 #define RV1126_PULL_PMU_OFFSET 0x40 184 #define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108 185 #define RV1126_PULL_PINS_PER_REG 8 186 #define RV1126_PULL_BITS_PER_PIN 2 187 #define RV1126_PULL_BANK_STRIDE 16 188 #define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */ 189 190 static void rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 191 int pin_num, struct regmap **regmap, 192 int *reg, u8 *bit) 193 { 194 struct rockchip_pinctrl_priv *priv = bank->priv; 195 196 /* The first 24 pins of the first bank are located in PMU */ 197 if (bank->bank_num == 0) { 198 if (RV1126_GPIO_C4_D7(pin_num)) { 199 *regmap = priv->regmap_base; 200 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET; 201 *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4); 202 *bit = pin_num % RV1126_PULL_PINS_PER_REG; 203 *bit *= RV1126_PULL_BITS_PER_PIN; 204 return; 205 } 206 *regmap = priv->regmap_pmu; 207 *reg = RV1126_PULL_PMU_OFFSET; 208 } else { 209 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET; 210 *regmap = priv->regmap_base; 211 *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE; 212 } 213 214 *reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4); 215 *bit = (pin_num % RV1126_PULL_PINS_PER_REG); 216 *bit *= RV1126_PULL_BITS_PER_PIN; 217 } 218 219 static int rv1126_set_pull(struct rockchip_pin_bank *bank, 220 int pin_num, int pull) 221 { 222 struct regmap *regmap; 223 int reg, ret; 224 u8 bit, type; 225 u32 data; 226 227 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) 228 return -ENOTSUPP; 229 230 rv1126_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); 231 type = bank->pull_type[pin_num / 8]; 232 ret = rockchip_translate_pull_value(type, pull); 233 if (ret < 0) { 234 debug("unsupported pull setting %d\n", pull); 235 return ret; 236 } 237 238 /* enable the write to the equivalent lower bits */ 239 data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); 240 241 data |= (ret << bit); 242 ret = regmap_write(regmap, reg, data); 243 244 return ret; 245 } 246 247 #define RV1126_DRV_PMU_OFFSET 0x20 248 #define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090 249 #define RV1126_DRV_BITS_PER_PIN 4 250 #define RV1126_DRV_PINS_PER_REG 4 251 #define RV1126_DRV_BANK_STRIDE 32 252 253 static void rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 254 int pin_num, struct regmap **regmap, 255 int *reg, u8 *bit) 256 { 257 struct rockchip_pinctrl_priv *priv = bank->priv; 258 259 /* The first 24 pins of the first bank are located in PMU */ 260 if (bank->bank_num == 0) { 261 if (RV1126_GPIO_C4_D7(pin_num)) { 262 *regmap = priv->regmap_base; 263 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET; 264 *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4); 265 *reg -= 0x4; 266 *bit = pin_num % RV1126_DRV_PINS_PER_REG; 267 *bit *= RV1126_DRV_BITS_PER_PIN; 268 return; 269 } 270 *regmap = priv->regmap_pmu; 271 *reg = RV1126_DRV_PMU_OFFSET; 272 } else { 273 *regmap = priv->regmap_base; 274 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET; 275 *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE; 276 } 277 278 *reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4); 279 *bit = pin_num % RV1126_DRV_PINS_PER_REG; 280 *bit *= RV1126_DRV_BITS_PER_PIN; 281 } 282 283 static int rv1126_set_drive(struct rockchip_pin_bank *bank, 284 int pin_num, int strength) 285 { 286 struct regmap *regmap; 287 int reg; 288 u32 data; 289 u8 bit; 290 291 rv1126_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); 292 293 /* enable the write to the equivalent lower bits */ 294 data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16); 295 data |= (strength << bit); 296 297 return regmap_write(regmap, reg, data); 298 } 299 300 #define RV1126_SCHMITT_PMU_OFFSET 0x60 301 #define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188 302 #define RV1126_SCHMITT_BANK_STRIDE 16 303 #define RV1126_SCHMITT_PINS_PER_GRF_REG 8 304 #define RV1126_SCHMITT_PINS_PER_PMU_REG 8 305 306 static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 307 int pin_num, 308 struct regmap **regmap, 309 int *reg, u8 *bit) 310 { 311 struct rockchip_pinctrl_priv *priv = bank->priv; 312 int pins_per_reg; 313 314 if (bank->bank_num == 0) { 315 if (RV1126_GPIO_C4_D7(pin_num)) { 316 *regmap = priv->regmap_base; 317 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET; 318 *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4); 319 *bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG; 320 return 0; 321 } 322 *regmap = priv->regmap_pmu; 323 *reg = RV1126_SCHMITT_PMU_OFFSET; 324 pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG; 325 } else { 326 *regmap = priv->regmap_base; 327 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET; 328 pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG; 329 *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE; 330 } 331 *reg += ((pin_num / pins_per_reg) * 4); 332 *bit = pin_num % pins_per_reg; 333 334 return 0; 335 } 336 337 static int rv1126_set_schmitt(struct rockchip_pin_bank *bank, 338 int pin_num, int enable) 339 { 340 struct regmap *regmap; 341 int reg; 342 u8 bit; 343 u32 data; 344 345 rv1126_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit); 346 /* enable the write to the equivalent lower bits */ 347 data = BIT(bit + 16) | (enable << bit); 348 349 return regmap_write(regmap, reg, data); 350 } 351 352 static struct rockchip_pin_bank rv1126_pin_banks[] = { 353 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 354 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, 355 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, 356 IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU, 357 IOMUX_WIDTH_4BIT), 358 PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1", 359 IOMUX_WIDTH_4BIT, 360 IOMUX_WIDTH_4BIT, 361 IOMUX_WIDTH_4BIT, 362 IOMUX_WIDTH_4BIT, 363 0x10010, 0x10018, 0x10020, 0x10028), 364 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 365 IOMUX_WIDTH_4BIT, 366 IOMUX_WIDTH_4BIT, 367 IOMUX_WIDTH_4BIT, 368 IOMUX_WIDTH_4BIT), 369 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 370 IOMUX_WIDTH_4BIT, 371 IOMUX_WIDTH_4BIT, 372 IOMUX_WIDTH_4BIT, 373 IOMUX_WIDTH_4BIT), 374 PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4", 375 IOMUX_WIDTH_4BIT, 0, 0, 0), 376 }; 377 378 static const struct rockchip_pin_ctrl rv1126_pin_ctrl = { 379 .pin_banks = rv1126_pin_banks, 380 .nr_banks = ARRAY_SIZE(rv1126_pin_banks), 381 .nr_pins = 130, 382 .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */ 383 .pmu_mux_offset = 0x0, 384 .iomux_routes = rv1126_mux_route_data, 385 .niomux_routes = ARRAY_SIZE(rv1126_mux_route_data), 386 .iomux_recalced = rv1126_mux_recalced_data, 387 .niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data), 388 .set_mux = rv1126_set_mux, 389 .set_pull = rv1126_set_pull, 390 .set_drive = rv1126_set_drive, 391 .set_schmitt = rv1126_set_schmitt, 392 }; 393 394 static const struct udevice_id rv1126_pinctrl_ids[] = { 395 { 396 .compatible = "rockchip,rv1126-pinctrl", 397 .data = (ulong)&rv1126_pin_ctrl 398 }, 399 { } 400 }; 401 402 U_BOOT_DRIVER(pinctrl_rv1126) = { 403 .name = "rockchip_rv1126_pinctrl", 404 .id = UCLASS_PINCTRL, 405 .of_match = rv1126_pinctrl_ids, 406 .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), 407 .ops = &rockchip_pinctrl_ops, 408 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 409 .bind = dm_scan_fdt_dev, 410 #endif 411 .probe = rockchip_pinctrl_probe, 412 }; 413